PT719050E - DEVICE FOR TRANSMITTING RECEIVING AND DECODING AUDIO-VISUAL FLOWS TABLETS - Google Patents

Description

DEVICE FOR TRANSMITTING, RECEIVING AND DECODING FLUXES TO UDIO-VISUAL COMPRESSED " The present invention relates to processing systems for digitized audio and video signals and in particular relates to a device for receiving, transmitting and decoding compressed audio-visual streams arranged in accordance with the international standard ISO / IEC 11172, also known as ISO / MPEG-1. For the sake of simplicity, henceforth these streams will be referred to as streams or MPEG data.

As is well known, MPEG streams are time-division streams wherein, in addition to packets of audio and video sequences, packet sequences relating to data of other types (hereinafter called "private data") are also multiplexed; the latest data is generated by a user and its nature depends entirely on the user himself. The coding of the " bit " in one of said flows has the consequence of forming two layers; an outer layer ("system layer"), which provides the functions necessary to use one or more compressed data streams in a system, and an inner layer ("compression layer") which provides the functions necessary to encode the audio data and video.

An MPEG stream decoder should further comprise a system layer decoding part, to separate the streams into its different components (audio, video and data) and retrieve the information necessary for the synchronization between audio and video components; a video decoding part; and an audio decoding part. The functions assigned to the three decoding parts and their requirements are described in detail in parts 1.2 and 3 respectively of the standard standard.

Devices for decoding MPEG audio-visual streams are already commercially available. In particular the device "CL 450 Development Kit" of the company C-CUBE is a device, which is intended to be connected to a computer

which performs audio and video decoding functions and which also allows the overlapping of the decoded video signal to the output signal of a videographic card so as to allow presentation of the video signal in a window of a graphical application. The functions prescribed by the system layer of the algorithm assigned to a separate program, run by the computer's processing unit. The device has some drawbacks due to this division of tasks between the device itself and the host personal computer. A first drawback is that the device itself can not be used as a stand-alone device since it lacks the essential functions, such as synchronization. In addition, the fact that certain functions are assigned to the computer processing unit delays the computer's operations and penalizes its performance in case it has to perform other operations. Above all, software management and synchronization functions are complex and the results obtained are not excellent.

A device of the same type is also known from the texts of Ackland BD: "The video-codec chip set for multimedia applications", AT & T Technical Journal, Vol. 72, No. 1, January 1, 1993, pages 50 to 66. This device shows only a single communications channel and states the possibility of connecting to a CD-ROM which may be the local source / receiver.

Thus, the known devices are also not very flexible, since they can not be connected directly to different sources, but instead, for this purpose, external interface cards are required to be associated with the controller. Regardless of the difficulty in finding these cards on the market, their use would require the use of " bus " and this would take away resources from other tasks.

The features of the invention are defined in the claims. According to the invention, there is provided a device which can be used as a stand-alone device, as it is equipped with means for performing the functions required by the system layer, or as an expansion of a conventional personal computer and which is equipped with circuits for direct connection to different external data sources. In addition, when used in association with a computer, the device can perform decoding functions and can be connected to external sources without removing processing resources from the computer itself. Accordingly, the advantages of the present invention over the prior art reside

substantially in the great flexibility inherent in the structure of the interface means! and therefore to the type of sources to which the devices can be connected.

For the sake of clarity, reference is made to the accompanying drawings in which: Figure 1 is a block diagram of the device according to the present invention; Figure 2 is a block diagram of a demultiplexing and synchronizing circuit (DES block in Figure 1); Figure 3 is a representation of the organization of the data according to the MPEG-1 standard; Figure 4 is a logical diagram of the data flow through the demultiplexing and synchronization circuit; Figure 5 is a logical diagram of the grammar analyzer included in the demultiplexing and synchronization circuit (PA block in Figure 2); - Figures 6 to 9 are flowcharts of grammar analyzer operations; Figures 10 to 19 are more detailed diagrams of other units in the demultiplexing and synchronization circuit.

Before the structure of the device according to the present invention is illustrated, the functions it has to perform are briefly summarized. The device must be capable of receiving MPEG audio-visual streams from multiple sources, in particular: from the hard drive of a computer. conventional personnel from which the device may constitute an expansion to provide the processing power necessary to decode these audio-visual streams in real time; of a local digital storage device; of a remote digital storage device or of an encoder through a telecommunications network. For this purpose, the necessary interfaces are incorporated into the device. The device processes the demultiplexing of the audio and video information from a received stream, decodes it and provides the user, synchronously, with high quality motion video images and audio signals of the same quality as those of the stereo compact discs. In the decoding process, strategies are also put in place to eliminate the effects of transmission errors. In addition, the decoded video images may be mixed in real time with output signals from a conventional computer graphics adapter and shown in a window on the computer monitor. The device, which is embodied on a board, may be pre-programmed and may act as a stand-alone device with the aid of a controller present on the board, or may be programmable from an external controller (e.g., a personal computer). The attached drawing illustrates, by way of example, an external CNT controller and the description refers, in a more general manner, to the case where the device is programmable.

In addition to performing the receive and decode functions, the device may also function as a storage device or as a transmitter (or playback unit) of MPEG streams. 'The device can be used in applications such as access to multimedia information databases, video-on-demand services, etc.

All said, as can be seen in Figure 1, the device, generally indicated as DEC, comprises: - a section for connection to sources (or receivers, depending on the mode of operation) of MPEG streams; this section is made up of the following components: CSC to control the transfer of data in a " bus " 1 for connection to conventional peripheral computer units; IA for connection to a first bidirectional serial line 2 in which the data transfer occurs asynchronously; CIS for connection to a second bidirectional serial line 3 in which the data transfer occurs in synchronized mode; - a demultiplexing and synchronizing circuit DES, associated with an external memory MT, intended, on the one hand, to a temporary storage of the streams to be demultiplexed and decoded and, on the other hand, for the temporary storage of the demultiplexed audio and video streams and private data to be sent, respectively, to the decoders or to the controller; - a section for sending audio and video data, which comprises the DA decoders, DV and circuits to provide the users with decoded data and to mix video signals and decoded graphic signals. The device also comprises a " bus " input E and a " bus " output U connected to the " bus " 4 of the CNT cxtcmo controller. To simplify the drawing, in the " bus " E, U, 4 the yarn groups destined to the transfer of data were not distinguished from those destined to command and / or transfer of address. Regarding data transfer, " bus " are, for example, " bus " of 16 " bits ". &Quot; bus " E is used for the exchange of information (data, commands ...) between IA and CSC, on the one hand, and for the DES circuit of demultiplexing and synchronization, on the other hand, for the transfer of private data included in the MPEG stream of the DES for the external controller, and for programming the DES by the external CNT controller. Other commands and programming information are sent to CSC and CIS via " bus " 4. In contrast the CIS is directly connected to the demultiplexing and DES synchronization circuit via an additional serial line 6. The " bus " U is used to transfer the respective streams to be decoded to DA and DV audio and video decoders and to program the decoders themselves. The two " bus " E, U are connected to " bus " 4 by appropriate drive circuits PE, PU, controlled (by signals sent by a connection 5) by the DES circuit, in order to avoid access conflicts of " bus " components. To simplify the design, blocks IA, CIS, CSC, DES also include the drive circuits that may be required to. connect them to the connections that lead them and the decoding circuits to the signals that allow the CNT to have access to the different blocks.

Turning to the different blocks constituting the DEC decoder, the CSC unit is a conventional control unit of a Small Computer System Interface (SCSI) for reading and writing MPEG data only to and from a peripheral unit (for example, a device local MEL storage device) attached to the " bus " 1. The CSC unit is attached to both the " bus " And for MPEG data transfer, with " bus " 4 of the external controller to be programmed by the controller. For example, the CSC unit is performed by means of the AM53C94 component marketed by Advanced Micro Devices. The features and operating modes of this component are not influenced by the present invention and are reported in the component data sheets.

interface of the DEC decoder with the asynchronous serial line 2 that can carry data from an MPEG encoder or from a remote memory device, for example through a DECR remote decoding device identical to the DEC. The interface IA is a circuit which essentially acts as a protocol converter, which transforms the bidirectional serial line 2 into a pair of parallel ports, one for signal input and the other for signal output, connected to the " bus " The LA interface can be performed, for example, by the COll component manufactured by INMOS. The features and modes of operation of this component are not influenced by the present invention and are reported in the data sheets of the components. The CIS unit is intended to interface the DEC device with the synchronous serial line 3 which, analogously to line 2, allows connection to the remote device DECR. Line 3 is intended to carry data transmitted, for example, according to the protocols established by CCITT Recommendations G.703, G.704 for the physical layer and frame structure. In this case, line 3 is, for example, a 2 Mbit / s line where the transmission takes place according to a High Layer Data Link Control (HDLC) protocol, superimposed on a 32-bit 64 kbit / s. The data transmitted on line 3 may comprise, in addition to the MPEG data, also data relating to still images, subtitles, text and graphics and, in general, data and commands that can not be inserted into MPEG streams. The latest data and commands are exchanged in the form of messages whose flow is regulated by appropriate control signals provided by DES. The local decoder DEC and the remote decoder also exchange, through the same line, the acknowledged reception signals prescribed by the data transfer protocols. The CIS interface can, for example, be realized by the PCMSC component V7311, manufactured by Italtel. The features and operating modes of this component are not influenced by the present invention and are reported in the component data sheets.

When the device acts as a decoder, any of the above mentioned interfaces can receive data and send them to the DES circuit for demultiplexing. When the device acts as an MPEG stream transmitter,

controllers and are provided to the CIS interface to be sent along line 3 towards the DEC device associated with the receiver; through the CIS interface the device may also receive and transmit non-MPEG data as mentioned above. When the device acts as a storage device, it will be able to receive and transmit data (MPEG or non-MPEG) via the CIS: the received data is sent to the CNT controller and the data to be transmitted is provided by the same controller. The DES block acts as a system layer controller and puts into effect the different mode of operation of the device, depending on the programming provided by the controller.

In particular, in the case of decoding, the DES must recognize the different signal types (audio, video and private data) in the MPEG streams, separate them and supply them to the devices (decoders or controllers) and manage the synchronization ; in the course of demultiplexing, the DES also detects errors due to transmission in a noisy channel and indicates them to the external controller. The DES is connected to the external memory MT, which is a Dynamic Random Access Memory (DRAM), via a " bus " bi-directional data 10 and a connection 11 for addressing and memory control.

For synchronization, the DES exploits the information contained in the MPEG data stream, and in particular the SCR system clock references which allow the local reconstruction of the 90 kHz CKS system clock signal.

When, on the other hand, the DEC device functions as a transmitter or memory device, the DES might even be transparent to the data streams and the demultiplexing should not be performed. The DV Video Decoder, which can be programmed by the external CNT controller, receives the compressed video data from the DES through the " bus " U decodes it with the procedures prescribed by the standard MPEG and provides the decoded video signals to a UV video output unit which is intended to perform all the processing necessary for an image to be fed into a desired monitor window. The UV also includes a built-in digital-to-analog converter output. If the device is used in association with a personal computer, the UV block also includes components for overlaying decoded pictures to computer-provided graphic signals in the form of RGB digital signals through a connection 7. The analog video signals resulting from the decoding are shown at an output 8. The DV video decoder is conventional and can be performed, for example, by means of the CL450 component of the C-CUBE. UV block components are also conventional and may be those which perform the same functions in association with the aforementioned "CL450 Development Kit" component. The DA audio decoder receives, via the " bus " U, compressed audio packets to decode and perform decoding operations, as prescribed, - by default. The audio decoder, which may be, for example, the L64111 component of the LSI Logic Corporation, supplies the decoded audio signals to an audio output unit UA comprising a digital-to-analog converter, a processing circuit for performing signal required by the user and an output amplifier. The audio signals are then provided to the user via the connection 9. The DV video decoder and the audio output unit also receive appropriate control signals from the controller via the " bus " 4.

Referring to Figure 2, the demultiplexing circuit DES essentially comprises: a grammar analyzer PA separating audio and video streams and private data and extracting synchronization information; a CM memory controller MT; a DM unit to manage the data transfer of " bus " And for memory and vice versa; the IS, ICP devices to interface with the DES circuit with the synchronous serial line 6 (Figure 1) and the CNT controller; the FD circuits to perform the synchronization operations; an IU output interface to interface with the audio and video decoders. The PA grammar parser exploits the service information contained in private fields of MPEG streams, which start with a code that allows them to be identified. To make it easier to understand the PA functions, Figure 3 shows the ISO 11172 layer structure and the audio-visual packet layer, marking the information of interest of the invention. Further details are specified in Part 1 of the standard.

(a) a sequence of packets (data or synchronization information) PAC1, PAC2 ... PACn, each comprising, as indicated for PAC1: - a compression start code PSC, - a group of SCR words encoding the SCR information; - an HS System Header Registry, if any, which starts with a SHSC System Header Registration Start Code and contains service information (INFO) which is valid for a set of packets. The information contained in this register and of interest for the operation of PA should still be examined; W . ; A particular group of PCKl packets ... PCKn: as indicated for PCK1, each packet starts with a PSCP Packet Start Code Prefix, followed by a packet header register PCKH and then by the PDAT data; the PSCP prefix contains packet type information (audio / video / private data), whereas the header record contains the identity of the stream to which the packet refers, the length of the packet and other information used by the decoders in particularly the time information PTS (Presentation Time Mark) and DTS (Decode Time Mark). The last compression, PACn is followed by an IEC end code (ISO 11172 End Code). The structure and operation of the PA will be described with reference to Figures 5 to 9.

Turning to Figure 2, the memory controller CM manages the external memory MT so that the latter is functionally subdivided into four sections, each arranged in a FIFO structure, respectively intended for the temporary storage of incoming flows and the audio demultiplexed data , video, and private data to be sent to the decoders or to the external controller. The CM structure will be described below with reference to Figures 16, 17. The DM unit comprises means for managing the data exchange between the MT memory (Figure 1) and the IA and CSC units (via the " bus " E) or the CNT controller (via the " E " bus). The swapped data is managed according to the

(DMA) protocols, which prescribe the sending of a data request signal by one of the components involved in the exchange and a sending of a signal of acknowledgment of receipt of data sent by the other. The DM is connected to the CM memory controller via a " bus " M, to which the PA parser, IS serial interface and IU output interface are also connected. The DM structure is shown in more detail in Figures 4 and 10. The serial interface IS is intended to extract information from a PCM structure entering line 6, arranged according to the HDLC protocol, which is to be processed in the PA and, conversely, to dispose according to the HDLC protocol and insert into a PCM frame the information to be sent along line 6 and from PA through the connection 16. The IS structure will be described in more detail with reference to the Figures 13-15. The IU output interface is intended to extract the audio and video streams from the respective MT memory sections upon request from the DA, DV decoders (Figure 1) and to send them to the decoders. In practice, the UI consists of a pair of registers, one for each flow type, whose inputs are connected to " bus " M and the outputs are connected to " bus " U. The writing and reading of data occurs by request of the respective decoders. The retrieval of the stored signals and their transmission to the decoders is also managed according to the DMA protocols. The ICP interface for the CNT controller (Figure 1) is intended to manage the CNT addressing of the internal DES registers (i.e., the registers storing information related to the DES programming provided by the CNT, and the (for example, indicating errors, alarms, or data availability) to the CNT and to arbitrate access to the " bus " E, U through the different DES circuits or the CNT controller. The connection 15 outlines the set of wires for data exchange and other signals between the ICP and the other DES components. The structure of the ICP will be described with reference to Figures 11 and 12. The FD block comprises the digital part of a phase locked cycle (PLL) to reconstruct the CKS system clock from SCR indications drawn by the PA and provided over the connection 13 and a circuit for generating another CKESTR signal, to be supplied to the PA, which blocks the reading frequency of MT data to the

writing frequency. Note that the analogous part of the phase-locked cycle (made from a controlled-voltage oscillator and a digital-to-analog converter) is actually external to the DES device, but was not represented as a separate block to simplify the drawing . The DF structure will be described later with reference to Figures 18 and 19.

The following more detailed diagrams do not indicate the protocol-related signals for transferring data between the various components of the DES and between these and the CNT controller (as a rule, the data request sent by a first component to a second, acknowledges receipt by the latter of the sending of data and availability of the first component for a new operation), where such signals are not essential for understanding the invention, since all are conventional; to maintain the simple design, the means for blocking signals received at the internal time of each component has also been omitted; these means are also completely conventional. Figure 4 is a logical diagram of the data flow through the DES. The final letters E, U of the reference symbols indicate, respectively, the input and output elements in DES. In this figure, the DM block shown in Figure 2 has been divided into interfaces for connection to the blocks IA, CSC, CIS in Figure 1 and another interface dealing with data directed to or from the " bus " 4. The latter interface is hereinafter referred to as "interface for connection to " bus " 4 ". Each of these interfaces is in turn subdivided into an input section (ITE, ISE, ISE, IBE respectively for connection to IA, CSC, CIS and " bus 4) and an output section (ITU, ISCU , ISU, IBU). Note that the data transfer between the DM (Figure 2) and the " bus " 4 occurs via " bus " E, and therefore the IBE, IBU blocks are connected to " bus " E. Particularly in the diagram the external memory is divided into its four functional parts BS, BA, BV, BD, the first of which, as mentioned above, temporarily stores input streams (system amplifier) while the others store audio streams and video and private data demultiplexed (audio, video and private data amplifiers). In an exemplary practical embodiment, the external memory has a capacity of 64 words (16 " bits " each) distributed by the four functional parts as follows: BS 16 Kwords; BA 32 Kpalavras;

Accordingly, when the DEC device is used as a true decoder, the audio-visual streams from any one of the decoder inputs are carried by the " bus " E or part of the input 6E of the serial line 6, enter the DES through one of the ITE, ISCE, IBE or ISE interfaces. Only one DEC input and therefore only one of the above input interfaces can provide signals to the DES at any given time: the mutually exclusive operation is schematically represented by the SW1 switch inserted between the interfaces and the system amplifier BS itself. The streams to be decoded, read from the BS, are transferred to the PA parser that splits the streams into private audio, video and data components and routes them to the private audio, video and data amplifiers BA, BV, BD ; the audio and video signals are then routed to the respective decoders via the " bus " U, while the private data is forwarded to the IBU and from here to the controller, via " bus " AND.

When the DEC device functions as a transmitter, the MPEG data provided by the sources enters the ISCE, ITE or IBE interfaces and, after being stored, is sent to the ISU serial interface; the messages (non-MPEG data) to be sent to the IBU may arrive via the ISE.

When the device acts as a storage device, the MPEG data arrives through the ISE and is sent to the IBU. In these two cases, the demultiplexing may or may not be performed in PA. The Figure also indicates the BME, BMU amplifiers for temporary storage of messages received through the ISE and respectively of messages transmitted through the ISU. It should be said that, although the BME, BMU amplifiers are represented as separate blocks, they are actually an integral part of the IS interface, as will be seen below.

The different outputs of BS are also activated in a mutually exclusive manner, as schematically illustrated by the switch SW2. The additional switch SW3 represents the possibility of the IBU receiving data from both the BS and the BD.

reception of incoming IRD data is received from the CM memory controller, via the " bus " M, reading data into BS (Figure 4) and transferring it to subsequent components after organizing them into a format appropriate for these components. Data exchange occurs with a conventional protocol that involves a request for data reading by the IRD and accused of scheduling by the CM. Also for the " bus " M Figra does not distinguish groups of wires that carry data from those carrying signals related to protocols or other commands. The data is requested by the IRD to the CM at a frequency determined by the signal CKESTR (wires 13a of connection 13 quot the AP and the FD, Figure 2), and a read operation * automatically causes the advance of the read memory pointer, in a totally conventional way. In order to maintain the simplicity of the design, individual and accused order signs are not indicated in the drawing. In practice the IRD is made up of a shift register that performs the conversion from 16 to 8 " bits " of the reading of data words and, depending on the information communicated by the downstream components, provides them with a new block of data from which the data already used have been deleted.

The data read by the IRD is provided via a connection 17 to an SD unit which manages the data transfer to the IS serial interface (Figure 2) and through a connection 18 to four decoding logic networks D1- D4. The SD unit is intended to organize the data according to what is requested by the Serial Interface, in practice by converting from 8 to 16 ", bits to ". * provide the write and address increment commands to input amplifiers contained in the IS. The data is present on the wires 16a and the commands on the wires 16b. The two groups of wires together form the connection 16 in Figure 2. The unit SD is activated, when necessary, by signals supplied by a CPA control unit through the connection 65. The logic network D1 is intended to recognize the identifying the fields assigned to the service information relating to the system layer and for indicating to the control unit CPA the detection of a code and the type of code through a connection 60 which also includes information transport lines emitted by the logic networks D2 - D4 for CPA.

/

The logic network D2 is for extracting the SCR time indications to make available plugs for the FD circuit (the wires 13b of the connection 13); these indications are also provided to a parameter memory MP (via a connection 61 which also includes the lines in which the information exchange occurs between MP and D3, D4). The MP memory can also be accessed by the external controller (through the ICP interface, Figure 2 and the wires 15a of the connection 15) which reads the information written by the decoding logic networks and writes the programming data to the DESs. The logic network D3 is intended to extract the information contained in the header registration system and send it to the MP parameter memory. The information of interest to the invention will be apparent from the description of the operation. doPjA. The logical network D4 decodes the packet header registers and, depending on the content of the packet header register and the procedures determined by the programming information contained in the MP, sends, via the connections 62, 63, 64, audio signals, video signals and private data, respectively for POA, POV, POU. In a preferred embodiment of the invention, the grammar analyzer PA is capable of simultaneously extracting the related packets from one of the private data streams, one of the audio streams and one of the video streams multiplexed in the MPEG stream. The identity of these flows can be determined by the programming information contained in the MP; in the absence of a specific indication, D4 will extract the first stream identified by each type. In both cases the data of the other flows will be discarded. Then through " bus " M, the POU, POA, and POV units are fed to CM signals received from D4 for writing to amplifiers BD, BA, BV (Figure 4). This transfer also occurs with conventional procedures involving a request for writing by the units in AP and of accused of full operation by the CM. D4 also extracts from the received packets the DTS, PTS time indications already discussed above; these indications are used with procedures that depend on the type of audio and video decoders used and are also written in the MP parameter memory along with indications about the identity of the stream to which the packet refers and about the length of the packet.

The logic networks D2-D4 are activated in a mutually exclusive manner by the CPA via signals emitted in a connection 20 and provide the CPA with information about errors and serious anomalies that alter or impede the operation of the device.

Each of the ports POU, POA, POV is essentially made up of a register with input of 8 " bits " and output of 16 " bits " and a logic network for managing the protocol for the transfer of signal to the respective sections of the MT memory (Figure 1). The CPA control unit manages all circuit operations according to the data contained in the MP parameter memory (Figure 5), with the information received from the logic networks D1-D4 and with the possible external signals supplied by the controller and present in the bus "part 4E wires 4 that are being received in the DES means (Figure 1). Between the external signals a START signal for activating the operations of the device and a VIDEO_AUDION signal are mentioned here, which together with the information contained in the MP disables the decoding of the audio and video packages when these operations are to be carried out in other circuits. For this purpose, the POA and POV inputs are connected to the outputs of respective MX3 and MX4 multiplexers which are controlled by the CPA through a signal present on a connection 66 and having a second input connected to an additional output connection 21 of the IRD, in which packages are present. The two multiplexers are operated in a mutually exclusive manner, as indicated by the inverter INV. The CPA signals errors or anomalies to the ICP interface (Figure 2) in the form of interrupt requests issued on the wires 15b of the connection 15. The operation of the device PA will now be described, also with reference to the flow chart in Figures 6 to 9.

As shown in Figure 6, after receiving the START signal, the CPA grammar analyzer control unit (Figure 5) must first verify that the VIDEO_AUDION signal indicates that the analysis should not be performed. In the latter case, as discussed above, the CPA positions the MX3, MX4 multiplexers at the input connected to the connection 21 so that the packets are transferred directly from the IRD to the POA, POV output ports. If the analysis is to be performed, the CPA positions the multiplexers at the inputs connected to the D4 outputs, activates the D1 logic network and starts by waiting for a code (SEARCH CODES). Under normal operating conditions, the D1 must first detect a condensation start code, then a possible system header register start code and then the

start of packages. While the packet start code does not arrive, all " bits " to the DES circuit are eliminated. Upon arrival of each kidney of the codes (step 100), the D1 decodes them and the CPA will follow three different paths depending on the received code. The three paths are indicated synthetically in Figure 6 by steps 101 (analysis condensation header record), 102 (analysis system header record), 103 (analysis package). Each of these three paths respectively corresponds to the activation of one of the logical networks D2-D4, as indicated by steps 104, 105, 106 in Figure 7. Note that the step "POSITIONING THE SEARCH SEARCH" ") In Figure 7 corresponds to the" SEARCH CODES "step in Figure 6. xv, lv

If the code is the condensation start code, the logic network D2 (Figure 5) * analyzes the condensation header register (step 101), extracting the SCR system clock references and supplying them with the FD block (Figure 2 ) for the reconstruction of the CKS signal.

When a system header register start code is recognized, the operations of step 102, shown in more detail in Figure 8, are performed. The logical network D3 (Figure 5) must decode certain parameters contained in the header record and them to the MP parameter memory. The meaning of these parameters, which are indicated in the flow chart in Figure 8, is known by the standard. The CPA performs checks on the values of some of these parameters - in particular those related to the flow rate ("RATEJBOUND") and the minimum amount of memory required by the data, private (STD_AMPLIFICADOR_DIMENSÃO_LIMITE) ("STD_BUFFER_SIZE_BOUND"), and a pair of F and CPS flags indicating the characteristics of the flow (transmission at a fixed rate and limit parameters) - to check whether the values themselves are acceptable (flow rate and memory capacity) or if they are intended (for the two flags). If the result is negative, a signal is generated indicating that the decoding is impossible, which is displayed on one of the wires 15b. Under these conditions, grammar analyzer operations are blocked until a new START arrives.

If the received packet is a packet start code, the operations of step 103, shown in more detail in Figure 9, are performed. The CPA activates the D4

the identity of the stream to which the packet belongs, to verify that the stream is actually the one being processed. If the header record indicates that the packet is a video packet belonging to the present stream, the packet length is stored in MP; the presence of DTS signals (if any) is indicated to the external controller and, after the controller reads these signals, the transfer to the POV of the data contained in the packet is commanded for subsequent sending to the video amplifier BV (Figure 4) and then to the DV video decoder (Figure 1).

If the package is not a video package, the CPA examines whether it is an audio package or a private data package. If it is an audio packet belonging to the desired stream, the length is stored in MP, the PTS signals that may be present are read and the transfer of the data contained in the packet to the POA for storage in the BA is ordered. If it is a private data packet, it is ordered to send the data contained in the packet to the POU for storage in the DB.

When the AP eventually receives the end code, it rests again.

It should be noted that, for video signals and private data, only "liquid" data is transferred to the output, ie the data without the service information contained in the header record as prescribed by the standard. For audio it is possible to transfer liquid data, as prescribed by the ISO / IEC 11172-3 standard, or to transfer the whole package, depending on the characteristics of the audio decoder. Figure 10 shows the devDM block diagram. Also shown are elements in Figure 4 indicated with the same references. The DM comprises an input section (ITE blocks, ISCE, IBE) that transfers the data from the IA, CSC and CNT (Figure 1) into an EE connection to the CM memory controller, through an MX1 multiplexer and a connection or "; bus " MW, which represents that part of " bus " M which carries signals directed to the memory controller CM (Figure 4), and an output section (ITU blocks, ISCU, IBU) that forwards to LA, CSC and CNT, through an MX2 demultiplexer and a EU connection, the signals read in BS (Figure 4) and present in a connection or " bus " MR, which represents that part of " bus " M (Figure 2) intended to carry the signals coming out of CM. The connections EE, EU and MW, MR are unidirectional connections obtained by separating, in a fully conventional manner, the two transmission directions of the " bus " ^ and M respectively to the DM input.

If the device of the present invention is placed on the decoding side of a transmission system for MPEG streams, the ITE circuit receives data blocks of " bits " of an AI and it arranges us in blocks of 16 " bits " to be transferred to the CM controller and to the BS. The ITU circuit receives from the CM controller, via a suitable bus " MR, information on the level of filling of the memory BS (STAT signal which will be examined in the course of a detailed description of CM) and sends a request to the IA, through a US wire, to discontinue the data transmission. if the. BS fill level exceeded a higher threshold, t or a request to restart the transmission if the BS fill level fell below a lower threshold. Both thresholds are programmable.

If the device is used on the transmitter side, the ITU will divide the blocks of 16 " bits " of data read in memory in two " bytes " and will send them sequentially to AI; the ITE receives the LA return signals from the controller and sends them to CM.

Both ITE and ITU are performed by means of two finite state machines, one dedicated to receiving data from the outside and sending it to memory, and the other dedicated to the management of control signals. Since the dialog protocol is standard, one skilled in the art will have no problem performing these devices.

The ISCE, ISCU, IBE, IBU circuits comprise a pair of registers in a "ping-pong" arrangement (i.e., a pair of registers alternating in each reading, writing and writing cycle) and a logic network for the request / acknowledgment signals prescribed by the protocol. The data arriving at or leaving these circuits in the different modes of operation are clearly shown by what has been described above.

Through the wires 15c of the connection 15 all the circuits in DM also receive from ICP (Figure 2) the STOPE command to stop their operations when the CNT controller (Figure 1) requests access to " E, and send to the ICP, through the wires 15d, which also belong to the connection 15, a STOPDE signal to acknowledge that the stop has occurred.

With reference to Figure 11, the ICP block comprises three logical networks ^ GIR, CDE, CAC respectively, which are intended to manage interrupt requests, decode the addresses of the internal registers in the DES and to arbitrate requests for access to "; bus " E, U (Figure 1) from DM, IU (Figure 2) or the CNT controller. The GIR receives interrupt requests from the PA, CM and IS through the wires 15b of the connection 15, each of the wires being associated with a specific request IRQX. It is assumed, by way of example, that 16 different applications can reach GIR. In the presence of these requests GIR sends an IRQ flag to the CNT controller (Figure 1) via a " bus " 4U (representing the part of the "bus" 4 that exits from the DES) and subsequently, when they receive the RIRQ command from CNT through the " bus " 4E, makes requests available in " bus " E. GIR also comprises means for preventing requests arriving while processing an earlier request being erased without being distributed. The structure of the GIR will be described with reference to Figure 12. The CDE circuit which generates the address register completes an indirect addressing which involves, in an initial operation, which sends the address the CDE and, in a second operation, which actually write is -list the data to / and log. The CDE essentially consists of a decoder that receives the address through " bus " EE and displays, on the wires 15e of the connection 15, the activation signals for individual registers. Indirect addressing is a technique well known to those skilled in the art, and therefore, the CDE circuitry does not require a more detailed description. The CAC circuit generates access to " bus " And, so that these " bus " are usually assigned to the DM or UI, respectively, and instead are assigned to the CNT controller (Figure 1) when the latter requires it. The circuit comprises two identical elements, each of which generates access to one of the two " bus ". The controller access request is the IOBUS signal that is displayed by the CNT on one of the two " bus " 4E and indicates, depending on its logical value, whether access to the " bus " E or the " bus " U. As a consequence of the request, the CAC generates, depending on the element concerned, the signal STOPE (wires 15c) or STOPU (wires 15f) requesting operations for the circuits DM or IU to stop; after receiving the STOPDE, STOPDU indictment, provided by the components involved through

and that indicates that the stop has occurred, the CAC will generate OEE, OEU signals for the PE, PU conductive circuits in the wires 5E, 5U, which form the connection 5 in Figures 1, 2; the CAC will also receive the usual read / write (R / W) commands and select " chip " (CS) and will send the RDY availability signal to the controller. Such a circuit is totally conventional.

Other input / output signals to and from the ICP will result from the description of other DES blocks (Figure 1).

Referring to Figure 12, in the example given here, of 16 possible interrupt requests, the GIR circuit comprises a bank of 16 "latch"

Ll. Each element has its door input connected to one of the wires 15b and, upon receiving:. In the IRQX request, it outputs a signal at a predetermined logical level (in particular 1). The outputs of the different elements of Ll are connected to the inputs of the OR gate, denoted by Pl, whose output is the " bus " 4U that carries the IRQ flag, which signals the presence of an interrupt request, to control the CNT. Above all, each of the outputs of Ll is connected to one of the registers of a bank of 16 registers Rl, which stores interrupt requests and transfers them to the " bus " US (IRQR signal) upon receiving a RIRQ read command supplied by the controller through a " bus " 4E. Each Rl output signal is also returned to the readjust input of the respective element in Ll through the series of an AND gate and a NOR gate, which belong to the respective gate banks P2, P3. Each port in P2 is activated by a pulse which is derived from a GIM pulse generator of the read command for the respective register in, JS.1.

In practice, IMT can be a differentiation circuit. The individual ports in P3 are activated by the respective output signal of a bank of 16 which activates the registers R2 which, under the command of a writing signal provided by CDE (Figure 11) through one of the wires 15e, carries a signal which activates the processing of individual interrupt requests and which is provided by the controller through " bus " AND IS. Of course, with the arrangement described herein, an interrupt request is not readjusted and is kept available to the controller unit until it is actually read by the latter. Therefore, requests arriving while the controller is already processing another request are not lost. Above all, through the register R2 and the P3 ports it is possible to mask interrupts individually.

the transmission section STX and an SRX receiving section, which corresponds to the set of blocks BMU, ISU and respectively ISE, BME in Figure 4. If the DEC device (Figure 1) is used as a transmitter, the receiving section SRX receives and makes available to the controller the signals that acknowledge the message coming from the device associated with a remote decoder; vice versa, in the DEC device associated with the receiver, the SXT section transmits the acknowledge signals provided by the controller and the receiving section receives the data and messages, sends the first to the system amplifier and provides the latter to the controller . The transmission section is intended to provide the transmission of signals in an HDLC protocol within a PCM frame in that it takes into account, on the one hand, the protocol characteristics and, on the other, the fact that certain channels of a frame are reserved for synchronization and signaling information and can not be used for communications. The HDLC protocol used in the present application uses frames which include, in order: at least one initial synchronization word, characterized by six " bits " consecutive "1"; the sync words can be multiple if you need to adapt the channel fill to the " bit " really required; an "address" word, which comprises a group of " bits " which specifies the type of information transmitted, namely the MPEG data, and the message signal or acknowledge signal; in the latter case the word of address also encodes the meaning of the signal of accused of receiving itself; a sequence of words representing the content of transmission information (obviously these do not exist in case of transmission of a signal of accused of reception); two words to check the transmission correction (in particular, two words representing a cyclic redundancy code).

More details on the frame structure indicated in the international standard 1SO / 1EC 3309 can be found.

In view of the foregoing, the transmission section STX comprises: a data generator GD, comprising two elements respectively storing the data coming from, for example, the SD unit (Figure 5) of the parser, grammar PA through of the connection 16 and the messages provided by the controller through the " bus " AND IS; the GD sends the data / messages, a " byte " at a time, to an HDLC frame forming the device TH, when the GD receives the corresponding request of TH; The memory element for the messages is the BMU block in Figure 4. the HDLC framing device TH, which inserts the words synchronization and the address at the beginning of each frame, breaks the ls sequences which, in the information words, could simulate the sync word (in particular, by inserting a 0 after five consecutive ls) and computes the cyclic redundancy code by adding it to the end of the frame; the TH structure will be described below with reference to Figure 14; an IPT output interface, which requests TH, a " bit " at each turn, the signals are " are transmitted and inserted into a PCM frame on the basis of the synchronization information provided by CIS (Figure 1) via line 6E; the PCM frame is then emitted at the 6U connection. The SRX receiving section is complementary to the transmission section and comprises: an IPR output interface extracting a " bit " at a time, HDLC data of a PCM frame present in line 6E, on the basis of the synchronization information provided by CIS through the same line 6E; an RH device to divide the HDLC frame, whose tasks are complementary to those of TH and which must recognize the type of information transmitted by transferring messages and MPEG data, a " byte " at a time, to an RXD data receiver and which provides the acknowledge signals to the CNT controller (FIG. 1); the HR structure is illustrated in detail in Figure 15; \; ο the RXD data receiver, which annazena in data or message amplifiers the " bytes " received from HR before sending them, respectively, to BS (Figure 4) and CNT (Figure 1) through the " bus " MW, EU; the data amplifier is composed of two elements in a "ping-pong" arrangement and is intended to store data for as long as the memory controller needs to gain access to BS; instead the message amplifier (which has been indicated as BME in Figure 4) is a FIFO, which annains complete messages and indicates that it is filled (and therefore the messages are present) by an interrupt request.

With reference to Figure 14, in block TH an MX5 multiplexer has four inputs respectively connected: to the connection 22 in which the GD (Figure 13) shows the information to be transmitted; the means that provide the information to be transmitted; to means providing the synchronization word (arrow FL), obtained through the appropriate group of logical levels by wires; to the output 70 of a CRT circuit which computes the cyclic redundancy code in the transmission; to the output 71 of an SIH circuit to select the HDLC address. Ο MX5 is positioned at the appropriate input, depending on the phase of the transmission, by means of a command issued on a connection 27 by a LOT-control logic network, which also requests the " bytes " of data from the generator GD via a UNBYTE signal issued on the wire 23. The circuit SH comprises three registers in which the controller writes, through the " bus " EE, the values assigned to the address word, respectively for data, message and acknowledgment signals. Through the connection 71, the SIH provides the MX5, on the basis of a control signal emitted by the LCT in a connection 28, with the word ADDR corresponding to the type of information transmitted. The SIH also provides the values used to lock the HR in Figure 13 (DAM signal present on a connection 25), so that the latter can correctly interpret the received information. Obviously, these values will also be reported to the remote DECR device (Figure 1), if present. The output 72 of the MX5 multiplexer is connected to a PS-series parallel converter whose output 29 (OUTS signal) is connected to both the CRT and to a UNT device which outputs the data in the serial output 24 after breaking the consecutive ls sequences as mentioned above. The PS circuit loads the " bytes " which leave the 2 '

ΜΧ5 on command of the logical network LCT (LOAD, wire 30) to which the PS signals (that a byte was sent to UNT.) The sequence breaking of ls is disabled by LCT (DISUNI signal present in a wire 31) when the bit string in the wire 29 is related to the synchronization word. The UNT also receives from IPT (Figure 13) the request for "bit" (UNBIT signal) through wire 26 and transfers it through a wire 32 for both PS and a splitting command to cause the output of a new " bit ", as for CRT as a command to load the " bit " that exits from the PS so that " bit "can be taken into account in computation of the redundancy code. The realization of a circuit that performs the functions of UNT is not a problem for those skilled in the art.

Referring to Figure 15, in the RH circuit for dividing the HDLC frames, a UNR block, whose tasks are complementary to those of the UNT block (Figure 14), receives from the IPR (Figure 13) the serial stream of signals present on a wire 33, discards the ones that the UNT may have inserted, and recognizes and signals to an LCR control logic network, via a wire 37, the arrival of a synchronization word (FLG signal). The UNR data output 38 (OUTU signals) is connected to a serial-to-parallel converter SP and to a CRR circuit for checking the cyclic redundancy code, the circuit of which signals the LCR that two words relating to that code ( CRCOK signal on wire 39, which is also stored in an LCR register to be made available to the controller, for example via ICP, Figure 2, as schematically represented by wires 15i). The SP output 40 (POUT signals) is connected to an HIV circuit to check the HDLC address and a two-word PIP output amplifier memory which provides the words SP sent to the data receiver RXD after storing them for a time interval equal to the duration of two words.

The storage of two words is intended to prevent two words related to the cyclic redundancy code from being sent to downstream components, as will be clarified with the following description. The VTH circuit is provided by LCR to load the address after the RHs have received the word or sync words through the WRADDR command on wire 41 and to compare that address with the DAM signal provided by the transmitter to recognize the type of transmission . Information on the type of transmission is communicated to LCR (signal AD 25

transmitted information to the appropriate RXD memory (Figure 13) via the WD data write commands or WM message write commands generated on the wires 35, 36. The issuance of these commands is inhibited in the presence of synchronization words of the address or cyclic redundancy code. If the transmission concerns an acknowledgment signal, HIV makes it available to the controller via ICP (ACKDAT signal present on wires 15h). The LCR also emits, on the appropriate wire 15b, the ACKREC interrupt request. In order to maintain the simplicity of the drawings, the reading request signals for ACKDAT and CRCOK are not shown. The operation of HR is as follows. The arrival of a sync word after a series of different words indicates to the LCR the beginning of an HDLC frame: this means that the two words currently stored in the PIP are the words of the cyclic redundancy code of the previous frame, which does not have to be sent to components downstream, so the LCR does not emit WD, WM signals. After the first synchronization word, the HR can receive other synchronization words or the HDLC addresses: if other synchronization words arrive, they are signaled to the CRL by an equal number of FLG signals; when, in correspondence with a new word, the FLG signal is no longer present, the LCR issues the WRADPR address loading command: in these cases, too, the write commands are not generated. They will be generated only upon receipt of the address, with a two-byte delay of ", so that the first information word is actually present in the PEP output. Figure 16 shows the block diagram of the CM memory controller. The CM controller must process any access requests from the DES components (Figure 1) to one of the BS, BA, BV or BD sections (Figure 4) for write / read MPEG streams to be demultiplexed or for demultiplexed streams, or requests of the CNT controller (Figure 1) to any memory location. In the example shown, it is assumed that the CM can therefore receive five different write requests and five different read requests: four of the read / write requests come from DES components and concern only one section between BS, BA , BV or BD (in particular ISCE, ITE, ISE, IBE, Figure 4, can write in BS, ISCU,

ITU, ISU, IBU can read from BS; the PA can read from BS and write in BA, BV, BD; can read it from BA, BV); the other read / write request is that provided by the CNT and, for the purposes of this request, the MT memory (Figure 1) is viewed as a single unit. A different pointer must match each of the five read / write requests; the pointers for operations required by the DES components choose the address in the group that corresponds to the particular section and allow a FIFO management of the sections; instead, the pointer for CNT access points to the address reported by the CNT.

That being said, the CM block comprises: an ARB arbitration circuit which receives the read / write memory requests and selects the corresponding pointer (ADPU signal and WR / RD read / write signals).

It should be noted that orders from the DES components (Figure 2) arrive via MW and those from the controller arrive via the connection wires 15; for the sake of simplicity, it is not a distinction between the different request sources and the requests are indicated mainly as REQW, REQR, respectively for writing and reading. The ARB also checks the fill condition of the individual sections, which generate a number of signals about that condition, which will be examined in connection with Figure 17, which provides a detailed illustration of the structure of the ARB. Some of these signals, indicated above all as STA, are used outside the ARB; a CIM circuit which controls the memory addressing and which, depending on the information provided by the ARB, identifies the section involved and generates on the connection 11 the read or write command (MEMCONTR) and the addresses (MEMADDR) with the procedures required by the protocols for managing a dynamic RAM memory; these procedures are entirely conventional and therefore it is not necessary to describe the CIM in detail; a pair of RER registers, REW for the temporary storage of data read from the memory (arriving through the connection 10R, belonging to the connection 10 in Figure 2 and having to be transferred in MR) or, respectively, of data intended to be written in memory (which

I

2F -VJUOJJ 'arrive via MW and have to be transferred in connection 10W, also part of connection 10 in Figure 2); the data is loaded to RER, REW under a CIM command (44,45 wires).

At the end of each operation, the CIM provides the ARB with an end-of-operation signal RDY (wire 48) and the ARB, in turn, will be able to send to the component that requested it the ACKR, ACKW signals that accuse reading or writing, through the " bus " MR or connection 15 (requested respectively by DES or CNT, Figure 1). Also in this case, no distinction is made between indictments directed at the DES or the controller.

Referring to Figure 17, the ARB circuit comprises: a ten-input multiplexer MX6, which receives the ten possible requests REQW, REQR for access to the memory and sends one request at a time at an output 50, under the command of a counter CN1 ; a GPU circuit for generating the ten read / write pointers; a DAK circuit for generating the acknowledged ACKR, ACKW; an LCA control logic network. The counter CN1 is a counter which normally performs a cyclic count to sequentially command the connection of the ten MX6 inputs to the output 50, thus allowing sequential processing of access requests, for example, following the technique commonly known as "round robin". Conveniently, MX6 entries are arranged in such a way that there is an association between read / write requests and even / odd CN1 count values; for example, the even values can choose the entries that carry the REQR read requests, and the odd values can choose the entries that carry the REQW write requests. The CN1 can, however, also be programmed by the controller in such a way as to only connect the pre-set MX6 inputs to the output. The REQ request transferred to the MX6 output is provided for both the LCA control logic network to be processed and the CN1 as a command to temporarily stop (the STOP signal) the sequential count, which will be restarted by the LCA command RESTART) once the request has been processed.

The counting value present at the output of CN1 is also supplied to the GPU pointer generating circuit, the LCA control logic network and the DAK receiving acknowledgment generator circuit. The GPU circuit, depending on the value present at the connection 51 and the address provided by the CNT (Figure 1) through the " bus " EE (in the case of a request from the CNT) sends the ADPU signal to the CIM (Figure 16) to address the pointer involved. The write address issued by GPU is always the address of the first free position, while the read address is always that of the first occupied position. After each operation the GPU increases the pointer under the command of an INC-supplied LCA signal. Clearly, in the case of operation requested by CNT, the increase of the pointer does not have any effect if the previously performed operation involves only one cell and the CNT has in the meantime loaded a new GPU address through the EE. Procedures for treating memory pointers, described above, are well known in the art.

The GPU also performs a comparison between the read pointer and the write pointer to measure how full the memory is and generates three signals that indicate the result of the comparison. A first signal is the STAT signal which indicates whether the fill level is between a lower and a higher limit or if it exceeded the upper limit as an effect of a write operation or if it fell below the lower limit as a result of a read operation : as mentioned above, this signal is supplied to the ITU block (Figure 4) to generate the request for suspending or resuming data being executed; the limit values are programmable and are supplied to the GPU by the CNT controller via the " bus " AND IS. Instead, a second signal (ISTAT) indicates the condition of the full or empty memory and is supplied to the LCA control logic network which, depending on the value of this signal and the type of operation requested (which, with the hypothesis set forth in CN1 counting values, is indicated by the least significant bit of the value present in the connection 51), decides whether to perform the operation and hence generate the respective command for CIM and then send the accused that the operation has taken place, or send an FVP interrupt request to ICP (Figure 2). A third signal (LEVEL) represents the difference between read and write pointers in the system amplifier and is supplied, again via " bus " MR, the FD (Figure 2) that uses it to generate the signal CKESTR: signal LEVEL

has a capacity of 16 bytes, which corresponds to examining the memory fill level in steps of 1 byte ". The STATS and LEVEL signals are the signals indicated as a whole by STA in Figure 16. The various signals generated by GPUs are also kept available to the CNT controller, which may request that they be displayed in the " bus " I. The performance of a circuit which in accordance with the functions described above poses no problem to those skilled in the art. The DAK signal generation circuit is a simple decoder which receives an ACK signal which accuses the completion of an operation by the LCA and, depending on the value present in the connection 51, generates one of the five possible ACKW signals, or the five signs of ACKR reading accused. The generated signal is sent to the component that requested the operation in memory. The LCA control logic network is a conventional finite state machine, the operations of which are inferred from the above description. For the sake of clarity, these operations are summarized here: the LCA receives a REQ signal and the count value of CN1, which specifies whether the request pertains to a write / read on the system, audio, video or user amplifiers, or a write / read requested by the CNT and therefore viewing the memory as a whole, checks the memory to see if the operation can be performed: if not, the LCA emits an interrupt signal FVP on a wire 15b and, if so, generates the write / read command WR / RD on wire 47, outputs the acknowledged ACK signal and the INC. sharpener signal, and, at the end of the acknowledged signal, sends the RESTART signal to CN1. Designing a logical network that performs these operations is no problem for those skilled in the art. Figure 18 shows that the circuit contained in the FD circuit (Figure 2) and generating the CKS comprises: a REI register which carries the time stamp value SCR taken from the MPEG compression and provided by the PA (Figure 2) through the wires 13b of the connection 13. A subtractor ST1, which subtracts between the SCR value received from REI and a SCR local value SCR ', provided by a CN2 counter controlled by the CKS signal, and generates an error signal e1; a digital filter Fl, which performs low pass filtering of the gate signal ei; the filter Fl is a filter whose zeros, poles and gain can be programmed by the controller via the ICP interface (Figure 2); the connection 15j schematizes the connection between Fl and ICP required for addressing, loading of programmed values, exchange of protocol protocol signals; a DAC digital-to-analog converter, which receives the filtered error signal and converts it into the analog form to regulate the frequency of a VCO-controlled oscillator, from which the output 12 carries the reconstructed CKS signal at 90 kHz. ·

It should be noted that for correct circuit operation, the filter F1 must be started so that the local value SCR 'of SCR corresponds to the value loaded in RI.

Referring to Figure 19, the FD circuit (Figure 2) for generating the CKESTR comprises: a subtractor ST2 which receives from the memory controller, through the " bus " MR, the LEVEL signal which represents the difference between the read and write pointers and introduces a fixed OFF offset to that difference, for example in such a way that the equilibrium condition, which does not require a CKESTR frequency correction, corresponds to the semi-filled memory situation: in the example considered, where the fill level is evaluated on a sixteen-value scale, OFF will have a value of 8; a sample register RE2, which shows the output signal ST2, representing an error signal β2, with frequency fc (for example 8 kHz or 1 kHz) much smaller than the frequency of variation of the LEVEL signal; the command for loading the & 2 cm signal RE2 is provided by the decoding time base (not shown); a digital filter F2, which performs low-pass filtering of the & 2 signal, also F2 is programmable by the controller, in exactly the same way as Fl (Figure 18); the connection 15k, whose objectives are the same as those of connection 15j, schematizes the connection between F2 and ICP (Figure 2); a divider DIV, which divides a fixed frequency signal (in particular a 23 MHz signal), generated by the time base of the decoder DEC, by the signal

/ / which exits the filter F2 and generates the signal CKESTR, which is sent to the PA through the wires 13a of the connection 13.

Lisbon, 3 0 ABR. ZiOl

Dra. Maria Silvina Pferreira

Official Owner of Industrial Property R. Castilho, 201-3 ° E- 1070-051 LISBOA

Telefs. 213 851339-213 854 613

Claims (15)

A device for transmitting, receiving and decoding audio-visual streams, hereinafter referred to as MPEG streams, organized in accordance with ISO / IEC 11172 and resulting from the multiplexing of encoded audio and video streams as well as streaming streams (DEC) comprises: demultiplexing and synchronizing (DES) means for demultiplexing the MPEG streams in the audio, video and private data streams, and for extracting the synchronization information of the MPEG streams, means (DA, DV) for decoding audio and video streams, and means (UA, UV) for the presentation of audio and video signals in analog form; is associated with a controller (CNT) comprising a processing unit and controlling and supervising the demultiplexing and decoding operations; is embodied as a printed circuit board which forms the demultiplexing and synchronization means (DES) which is a unit distinct from the controller (CNT), and which further comprises first interface means (CSC) for connection to a peripheral unit (MEL ) which is a local source or a local receiver of said MPEG streams, second interface means (LA, CIS) for connection to a telecommunications network (2, 3) through which the device (DEC) receives said MPEG streams of sources or transmits them to remote receivers and " bus " (E, U) for signaling the transfer between the different units in the device and between the device and the controller, characterized in that said second interface means comprises a first unit (IA) provided for connection to a first series line ( 2) of the telecommunications network for the asynchronous transmission of MPEG streams and a second unit (CIS) for connection to a second serial line (3) for the synchronized transmission of streams, commands and MPEG data, hereinafter referred to as "messages" , which can not be inserted into the MPEG streams and which are addressed to the controller (CNT), and signals that acknowledge that a message has been received or that an operation has been performed; and in that the device is arranged to receive MPEG streams from the controller and to transmit MPEG streams to said controller (CNT). Device according to claim 1, characterized in that said " bus " (E, U) are linked to another " bus " (4) which is the " bus " of the controller (CNT) and comprises: a " bus " (E) to which the first interface means (CSC), said first unit (IA) of the second interface means and the demultiplexing and synchronization (DES) means are also connected and which allows: the transfer of MPEG streams the first interface means (CSC) and said first unit (IA) of the second interface means for the demultiplexing and synchronizing means (DES) and vice versa; sending private data. extracted from MPEG streams to the controller (CNT); sending messages and acknowledgment signals of the demultiplexing and synchronization (DES) means to the controller (CNT) and vice versa; controller access (CNT) via " bus " controller (4), the first and second interface means (CSC, IA, CIS) and the demultiplexing and synchronization (DES) means for writing programming information and reading information about the operation of the device, a " (DA) to which the demultiplexing and synchronizing means (DES), the means (DA, DV) for decoding the audio and video streams and the controller (CNT) are connected, and which allows the transfer of the demultiplexing means and synchronization (DES) for the decoding means (DA, DV) of the audio and video demultiplexed streams, and access by the controller (CNT) to the decoding and presentation means t (DA, DV, UA, UV) for its programming . Device according to claim 2, characterized in that the second unit (CIS) of the second interface means is connected directly to the demultiplexing and synchronizing means (DES) through a third series line (6). A device according to any one of claims 1 to 3, characterized in that said printed circuit board constitutes an expansion of a personal computer carrying said controller (CNT) and which is also in charge of programming the interface means (AI, CIS, CSC), the demultiplexing and synchronizing means (DES), the decoding means (DA, DV) and the display means (UA, 'UV), the demultiplexing and synchronizing means (DES) operating without involving the unit of the controller (CNT). Device according to any one of claims 1 to 3, characterized in that said printed circuit board also incorporates the controller (CNT), to realize a preprogrammed self-decoding device. Device according to any of the preceding claims, characterized in that it comprises temporary storage means (MT); (BS, BA, BV, BD), the first of which is intended to store the MPEG streams to be demultiplexed and decoded, and the other three sections respectively are used to store audio, video and audio demultiplexed streams, respectively. of data. Device according to the combined claims 1, 2, 3 and 6, characterized in that the demultiplexing and synchronizing means (DES) comprises: v: third interface means (DM) for transferring the " bus " (E) for the temporary storage means (MT) and vice versa, with a direct memory access technique, the MPEG streams being from or directed to the first interface means (CSC), to the means (IA ) for connection to the first series line (2) or the controller (CNT); (UI) for the transfer of audio and video demultiplexed streams from the temporary storage (MT) means to the " bus " output (U); fifth interface means (IS) for managing the exchange of signals through the third series line (6), between the means (CIS) for connection to the second series line (3) and the demultiplexing and synchronizing means (DES); a grammar analyzer (PA) that receives the MPEG streams from the temporary storage (MT) means, demultiplexes them and extracts the synchronization information comprising at least representative information (SCR) of a base frequency for the local reconstruction of a clock signal in that base frequency; control means (CM) for the temporary storage means (MT); sixth information exchange interface (ICP) means for information exchange with the controller (CNT), means which take information about the operation of the device available to the controller, provide commands to the other circuits of the demultiplexing and synchronization (DES) means and which have arbitration tasks to avoid conflicts in accessing " bus " (E) through the demultiplexing and synchronization means (DES) or through the controller (CNT); synchronizing means (FD) for local reconstruction of the base frequency clock signal and for generating a regulation signal (CKESTR) which determines the reading frequency by the grammar analyzer (PA) in the first section (BS) of the means of temporary storage (MT). A device according to claim 7, characterized in that said grammar analyzer (PA) comprises: a receiving unit (IRD) for receiving data from the first section (BS) of the temporary storage means, which unit requires the data in a frequency determined by said control signal (CKESTR); means (SD) connected to an output of the receiving unit (IRD) for transferring to the fifth transmission means. interface (IS) the information to be sent to the second series line (3); first decoding means (D1, D2, D3) also connected to the output of the receiving unit (IRD) to: recognize and decode codes representative of the service information inserted in the MPEG streams to enable their demultiplexing; communicating information extracted from said codes to a control unit (CPA) or parameter memory (MP) depending on the type of information; extracting and sending to the synchronization means (FD) said information (SCR) representative of a base frequency; second decoding means (D4) for: recognizing and separating the relevant packets for the video, audio and private data streams multiplexed in the MPEG streams; providing the packages to the respective output ports (POA, POV, POU) for subsequent sending, respectively to the second, third and fourth sections (BA, BV, BD) of the temporary storage means (MT); and providing service information extracted from a header record of each packet to the parameter memory (MP), also communicating the first and second decoding means (D1, D2, D3, D4) to said control unit (CPA), situations anomalies detected; the said memory parameter (MP), which is also accessible by the controller. . (CNT) for writing programming information and reading information extracted from MPEG streams and controlling the second decoding means D4 in order to enable the extraction of a packet sequence relevant to one or more predetermined streams of the different types; said control unit (CPA), which is arranged to initiate a series of operations of the grammar analyzer (PA) when it receives a controller start signal (CNT) and to activate, based on the information recognized by the controllers. . the first decoding means and the information contained in the parameter memory (MP), any of the units (D2, D3) belonging to the first decoding means for recognizing specific codes, or to the second decoding means (D4). '·. > ri Device according to claim 8, characterized in that said grammar analyzer (PA) also comprises means (MX3, MX4) controlled by said control unit (CPA) and connected between the output of the receiving unit (IRD) and the output ports (POA, POV) for the audio and video streams, for transferring the packets from an MPEG stream directly from the receiving unit (IRD) to one of said output ports, so that said packets bypass the second decoding (D4). The device of any one of claims 7 to 9, wherein said temporary storage means (MT) is made of a memory of __ 6 __ 6 dynamic random access, characterized in that said control means (CM) is capable of serving requests for access from the decoding and synchronization (DES) means for writing MPEG streams to be demultiplexed or to read audio, video or data demultiplexed streams in or respectively from one of the sections (BS, BA, BV, BD) of the temporary storage means (MT), and access requests from the controller (CNT) for writing / reading information relevant to device programming or operation in of any position of the temporary storage (MT) means and comprises: an arbitration circuit (ARB) which is adapted to: receive requests to write to or read from memory; generating sine; s. (ADPU) for selecting a writing / reading pointer relevant to a dash-section (BS, BA, BV, BD) or a relevant write / read pointer for all memory and signals (WR, RD) for commanding write / reading; generate signals (ACKW, ACKR) that accuse the operation was performed, to be sent to the unit that requires them; and verify the filling condition of the individual sections (BS, BA, BV, BD) that generate the signals relevant to this condition; a circuit (CIM) for controlling the addressing of the temporary storage (MT) means, which circuit identifies, depending on said selection signals generated by the arbitration circuit (ARB), an appropriate section or position in the temporary storage means ( MT) and generates commands and write / read addresses, sending them to the temporary storage medium (MT); a pair of registers (RER, REW), controlled by the addressing control circuit (CIM), for temporary storage, respectively, of data read from and to be written to the temporary storage (MT) means. A device according to claim 10, characterized in that the arbitration circuit (ARB) of the memory control means (CM) comprises: means (MX6, CN1) for selecting a writing / reading request to be served, said means which comprise a multiplexer (MX6) to whose inputs all possible requests arrive and a counter (CN1) of which the value of i \ 1 \ is a command signal for setting the multiplexer (MXK) and is stopped each time a write / read request is transferred to the output of the multiplexer (MX6), also containing the counting value of the counter (CN1) information on the type of memory operation to be performed; (LCA), which is arranged to: receive the selected request from the demultiplexer (MX6) and the counter (CN1) the corresponding count value; check the memory condition to see if the operation can be performed; generating, if the operation can be performed, a write / read command, a signal issuance command that indicates that the operation has been completed, a command to increment the pointer involved in the operation, and a signal to reset the counter count ( CN1); and generating, if the operation can not be performed, an interrupt signal for the controller (CNT): an address generation circuit (GPU), which is arranged to present at the output, in correspondence with a request and as a function of the value (CN1) or an address provided by the controller (CNT) and the increment signal; provided by the logic control network (LCA), the address of the first position available for writing or the first position containing the data to be read in the section on the temporary storage (MT) means, for a comparison between the pointers of reading and writing of a same section to determine the level of completion and to generate, as a consequence: a first STAT signal indicating whether the fill level is between an upper threshold and a lower threshold or has exceeded the threshold is the consequence of a write-in or has fallen below the lower threshold as a result of a reading and which is sent to the third interface means (DM) to cause the data to be suspended or reset to the temporary storage means ( MT); a second status signal (ISTAT) indicating a condition of filling or emptying a section of the temporary storage (MT) means and is sent to said control logic network (LCA) to allow the decision to carry out an operation ; and a third LEVEL signal representing the difference between the read and write pointers in the first section (BS) of the temporary storage (MT) means and is sent to the synchronization means (FD); a circuit (DAK) which generates reception signal signals, which generates these signals under the control logic network (LCA) and according to the counting value of the counter (CN1) corresponding to the request being served. A device according to claim 11, characterized in that said synchronization means (FD) comprises: - a circuit for reconstructing and checking the base frequency clock signal, which circuit comprises a voltage oscillator (VCO) which is controlled by a signal obtained by filtering on a first low pass digital filter (F1) and converting to the analog form a signal representing the difference between an instantaneous oscillator output signal (VCO) and the value nominal frequency of said base frequency, extracted from MPEG streams; a circuit for generating a regulation signal, the circuit comprising a second low-pass digital filter (F2) arranged to predefinely filter the third signal (LEVEL) and to supply the filtered signal to a digital divider ( DIV), which generates the regulation signal by dividing a fixed frequency by the filtered value and provides this signal to the grammar analyzer (PA). Device according to claim 12, characterized in that said first and second digital filters (F1, F2) are controllable by the controller (CNT). Device according to any one of Claims 7 to 13, characterized in that the fifth interface means (IS) comprises means (TH, IPT) for inserting data, messages and acknowledgment signals to be sent to the second line (3) into frames organized according to an HDLC protocol and to insert the HDLC frame into a PCM frame and means (IPR, RH) to extract the frames prepared according to an HDLC protocol of a PCM frame i from the second series line 3, for extracting the accused from receiving the HDLC frames and for transferring the data to the temporary storage (MT) means and providing the messages and signals from the controller (CNT). Device according to any one of claims 7 to 14, characterized in that said sixth interface means (ICP) comprises a circuit (GIR) for managing interrupt requests, comprising: acknowledgment means (Ll) comprising a plurality of each of them associated with a type of interruption request, to recognize the arrival of the requests and to keep them available until they have been served: gate means (Pl) connected to the outputs of all the elements in said recognition means (Ll) , to signal arrivals of requests to the computer (CNT); storage means (R1) for storing interrupt requests and comprising a plurality of elements, each element being connected to the output of an element of the recognition means (L1) and arranged to transfer the respective request to the controller (CNT) when it receives a read command from said controller; readjustment means (P2, P3) inserted between the output of each element of the storage means (R1) and a readjustment input of each element of the recognition means (L1), to readjust the respective request upon arrival of the read command ; activating means (R2) connected to the readjustment means (P2, P3) to enable sending a request to the controller (CNT) by the recognition means (Ll) only in the presence of an activation signal provided by the controller . 3 0 ABR. 2001 Lisbon, Dr. Maria Silvina Fferreira Official Agent of Industrial Property R. Castilho, 201-3 ° E- 1070-051 LISBOA Telefs. 213 851339 - 213 854 C13