PL445772A1 - RFID modulation pulse shaping system - Google Patents
RFID modulation pulse shaping systemInfo
- Publication number
- PL445772A1 PL445772A1 PL445772A PL44577223A PL445772A1 PL 445772 A1 PL445772 A1 PL 445772A1 PL 445772 A PL445772 A PL 445772A PL 44577223 A PL44577223 A PL 44577223A PL 445772 A1 PL445772 A1 PL 445772A1
- Authority
- PL
- Poland
- Prior art keywords
- transistor
- gate
- source
- hrv
- resistor
- Prior art date
Links
- 238000007493 shaping process Methods 0.000 title abstract 2
- 239000003990 capacitor Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/355—Monostable circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Amplifiers (AREA)
Abstract
Układ kształtowania impulsów modulacji RFID posiada wejście (IN) dołączone do bramki pierwszego tranzystora (T5), który swoim źródłem dołączony jest do masy układu (gnd), a swoim drenem dołączony jest jednocześnie do źródła napięcia zasilającego układu (HRV) poprzez pierwszy rezystor układu (R5) oraz do masy układu poprzez drugi tranzystor układu (T6) oraz do bramki trzeciego tranzystora układu (T7) poprzez kondensator układu (Cec). Bramka trzeciego tranzystora (T7) jest również dołączona do źródła napięcia zasilającego (HRV) poprzez drugi rezystor (Rec), źródło trzeciego tranzystora (T7) dołączone jest do masy układu (gnd), a dren trzeciego tranzystora (T7) dołączony jest jednocześnie do źródła napięcia zasilającego (HRV) poprzez trzeci rezystor (R7) oraz do bramki czwartego tranzystora (T8). Czwarty tranzystor (T8) ma źródło dołączone do masy układu (gnd), a swoim drenem dołączony jest jednocześnie do źródła napięcia zasilającego układu (HRV) poprzez czwarty rezystor (R8) oraz do zacisku wyjściowego (OUT). Bramka czwartego tranzystora (T8) jest także dołączona do bramki drugiego tranzystora (T6), bramka trzeciego tranzystora (T7) jest także dołączona do zacisku napięcia referencyjnego (REF) poprzez diodę ograniczającą w postaci tranzystora (TI), który ma swoją bramkę dołączoną do swojego źródła czyli bramki trzeciego tranzystora (T7).The RFID modulation pulse shaping system has an input (IN) connected to the gate of the first transistor (T5), whose source is connected to the ground of the system (gnd), and its drain is also connected to the source of the supply voltage of the system (HRV) through the first resistor of the system ( R5) and to the ground of the system through the second transistor of the system (T6) and to the gate of the third transistor of the system (T7) through the system capacitor (Cec). The gate of the third transistor (T7) is also connected to the supply voltage source (HRV) through the second resistor (Rec), the source of the third transistor (T7) is connected to the system ground (gnd), and the drain of the third transistor (T7) is simultaneously connected to the source supply voltage (HRV) through the third resistor (R7) and to the gate of the fourth transistor (T8). The fourth transistor (T8) has its source connected to the system ground (gnd), and its drain is simultaneously connected to the system's supply voltage source (HRV) through the fourth resistor (R8) and to the output terminal (OUT). The gate of the fourth transistor (T8) is also connected to the gate of the second transistor (T6), the gate of the third transistor (T7) is also connected to the reference voltage terminal (REF) through a limiting diode in the form of a transistor (TI), which has its gate connected to its sources, i.e. gates of the third transistor (T7).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PL445772A PL445772A1 (en) | 2023-08-05 | 2023-08-05 | RFID modulation pulse shaping system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PL445772A PL445772A1 (en) | 2023-08-05 | 2023-08-05 | RFID modulation pulse shaping system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| PL445772A1 true PL445772A1 (en) | 2024-01-15 |
Family
ID=89543756
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PL445772A PL445772A1 (en) | 2023-08-05 | 2023-08-05 | RFID modulation pulse shaping system |
Country Status (1)
| Country | Link |
|---|---|
| PL (1) | PL445772A1 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3522454A (en) * | 1968-07-08 | 1970-08-04 | Northern Electric Co | Pulse control circuit |
| US3996482A (en) * | 1975-05-09 | 1976-12-07 | Ncr Corporation | One shot multivibrator circuit |
-
2023
- 2023-08-05 PL PL445772A patent/PL445772A1/en unknown
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3522454A (en) * | 1968-07-08 | 1970-08-04 | Northern Electric Co | Pulse control circuit |
| US3996482A (en) * | 1975-05-09 | 1976-12-07 | Ncr Corporation | One shot multivibrator circuit |
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