PL4109283T3 - Aparat i sposób zarządzania pamięcią w środowisku przetwarzania grafiki - Google Patents

Aparat i sposób zarządzania pamięcią w środowisku przetwarzania grafiki

Info

Publication number
PL4109283T3
PL4109283T3 PL22189858.8T PL22189858T PL4109283T3 PL 4109283 T3 PL4109283 T3 PL 4109283T3 PL 22189858 T PL22189858 T PL 22189858T PL 4109283 T3 PL4109283 T3 PL 4109283T3
Authority
PL
Poland
Prior art keywords
graphics processing
memory management
processing environment
environment
management
Prior art date
Application number
PL22189858.8T
Other languages
English (en)
Inventor
Niranjan L. Cooray
Abhishek R. APPU
Altug Koker
Joydeep RAY
Balaji Vembu
Pattabhiraman K
David Puffer
David J. Cowperthwaite
Rajesh M. SANKARAN
Satyeshwar SINGH
Sameer Kp
Ankur N. Shah
Kun TIAN
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Publication of PL4109283T3 publication Critical patent/PL4109283T3/pl

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00General purpose image data processing
    • G06T1/20Processor architectures; Processor configuration, e.g. pipelining
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10Address translation
    • G06F12/1009Address translation using page tables, e.g. page table structures
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10Address translation
    • G06F12/1027Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10Address translation
    • G06F12/1027Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1036Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure
    • G06F13/4063Device-to-bus coupling
    • G06F13/4068Electrical coupling
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10Address translation
    • G06F12/1081Address translation for peripheral access to main memory, e.g. direct memory access [DMA]
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10Providing a specific technical effect
    • G06F2212/1016Performance improvement
    • G06F2212/1024Latency reduction
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/30Providing cache or TLB in specific location of a processing system
    • G06F2212/302In image processor or graphics adapter
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60Details of cache memory
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/68Details of translation look-aside buffer [TLB]

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Image Generation (AREA)
PL22189858.8T 2017-04-07 2018-03-29 Aparat i sposób zarządzania pamięcią w środowisku przetwarzania grafiki PL4109283T3 (pl)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US15/482,690 US10380039B2 (en) 2017-04-07 2017-04-07 Apparatus and method for memory management in a graphics processing environment

Publications (1)

Publication Number Publication Date
PL4109283T3 true PL4109283T3 (pl) 2024-09-16

Family

ID=61868363

Family Applications (2)

Application Number Title Priority Date Filing Date
PL19202984.1T PL3614270T3 (pl) 2017-04-07 2018-03-29 Aparat i sposób zarządzania pamięcią w środowisku przetwarzania grafiki
PL22189858.8T PL4109283T3 (pl) 2017-04-07 2018-03-29 Aparat i sposób zarządzania pamięcią w środowisku przetwarzania grafiki

Family Applications Before (1)

Application Number Title Priority Date Filing Date
PL19202984.1T PL3614270T3 (pl) 2017-04-07 2018-03-29 Aparat i sposób zarządzania pamięcią w środowisku przetwarzania grafiki

Country Status (5)

Country Link
US (4) US10380039B2 (pl)
EP (4) EP3614270B1 (pl)
CN (1) CN108776949B (pl)
ES (2) ES2975950T3 (pl)
PL (2) PL3614270T3 (pl)

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Also Published As

Publication number Publication date
EP3614270A1 (en) 2020-02-26
US11360914B2 (en) 2022-06-14
EP3385850A1 (en) 2018-10-10
US20180293183A1 (en) 2018-10-11
US11768781B2 (en) 2023-09-26
PL3614270T3 (pl) 2023-01-30
EP4109283B1 (en) 2024-01-03
ES2975950T3 (es) 2024-07-18
EP3614270B1 (en) 2022-10-05
EP4325371A2 (en) 2024-02-21
US20210056051A1 (en) 2021-02-25
CN108776949A (zh) 2018-11-09
EP4325371A3 (en) 2024-03-20
EP3385850B1 (en) 2019-10-16
US10769078B2 (en) 2020-09-08
EP4109283A1 (en) 2022-12-28
US20220334982A1 (en) 2022-10-20
US10380039B2 (en) 2019-08-13
US20190391937A1 (en) 2019-12-26
ES2934458T3 (es) 2023-02-22
CN108776949B (zh) 2024-05-03

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