PL114951B1 - Head of tv receiver - Google Patents

Description

The subject of the invention is a television receiver head. In the United States, the frequency distribution of television stations for channels in the VHF and UHF bands is determined by the Federal Communications C! omim;ission (FCC). These channel frequencies are maintained with a high degree of accuracy during transmission. Recently, it has been suggested to use phase-locked loop (PLL) frequency synthesizers to precisely generate local oscillator signals with predetermined frequencies corresponding to different channels that can be selected by the television viewer. For example, a head using a phase loop is described in DLgi/tal Initegraited Circuits Application Note ICAN-6716 under the title "Low-Fower Digital Freauency Synthesizer Utiaizing GOS/MOS IC's" by Tt. E. Funik, published in 1972. RCA Solid State Daltaibook on COS /MOS Digital Integrated Circuits (SSD-203) published by RCA Corporation. Other types of heads for tuning television/video receivers to standard frequencies are also known. It is adapted from United States Patent No. 3,181,6353 entitled "tomaJtic Tuning AppaTafcus Haviiing Dual Freauency Sweep" awarded to Sakamoto and released on June 18, 1974, a device that contains two alternately tuned oscillators and a step of a previously determined starting frequency over the entire local oscillator frequency range for all transmitted channels. By counting the number of tunings and stops occurring in the oscillators, it is possible to determine the tuning voltage of a local oscillator nearby, but slightly below, the tuning voltage appropriate for tuning to a particular channel. Then, the auxiliary tuning circuit increases the control voltage to the value appropriate for tuning. Thus, heads with a frequency synthesizer for standard carrier frequencies are known. However, not all television signals are normally transmitted on the carrier frequencies of television stations. In some television distribution systems, such as home and motel installations, television signals are delivered to receivers via cables. In these and other systems using cables (or even microwave lines), the modulated transmit carrier can be demundulated and re-modulated at another frequency arbitrarily close to the station's standard transmitter carrier frequency before being fed to the receiver. , Insisted /; therefore, it is necessary to design a receiver head that ensures tuning of the receiver to such a non-standard carrier. 30 The head of the television receiver, according to the design, contains an input amplifier connected to the input of the television receiver connected to the receiving antenna, a mixer whose first input is connected to the output of the input amplifier, and whose output is connected to the input of the intermediate frequency signal amplifier, a voltage-controlled generator, the output of which is connected to the second input of the mixer, a reference frequency generator, a phase detector, the first input of which is connected through the first frequency divider to the output of the controlled generator voltage-wise, the second thread is connected via a wire dizieMk. frequencies with gear output * Reference frequency, low-pass filter, attached to | the output of the phase detector, an amplifier connected at the output of the low-pass filter, the output of which is connected to the control input of the voltage-controlled generator, and a channel switch. According to the invention, the head contains a channel number register, the inputs of which are connected via a multi-wire link to channel switch outputs, the first outputs are connected by a multi-wire link to the information inputs of the programmable first frequency divider, a logic circuit designed to determine the start of the counting, the first inputs of which are connected to the second outputs of the channel number register, a reversal counter, whose information inputs are connected by a multi-wire link to the first outputs of the logic circuit for determining the counting start, and the outputs are connected by a multi-wire link to the information inputs of the second programmable divider, and whose control input is connected to the second output of the reference frequency generator through the attached in series, a clock signal switching circuit and a clock shaping circuit, a dial stop logic circuit, the first inputs of which are connected by a multi-wire link to the outputs of the reverse counter, the second inputs are connected to the second outputs of the logic circuit for determining the counting start, and the output is connected with the first control input of the clock signal switching circuit, a switch designed to switch the head to work with the timer, the first pin of which is connected to the control input of the circuit designed to set the counting start. The second control input of the clock signal switching circuit is connected to the first output switching logic circuit, the first inputs of which are connected to the assigned outputs from the group of second outputs of the channel number register, and the second output is connected to the control input of the switch intended for switching the receiver from coarse tuning to fine tuning, connected between the output a set containing a low-pass filter and a filter, and the control input of a voltage-controlled generator, where the second input of the switching logic is connected to the first pin of the switch intended to switch the head to selectable operation. To the third input of the switch intended for switching the receiver from coarse tuning to fine tuning, a fine automatic frequency control system is connected, consisting of a frequency discriminator, an intermediate frequency amplifier connected at the output of the television receiver, and a signal amplifier for fine automatic frequency control. .Between the second output of the frequency discriminator and the third input of the switching logic circuit is a threshold detector, and between the fourth input of the switching logic circuit and the output of the precise automatic frequency control signal amplifier, a comparator is connected, the second input of which is connected with the output of the circuit containing a low-pass filter and an amplifier, connected at the output of the phase detector. The subject of the invention in an embodiment is presented in the drawing, in which Fig. 125 shows a block diagram of the head according to the invention, placed in a television receiver. , Fig. 2 is a schematic diagram of a portion of the head shown in Fig. 1, Fig. 3 is a schematic diagram of another portion of the head shown in Fig. 1, Figs. 4 and 5 are voltage versus frequency graphs relating to the portions of the head shown in Fig. Fig. 1, Fig. 6 shows a table helpful in understanding the operation of the head shown in Fig. 1. Fig. 1 shows the general arrangement of a television receiver using the head according to the invention. The high frequency signals are received by the antenna 12 and amplified by the high frequency amplifier 14. The reamplified high frequency signals are sent to mixer 16, where they are combined with a local oscillator signal at the appropriate frequency obtained according to the selected channel, as will be described later, to produce an intermediate frequency signal. The intermediate frequency signals are amplified by the intermediate frequency amplifier 18 and transmitted to the video signal detector 20. The video signal detector 20 extracts video signals including, for example, chrominance, luminance, and timing components from the amplified intermediate frequency signals. The video signals are sent to a video signal processing unit 22 containing, for example, channels for processing the chrominance, luminance and synchronization pulses of the video signal in a form suitable for driving the picture tube 24. In the described solution, the channel selection information is entered by the user using the channel selection keys 26. The keyboard 26 includes, for example, a set of calculator-type keys 1 which can be used to select VHF or UHF channels in a decimal system. The keyboard 26 may include, for example, a matrix circuit for converting information in decimal digits into binary information. The binary signals represent channel information and are sent to channel number register 28 via multi-wire circuit 30. Register 28 converts the binary channel selection information into other binary signals representing the Number N corresponding to the currently selected channel. For this purpose, register 28 may contain, for example, a ROM (Read Only Memory) memory in which information about the number N is stored for later reading in response to input binary signals from the keyboard 26. Binary signals representing the number N Multi -wire -wing 82 are transmitted to the programmed divider 34 frequencies used to divide the frequency of signals coming by the number N. Dzieller 34 will work in the phase petla system (PLL) together with the lodge osciller 50 soliti -heated, the initial divider of 52 frequencies, a reference crystal oscillator 40, a software divide-by-R circuit 38, a phase detector 36 and an amplifier 46 with a low-pass filter. This phase-loop circuit, combined with the channel selector, forms a frequency synthesizer which ensures that the television receiver is tuned to standard carrier frequencies. Most of the remaining blocks of the circuit shown in Fig. 1 are used to automatically tune the receiver to non-standard carrier frequencies that may occur, for example, in CATV and MATV systems. A more detailed block and logical diagram of such devices is shown in Figs. 2 and 3. A detailed description of the implementations shown in Figs. 2 and 3 is not necessary because they are easily understandable to those skilled in the art and result from the following description of the receiver head in Fig. 1. In this For this purpose, the components shown in FIGS. 2 and 3 and their interconnections are identified by use of the same numerical references that appear in FIG. 1, in the description of Fig. 1, reference is made to Zero-One logic signals relating to control signals associated with the head. These zero-one logic signals correspond to voltage levels near ground and approximately #+12 V, respectively, in the logic circuits of FIGS. 2 and 3, which may, for example, be manufactured using COS/MOS integrated circuit technology adapted to use such voltage. The TV receiver head in Fig. 1 has two types of operation. In the first type, without selection, i.e. when receiving the standard carrier frequencies assigned to the selected channels, the programmable divisor 34 by N and the programmable divisor 38 by R are set to predetermined values respectively. In this type of operation without selection suitable for tuning the receiver to standard 10 carrier frequencies, mode switch 54 is set by the user to its open position as shown in the drawing, so that the control signal ON SELECT (a logical one signal indicating the absence or completion of the control signal ON) DIAL SWITCH) is supplied to the switching logic unit 56 via wire 58 and to the count setting unit 62 via wire 60 to disable the circuit for receiving non-standard carriers as explained below. In response to the DIAL ON control signal, the logical switching unit 56 produces a STOP DIAL control signal #1 (zero logic signal) which is sent to clock switching unit 68 via link 90 to prevent clock pulses from being sent through divider 66 via A to the clock input via link 114 , reverse counter 42. As a result, the counter 42 does not change the R number of the divisor 38. In any mode of operation, the user selects a channel by pressing or otherwise operating the appropriate keys on the channel selection keyboard 26. The channel number register 28 receives binary signals representing information regarding the selected channel from the keyboard 26 and reads from its memory binary signals representing the number N corresponding to the selected channel. Binary information representing the number N is fed into a programmable divisor 34 dividing by N, so that it divides the frequency of the incoming signals by the number N. In addition to reading from memory the binary signals representing the number N for the new selected channel, both with and without select, channel select register 28 also provides a START PULSE control signal. A single logic signal that is applied to switch logic unit 56 via link 78 to reset switches 5612 and 5614 (shown in FIG. 3). , the operation of which is described below. In response to the START PULSE control signal, switching logic unit 56 generates a control signal (logical zero signal) on link 88 to set the synthesizer/AFT (Automatic Fine Tuning) switch 48 so that the output (link 122) of the low-pass filter and amplifier unit 46 is connected to the control terminal of voltage tunable oscillator 50 via link 128 to create the phase loop described above. A START PULSE control signal is also applied to logic circuit 62 setting the initial count point to set it to zero before entering new information from register 28 of the channel number. Channel number register 28, apart from outputting the appropriate number N to the programmable divider 1 34 and generating the START PULSE control signal, also produces three signals controlling the switching of band one - 20 25 30 35 45 517 , 114 951 8 signals (logic), namely : UHF control signal when a channel from the UHF range is selected (e.g. channels 14-83), LOV control signal when a channel from the lower part of the VHF range is selected (e.g. channels 2-6) and HIV control signal, 5 when a channel from the upper part of the VHF band is selected (e.g. channels 7-13). The band switch control signals in conjunction with the SELECT ON control signal are sent to logic circuit 62 setting the initial count point to cause it to select the correct number R. The band switch control signals are equal. not supplied in an appropriate manner (not shown) to voltage tuning elements, such as capacitive diodes in the oscillator and in the preliminary divider 52 by X, in order to ensure that the frequency of the input signal of the divider 34 is adjusted by N in accordance with the frequency band selected channel. The N and R values for tuning the receiver to the standard carrier frequency are given in the columns marked N SELECTING and NO-SELECTING and R NO-SELECTING in the table of Fig. 6. The values given in the table correspond to the implementation when the frequency of the crystal oscillator 40 is 5 MHz and the pre-divider 52 divides the frequency of the output signal of the voltage-tuned oscillator 50 by 256. Nadezy . Note that the values of N are equal to the required frequencies in MHz of the voltage-controlled local oscillator 50 output signals when mixed with the appropriate received standard carrier frequency to produce signals with a differential (intermediate) frequency equal to the image carrier 45 .76 MHz (standard intermediate image carrier frequency in most American receivers). Initially, when the user selects a channel and the N-programmable divider 34 and R-programmable divider 38 are set appropriately, the voltage-tunable oscillator 50 oscillates at any frequency (e.g., at some midpoint of the selected band). The operating frequency of voltage tunable oscillator 50 is modified in response to the constant current drive signal obtained from the output of the low-pass filter and amplifier assembly 46 until the output error signal produced by phase deiekfbar 36 indicates that there is no phase or frequency difference between the output signals. program communicators 34 through Ni 38 through R. At this time, the phase loop includes oscillator 50, pre-divider 52 pinz K, programmable divider 34 through N, phase detector 36, programmable divider 38 through R, crystal oscillator 40 and low-pass filter assembly with amplifier 46 ensures the generation of a local oscillator signal at the output of the voltage-tunable oscillator 50 having a frequency fLo dependent on the frequency fX of the output signal of the crystal oscillator 40 according to the following equation. NK fix= fxosc (1) R It should be noted that the output signal from spolu: 46 the low-pass filter and amplifier should have a range of amplitudes sufficient to cause a change in the oscillator signal. local in the entire frequency range for a given band, with the possibility of switching to an adjacent channel, and large enough to ensure tuning of the receiver to all channels in a given band. For example, in the lower VHF range, the low-pass filter and amplifier assembly 46 may provide a drive voltage in the range between the first and second voltages sufficient to tune the receiver to each of channels 2, 3, 4, 5 or 6. Signal The output from the local oscillator of the 50 -juvenile oscillator 'is sent to the mixer 16, where it is connected with the output signal of the amplifier of 14 great frequency to produce the intermediate traffic signal, whose nasal image is equal to the difference in the frequency of the nasal signal and the oscillator of the local oscillator - (for example) 45.75 MHz. The intermediate frequency signal is amplified by the intermediate frequency video amplifier 18 and the video information; is extracted from it by the video detector 20. The video signals are processed by the processing unit 22 to produce an image on the screen of the picture tube 24. When the user decides to receive signals in a distribution system with a non-standard carrier (i.e. ¬ CATV or MATV), then the mode selection switch 54 is set to the closed position, which generates a SELECT ON control signal (zero logic signal) to switch the heads to the second mode of operation with selection in the second mode of operation, with selection, when receiving a non-standard carrier frequency arbitrarily close (e.g. within ±2 MHz) to the frequency associated with the standard carrier frequency, the programmable divisor 34 dividing by N is again set to a fixed value corresponding to the selected channel. However, the divisor 38 dividing 30 by R is initially set to the first division number or a value lower than the division number or a value corresponding to the associated standard carrier frequency (for which the programmed divisor 38 dividing by R should be set to the first type during operation), and this division number is then incremented towards the second number greater than that corresponding to the associated standard carrier frequency until alignment at or above is achieved, which is fully explained below. In dialed operation as in unselected operation, the user selects a channel by pressing the appropriate key on the keyboard 65, channel selection turn 26, and as a result, binary information representing the number N is entered into the programmable divisor 34 dividing by N. Above/this register 28 of the channel number also produces a START PULSE control signal (a single logic signal), which is sent to switching logic unit 56 to set flip-flops 5612 and 5814 to their initial state. In response to the START PULSE control signal, switching logic assembly 56 generates a zero-signal (logic) control signal on link 88 to cause synthesizer/AFT switch 48 to initially connect the output terminal of low-pass filter and amplifier assembly 46 to the control terminal of oscillator 1 50 Moreover, the START PULSE control signal also resets the switching logic unit 62 that sets the counting start before entering new data from the channel number register 28. Talk, as in dialless operation, channel number register 28 produces each of the UHF, LOV or HIV control signals depending on which band the selected channel falls in. According to each of the HIV or LOV control signals produced by register 28 channel number and with the SELECTION ON control signal generated by the switch 54, the logic unit 62, which starts the counting, supplies binary signals to the reverse counter 42, the content of which reflects the first previously selected value smaller than the R value that should be selected for the same output channel. /taken at work without selecting. The first pre-selected values, corresponding to the various channels, entered into the reverse counter 42 during dialing operation are given in the "START R" column of the table in Fig. 6. The counting start logic unit 62 also produces complementary control signals. ce HIV, and LOV which is the negation of the HIV and LOV control signals. These complementary signals are sent to dial stop logic unit 78 via multi-wire link 64 to set it to one of two pre-selected values (depending on whether the selected channel is in the upper or lower VHF range) greater than the R value to which it would be set in unselected operation. The second previously selected value corresponds to the highest value of the R value to which the R number can be increased in selected operation. The second previously selected cd- values for the various channels are given in the "R END" column of the table in FIG. 6 in response to the control signal. ENABLE DIAL switching logic unit 56 generates the control signal DIAL COMMIT NO. clock inputs of the reverse counter 42. In response to these clock signals, the reverse counter 42 increases the number R from the first 10 previously selected value towards the second previously selected value. The second pre-selected values corresponding to the various channels are given in the END R column of Table 5* in FIG. 6. Operation of a phase loop in select operation including an oscillator 50, a pre-divider 52 dividing by K, a programmable divisor 34 dividing by N, a detector phase 36, oscillator ! ° crystal 40, programmable divider 38 dividing by R and the dockpass filter and amplifier assembly 46 are as they are without selection when adjusting the local oscillator frequency fLO according to equation (1). However, as each subsequent clock pulse from output 1 of circuit 66 is fed through A to reverse counter 42, the number R is successively increased by a predetermined amount, as shown in column AR of the table in Fig. 6 , where the AR gain for the various channels when A is selected as 2 is 2. As a result, the frequency of the local oscillator signal is reduced (i.e. reduced in steps). The starting and ending frequencies of the local oscillator signals and the frequency increments for the various channels are given in the columns fLO START, fLO END and ALp of the table in Fig. 6 for an implementation where A is chosen to be equal to 2. The output signal of the local oscillator 50 is so as in unselected operation, it is combined with the output signal of the high-frequency amplifier 14 in the mixer 16 to produce a modulated intermediate frequency signal, the carrier frequency of which is increased in direct dependence in a range corresponding to the frequency range of the local oscillator signal. The selection range for each channel is selected wide enough to encompass the required local oscillator signal frequency when mixed with a received non-standard frequency carrier in mixer 16 to produce a modulated intermediate frequency signal having an image carrier of a predetermined frequency. , e.g., 45.75 MHz. When the intermediate frequency carrier is reduced, the automatic fine-tuning frequency discriminator 52, connected to the output of the intermediate frequency amplifier 18, produces a voltage depending on the frequency difference between the intermediate carrier i 45.75MHz. FIG. 4 is an S-shaped diagram showing the voltage cd frequency relationship 412 of the automatic frequency control circuit 92 for typical voltages and frequencies for the implementation shown in FIGS. 2 and 3. It should be noted that the characteristic 412 in . S-shaped is determined for the amplitude range between the minimum and maximum amplitudes corresponding to the frequency deviation (±25 kHz). which is part of the frequency spacing pcr between channels (6 MHz). The direction in which the modulated intermediate carrier frequency is selected is also shown in Fig. 4. The output signal generated at the output (+) terminal of the automatic frequency control circuit 92 is fed to the threshold detector. wy 82 connects 104, where it is controlled. Threshold detector 82 produces a THRESHOLD control signal (one logic signal) when the output voltages at terminal (+) of circuit 92 increase above a predetermined threshold 414. The THRESHOLD control signal is applied to switching unit 56 106 , and sets the flip-flop 5612 of the switching unit 56. The amplifier 94 amplifies the automatic frequency control signal obtained at terminal (—) of circuit 92 and transmitted to it via link 124. The gain of amplifier 94 is selected so that the amplified automatic frequency control signal has substantially the same range of amplitudes between the first and second voltages as the output signal from the low-pass filter and amplifier assembly 46. This means that the amplitude range of the amplified output of amplifier 94 should provide substantially the same voltage for the selected channel when connected to oscillator 50 as the output from low-pass filter and amplifier assembly 46. It should be noted that the first and second voltages of the amplified automatic frequency control signal correspond to the deviations of the intermediate carrier frequency falling between the deviations assigned to the maximum and minimum voltages of the frequency discriminator characteristics connected to the automatic frequency control system 92. ci.Graphical representation of 512 dependencies voltage from the frequency of the amplified output signal of amplifier 94 is the graph in Fig. 5 for typical voltages and frequencies for the implementation shown in Figs. 2 and 3. The direction in which the frequency of the modulated intermediate carrier is selected is also shown . Also indicated are the approximate levels of control voltages supplied to the oscillator 50 corresponding to the channels located in the lower range of the VHF frequency band. Of course, similar characteristics apply to channels in the upper VHF band. Fig. 5 also shows a partial diagram of a stepped signal 514 similar to the output signal of the low-pass filter and amplifier 46, which causes an increase in the frequency of the modulated intermediate carrier. Comparator 84 compares the output signal of low-pass filter and amplifier assembly 46 (waveform 514) supplied on link 100 with the output signal of amplifier 94 (waveform 512) supplied on link 98 and produces a control signal COMPARISON one (logical) signal when these voltages become equal . The COMPARISON control signal is fed via wire 102 to the switching logic unit 56, where it sets the flip-flop 5014. When the 5012 flip-flop is set with the THRESHOLD control signal 10 15 20 30 35 40 BO 65, and the flip-flop 5614 is set with the COMPARISON control signal, in that time switching unit 56 generates a control signal (a single logic signal on link 88) to disconnect the output terminal 46 of the low-pass filter unit 46 and the amplifier to the oscillator control terminal 50 and connect to the oscillator control terminal 50 of the amplifier output terminal 94 Thereafter, the amplified auto frequency control signal controls the frequency of the output signal of local oscillator 50. If the frequency of the signal of local oscillator 50 changes due to changes in temperature, or element values, or similar reasons, relative to the fixed frequency, the control output of oscillator 50 is then switched from the output of the low-pass filter and amplifier assembly 46 to an amplified auto frequency control signal, with circuit 92 operating with negative feedback to provide the amplified auto frequency control signal to cause a change in frequency. liberties in direction opposite to changes caused by external factors or aging of system components. The THRESHOLD control signal indicates that the amplified automatic frequency control signal is changing in the correct direction to ensure frequency control. Threshold 414 in FIG. 4 corresponds to threshold 516 in FIG. 5. If switch 48 caused the amplified signals from circuit 92 to be fed to oscillator 50 before the amplified auto frequency control signal reached threshold 516, then automatic frequency control would not be achieved. when changing the control voltage supplied to the oscillator 50, because it would vary in the wrong direction, i.e., along the sloped part 518 of the characteristic 512, rather than along the sloped part 520. The control signal COMPARISON indicates that the amplified automatic part control signal frequency provides a control voltage which, when applied to the oscillator 50, causes the oscillator 50 to generate a local oscillator signal having a frequency sufficiently close to the frequency of the local oscillator signal assigned to the selected channel. For example, I assume that the selected channel is channel 4. Then, if switch 48 is set to connect the output terminal of amplifier 94 to the control input terminal of oscillator 50, when the amplified automatic frequency control signal voltage is at 516, the control voltage that is applied to the oscillator 50 corresponds to channel 2 rather than the control voltage required for channel 4. Thus, oscillator 50 is driven out of phase by the automatic frequency control when both THRESHOLD and COMPARISON control signals are present. Furthermore, when the THRESHOLD and COMPARISON control signals are NOT produced, the switch logic unit 56 produces the END OF DIAL 1 control signal (zero logic signal on link 90) to prevent clock signals from reaching the clock input of the reverse counter 42 , which prevents the contents of the programmed divisor 38 dividing J-R from increasing any further and thus terminating the dialing operation. If automatic frequency control is not provided before the number R reaches its final value (END R in the table of Fig. 6), then The dialing initiation logic unit 70 generates an END OF DIAL control signal #2 (a zero logic signal on link 108) to cut off the clock signals from the reverse counter clock input 42 and terminate the dialing. At this point the viewer will see a very poor quality picture and may select another channel or initiate a new selection cycle by selecting another channel and then reselecting the previously selected channel. Note that the frequency of the modulated carrier is reduced by reducing the frequency of the local oscillator signal. This is desirable because the first carrier selected is the desired image signal carrier and not the audio signal carrier of the adjacent channel. This helps avoid or minimize misalignment. It should be noted that if channel number register 28 produces a UHF control signal even when mode selector switch 54 is not closed to enable the receiver to tune to non-standard carrier frequencies, then logic assembly 56 in response to the UHF control signal, generates the END DIAL 1 control signal to cut off the clock signals from divider 66 divided by A from the clock input of reverse counter 42 fed through unit 68. Thus, the number R in the programmable divider 38 divided by R is not incremented when the UHF channel is selected, regardless of whether the mode selection switch 54 is pressed or not. This arrangement was introduced because most television distribution systems do not reprocess UHF carrier frequencies to transfer to other UHF frequencies, and therefore dialing work is not required when a channel in the UHF band is selected. However, it should be emphasized that the heads can be modified in this cell to enable operation with the selection of non-standard carrier frequencies in the UHF band for the application case. Although no detailed description of the implementation of the arrangements shown in Figs. it should be noted that, in terms of the circuit solution, the GD4027 integrated circuit, which is part of the software-divider 38 dividing by R, is a flip-flop that divides the frequency of the output signal from the counter implemented using the CD4O50 integrated circuit, which is also another component of the divider 38t, where it performs division by 2. As a result, the number of positions in the integrated counters CD4029 forming the reverse counter 42 is equal to only half of the value corresponding to R given in the table in Fig. 6. Moreover, only the signal Binary numbers mapping the numbers 1, 2 and 4 for io forming the most significant digit corresponding to the position of the multiple ten and the least significant digit corresponding to the position of the multiple one, numbers corresponding to the END R values, are fed to the 15th logic retaining unit 70 nia, because. the most significant and least significant digits corresponding to the END R signal, such as 8, are not required to create these signals. The binary signals for forming 20 times one hundred numbers output by the reverse counter 42 are not fed to the dialing stop logic unit 70 because the value of this item is: alone for. lower and upper VHF band and is not increased. 25 Although in the arrangement in FIG. 1, increasing the modulated/modulated intermediate carrier frequency is accomplished by decreasing the content of a programmable divisor 38 divided by R, it should be noted that the intermediate carrier frequency 30 may be alternately decreased by decreasing the value fed into the programmable N divider 34 as shown by the multi-wire link 126 connected between the reverse counter 35 42 and the programmable N divider 34. Furthermore, although the head tuning of FIG. 1 is described as reducing the intermediate carrier frequency frequency to avoid tuning 40 receiver to the nasal sound of a neighboring Canal, it is obvious that the frequency of nasal intermediacity can be increased. Patent fasteners 45 1. The head of the television receiver, contains the input amplifier. reception, the first input of which is connected to the output of the input amplifier, and the output of which is connected to the output of the input amplifier, and the output of which is connected to the input of intermediate frequency signals, a voltage-controlled generator, the output of which is connected to, the second inieszaicz input, reference frequency generator, phase detector, the first input of which is connected through the first frequency divider to the output of the voltage-controlled generator, the second input is connected through the second frequency divider to the output of the reference frequency generator, low-pass filter , an amplifier connected at the output of the phase detector, connected at the output of the low-pass filter, the output of which is connected to the input of the voltage-controlled generator, and a channel switch, characterized in that it contains a register (28) of the channel number, whose inputs are connected by a multi-wire link (30) with the outputs of the channel switch (26), the first outputs are connected by a multi-wire link (32) to the information inputs of the programmable first frequency divider (34), the logic circuit (62) is intended for to determine the counting start, the first inputs of which are connected to the second outputs of the channel number register (28), the reversible counter (42), whose information inputs are connected via a multi-wire link (64) to the first outputs of the logic circuit (62) to determine the counting time , and the outputs are connected via a multi-wire link (44) to the information inputs of the second programmable divider (38), and whose control input is connected to the second output of the reference frequency generator (40) through a series-connected circuit (68). switching on the clock signal and the clock signal shaping circuit (66), dial stop logic circuit (70), the first inputs of which are connected via a multi-wire link (72) to the outputs of the reverse counter (42), the second inputs are connected to the wire the second outputs of the logic circuit (62) for determining the counting start, and the output is connected to the first control input of the circuit (68) for switching clock signals, the switch (54) intended to switch the head to selectable operation, the first pin of which is connected to the control input of the system (62) intended for setting the counting start. 2. Head according to claim 1, characterized in that the second control input of the clock signal switching circuit (68) is connected to the first output of the switching logic circuit (56), the first inputs of which are connected to the assigned outputs from the group of second outputs of the channel number register (28), and the second output is connected to the control input of a switch (48) intended to switch the receiver from coarse to fine tuning, connected between the output of the assembly (46) containing the low-pass filter and the amplifier and the control input of the voltage-controlled generator (50). , where the second input of the switching logic circuit (56) is connected to the first output of the switch (54) intended to switch the head to selectable operation. 3. Head according to claim. 2, characterized in that the third input of the switch (48) intended for switching the receiver from coarse tuning to fine tuning is connected to a fine automatic frequency control system (92, 94), consisting of a frequency discriminator (92), the TV receiver's intermediate frequency amplifier (18) connected at the output and the fine automatic frequency control signal amplifier (94). 4. A head according to claim 2 or 3, characterized in that a threshold detector (82) is connected between the second output of the frequency discriminator (92) and the third input of the switching logic circuit (56), and between the fourth input switching logic circuit (56) and the output of the amplifier (94) for the precise automatic frequency control signal, a comparator (84) is connected, the second input of which is connected to the output of the circuit (46), containing a low-pass filter and an amplifier, connected at the output of the phase detector (36). . 1S 20 35 L0V 62 64^J i i l i tSO 44, M20 ,1f0_ \ i Mo 74-? uv 76 ? HIV 1 _Fll18 M4L 108- -70 .122 U2S 124TT.! ' '—* ,C6 * 48 77 V94 98; K83 106} %) TT 69 90- £~~^H 84t lB2 3 Moo i- -60 Z*TRIt**M£ M3l£P. Hk 2. ZflTRZYMRMf SELECT/£R M- ' f/e. u114951 W^G 70 FIG. 2. ZKTRZm.WVBlEB.% 70 m -901 r^-w ill. _l FIG. 3.114 951 DIRECTION WY3;ERRNtA^ 45725 44'75 4575 C2EST0TUM0SC(MHz) THRESHOLD t1f U VOLTAGE(v) FIG. 4. VOLTAGE (V) ' L +29 HRNAt 6A DIRECTION BLANK^ KRNRl 45.775 ^ hS.725 KfllML A KM fic. 5 u_KRNUt 2 \j; THRESHOLD +1 4175 STOWk -(MHz) CZE5T0TUU0SC ¦ IN FIG. 5. HRNRT \ VHF 1 WF \ UHF 2 3 4 5 6 7 8 9 10 11 11 13 14 15 16 N with WLBMB- MI Mi without hybferphi 101 1 (7/113 125 129 129 221 22% 233 239 245 251 257 517 523 529 83 l 93/ R B£Z MBIB- RfiNtA 1280 » V H " » « » » . « - - " " * WORKING WITH HYBIE8ANJEM Z? Ptfczmn 1250 » . » " 1266 .. * . ». ir NA.- - ." " KONi£C 1304 * p " 1292 t » - » « ../ M. i ii - ^# 2 i .. - - " - - " ri - - NA. - » 0342 fOS57 . 11571 125.95 132 . W 22344 229.51 23553 241.64 247.71 253 7S 259.94 NA... r " \ (MHz) 99.14 105.03 H0.92 120.74 126.63 219.95 224.89 230.94 236.78 2 42.72 24267 25A-61 NA ir a V Afw\ ~15&\ 167 176 192 201 345 354 364 j yi3\ 592 \ 392 j 401 AM. * * ] » j FIG. 6. PZGraf.Koszalin D-524 100 A-4 Price PLN 100 PL PL PL

Claims (6)

1. Claims 45 1. A television receiver head, comprising an input amplifier connected to an input of the television receiver connected to a receiving antenna, whose first input is connected to the output of the input amplifier, and whose output is connected to the output of the input amplifier, and whose the output is connected to the input of intermediate frequency signals, a voltage-controlled generator whose output is connected to the second input of the inieszaicz, a standard frequency generator, a phase detector whose first input is connected through the first frequency divider to the output of the generator voltage-controlled, the second input is connected through a second frequency divider to the output of the reference frequency generator, a low-pass filter, connected to the output of the phase detector, an amplifier connected to the output of the low-pass filter, the output of which is connected to the input of the controller - \ 15 114951 16 of a voltage-controlled generator, and a channel switch, characterized in that it contains a register (28) of the channel number, the inputs of which are connected by a multi-wire link (30) with the outputs of the channel switch (26), the first outputs are connected by a link multi-wire outputs (32) with information inputs of the programmable first frequency divider (34), logic circuit (62) intended to determine the beginning of the counting, the first inputs of which are connected to the second outputs of the channel number register (28), reversal counter (42), whose information inputs are connected via a multi-wire link (64) to the first outputs of the logic circuit (62) for establishing the counting timer, and whose outputs are connected via a multi-wire link (44) to the information inputs of the second programmable divider (38), and whose control input is connected to the second output of the reference frequency generator (40) through a clock switching circuit (68) and a clock shaping circuit (66) connected in series, a dial stop logic circuit (70) whose first inputs are connected via a multi-wire link (72) to the outputs of the reverse counter (42), the second inputs are connected to the second outputs of the logic circuit (62) for determining the counting start, and the output is connected to the first control input of the circuit (68). ) for switching on clock signals, a switch (54) intended to switch the head to dialing operation, the first pin of which is connected to the control input of the system (62) intended for setting the counting start. 2. Head according to claim 1, characterized in that the second control input of the clock signal switching circuit (68) is connected to the first output of the switching logic circuit (56), the first inputs of which are connected to the assigned outputs from the group of second outputs of the channel number register (28), and the second output is connected to the control input of a switch (48) intended to switch the receiver from coarse to fine tuning, connected between the output of the assembly (46) containing the low-pass filter and the amplifier and the control input of the voltage-controlled generator (50). , where the second input of the switching logic circuit (56) is connected to the first output of the switch (54) intended to switch the head to selectable operation. 3. Head according to claim. 2, characterized in that the third input of the switch (48) intended for switching the receiver from coarse tuning to fine tuning is connected to a fine automatic frequency control system (92, 94), consisting of a frequency discriminator (92), the TV receiver's intermediate frequency amplifier (18) connected at the output and the fine automatic frequency control signal amplifier (94). 4. A head according to claim 2 or 3, characterized in that a threshold detector (82) is connected between the second output of the frequency discriminator (92) and the third input of the switching logic circuit (56), and between the fourth input switching logic circuit (56) and the output of the amplifier (94) for the precise automatic frequency control signal, a comparator (84) is connected, the second input of which is connected to the output of the circuit (46), containing a low-pass filter and an amplifier, connected at the output of the phase detector (36). . 1S 20 35 L0V 62 64^J i i l i tSO 44, M20 ,1f0_ \ i Mo 74-? uv 76 ? HIV 1 _Fll18 M4L 108- -70 .122 U2S 124TT. ! ' '—* ,C6 * 48 77 V94 98; K83 106} %) TT 69 90- £~~^H 84t lB2 3 Moo i- -60 Z*TRIt**M£ M3l£P. Hk 2. ZflTRZYMRMf SELECT/£R M- ' f/e. u114951 W^G 70 FIG.2. ZKTRZm.WVBlEB.% 70 m -901 r^-w ill. _l FIG.3.114 951 DIRECTION OUT3;ERRNtA^ 45725 44'75 4575 C2EST0TUM0SC(MHz) THRESHOLD t1f U VOLTAGE(v) FIG. 4. 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