PH12012000300A1 - Sheet-molded chip-scale package - Google Patents

Sheet-molded chip-scale package

Info

Publication number
PH12012000300A1
PH12012000300A1 PH1/2012/000300A PH12012000300A PH12012000300A1 PH 12012000300 A1 PH12012000300 A1 PH 12012000300A1 PH 12012000300 A PH12012000300 A PH 12012000300A PH 12012000300 A1 PH12012000300 A1 PH 12012000300A1
Authority
PH
Philippines
Prior art keywords
sheet
scale package
molded chip
die
conductive pillar
Prior art date
Application number
PH1/2012/000300A
Inventor
J Juskey Frank
Berger Otto
Bantz Paul
Original Assignee
Triquint Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US13/252,083 external-priority patent/US8487435B2/en
Application filed by Triquint Semiconductor Inc filed Critical Triquint Semiconductor Inc
Publication of PH12012000300A1 publication Critical patent/PH12012000300A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

Landscapes

  • Packaging Frangible Articles (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

Embodiments include but are not limited to apparatuses and systems including a microelectronic device including a die having a first surface and a second surface opposite the first surface, a conductive pillar formed on the first surface of the die, and an encapsulant material encasing the die, including covering the first surface, the second surface, and at least a portion of a side surface of the conductive pillar. Methods for making the same also are described.
PH1/2012/000300A 2011-10-03 2012-10-03 Sheet-molded chip-scale package PH12012000300A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13/252,083 US8487435B2 (en) 2008-09-09 2011-10-03 Sheet-molded chip-scale package

Publications (1)

Publication Number Publication Date
PH12012000300A1 true PH12012000300A1 (en) 2015-07-10

Family

ID=48022351

Family Applications (1)

Application Number Title Priority Date Filing Date
PH1/2012/000300A PH12012000300A1 (en) 2011-10-03 2012-10-03 Sheet-molded chip-scale package

Country Status (2)

Country Link
CN (1) CN103035589B (en)
PH (1) PH12012000300A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9362191B2 (en) * 2013-08-29 2016-06-07 Infineon Technologies Austria Ag Encapsulated semiconductor device
US10797019B2 (en) * 2016-08-31 2020-10-06 Advanced Semiconductor Engineering, Inc. Semiconductor package and method for manufacturing the same
CN111584478B (en) * 2020-05-22 2022-02-18 甬矽电子(宁波)股份有限公司 Laminated chip packaging structure and laminated chip packaging method

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7476980B2 (en) * 2006-06-27 2009-01-13 Infineon Technologies Ag Die configurations and methods of manufacture
US7829380B2 (en) * 2006-10-31 2010-11-09 Qimonda Ag Solder pillar bumping and a method of making the same

Also Published As

Publication number Publication date
CN103035589A (en) 2013-04-10
CN103035589B (en) 2017-01-04

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