NZ205167A

NZ205167A - Flexible printed circuit:folded into stacked array

Info

Publication number: NZ205167A
Application number: NZ20516783A
Authority: NZ
Inventors: J A Scarlett
Original assignee: Int Standard Electric Corp
Priority date: 1982-08-26
Filing date: 1983-08-05
Publication date: 1986-09-10
Also published as: DE3328851A1; GB2126793A; AU1817983A; GB2126793B

Description

2 05 i 67 Priority Date(s): Corr.plcte Specification Filed: Ciass: Publication Date: fl .9. ..

P.O. Journal. No: NEW ZEALAND THE PATENTS ACT, 1953 COMPLETE SPECIFICATION "HIGH DENSITY PACKAGING OF INTEGRATED CIRCUITS" WE, INTERNATIONAL STANDARD ELECTRIC CORPORATION, a Corporation of the State of Delaware, United States of America, of 320 Park Avenue, New York 22, New York, United States of America, hereby declare the invention, for which we pray that a patent may be granted to us, and the rrethod by which it is to be performed, to be particularly described in and by the following statement: 2 0 516 7 This invention relates to a method and means for high density packaging of integrated electronics circuit modules or "chips As the complexity of integrated semiconductor circuits, or "chips", increases the problems of mounting, interconnecting and cooling the chips also increase. In any system or sub system which employs more than about two dozen high speed chips it is likely to be the interconnect and cooling which will dictate the overall performance and the reliability of the system.

Traditionally large systems are split into planar subassemblies in which the chips, packaged in dual in line packages (DIP), flat packs or chip carriers, are mounted on printed circuit boards with roughly 50 to 200 integrated circuits per board. The boards plug into a back wiring panel or frame which provides a third dimensional interconnect at one side or end of the equipment. When air cooling becomes inadequate, the customary cooling adopted comprises a thermal conducting path (usually of metal) from the chip packages to the outer frame of the unit. Such "heat ladders" are usually inefficient because of poor thermal contact between the chip carrier, flat pack or DIP and the metal heat ladder and also because of poor contact between the heat ladder and the frame of the unit. Increases in chip densities and in the number of chips used in large systems 205\67 are resulting in expensive multilayer boards which approach the present and likely future practical limits of manufacturing technology, coupled with elaborate metalwork to provide the necessary thermal paths from the chips to the outside air.

As the number of chips on a given planar substrate increases, the major problem in interconnection lies not so much in accommodating the tracks which must connect to any given chip, but in leaving spaces for those tracks which must pass the site of that chip without making connection to it. Multilayer board technology allows such interconnections to be accommodated, but at considerable expense.

The use of a two layer planar interconnect with via holes and so-called "x-y co-ordinate layout" where all tracks on one side of the interconnect run substantially parallel, with tracks on the other side crossing them orthogonally, and diagonal connections made by using a length of track on each side with a "via hole" at their intersect to produce an L shaped connection, enables any conceivable interconnect pattern to be implemented. However, in practical cases either the lines must be made very thin or the area taken by the interconnect must be large relative to the sizes of the chips being connected. The use of a multiplicity of planar cards or boards, either double-sided or multilayer, all plugged into a third dimensional back wiring panel, can 2 05 167 result in unacceptably high tracking densities in the areas of the cards adjaccnt to the connectors and in some tracks. which connect chips on non-adjacent cards or boards being unacceptably long.

The interconnection between the individual boards and the "back wiring" can prove a severe limitation in the implementation of very large logic systems in which the structure is random so there is a high probability of an interconnection being required between any given chip and any other chip in the entire system.

In many instances the difficulties of wiring can be minimised by the use of matrices (e.g. a memory system) and by the use of bus addressed systems.

This invention is an attempt to minimise the expense of providing an interconnect and of cooling the active devices especially in large systems which are not amenable to solution as a matrix or addressed bus system.

According to one aspect of the present invention there is provided a method of mounting and interconnecting integrated electronics circuit modules or chips, including the steps of mounting individual modules or chips to a flexible or flexi-rigid substrate with the modules or chips mounted on regions of the substrate which are separated by flexible portions of the substrate, the substrate being provided with conductive tracks to which the modules or chips have electr- 205 I 67 ical connections, folding the substrate at the flexible portions so that the regions on which the modules or chips are mounted are stacked substantially parallel to each other with gaps between adjacent ones of said regions, interposing between some at least of the stacked regions of the substrate electrical interconnect means, so that modules or chips are connectable to the modules or chips on adjacent ones of said regions of the substrate, and applying retaining compression to the stacked regions of the substrate- According to a second aspect of the invention there is provided an apparatus for high density packaging of integrated circuit modules or chips including a substrate having a plurality of module or chip mounting apertures arranged in regular spaced apart arrays, the arrays being separated by flexible portions of the substrate, the substrate being provided with a pattern or patterns of conductive tracks to which modules or chips mounted in the apertures make electrical connections, said patterns having regularly distribute electrical contact means positioned between the apertures in cach array, the substrate being foldable at each flexible portion between the arrays whereby the arrays can be placed into parallel stacking relationship one with another, electrical interconnect means adapted to make interconnections between corresponding contact means of adjacent arrays in the stack, and means for applying retaining compression 2 0 516 7 to the stacked arrays - The invention provides two major features, namely a substantially three-dimensional high density interconnect for electronic modules and a facility for cooling the modules or chips by direct contact with an inert fluid which can flow through the interstitial channels between the folded portions of the substrate.

Embodiments of the invention will now be described with reference to the accompanying drawings, in which:- Fig. 1 illustrates a substrate for mounting electronic integrated circuit modules; Fig. 2 illustrates a detail of the substrate of Fig. 1; Fig. 3 illustrates a section through the detail of Fig. 2; Fig. 4 illustrates schematically a mounting apparatus for integrated circuit modules using the substrate of Fig. 1? Fig. 5 illustrates an electrical interconnect; Fig. 6 illustrates an alternative form of electrical interconnect; Fig. 7 illustrates a form of substrate contact; and Fig. 8 illustrates another form of electrical interconnect.

The substrate shewn in Figs. 1-3 comprises a basic two-dimensional printed circuit 1 which may be single or double sided and can have four or more layers bonded together if required. The substrate is in the form of a long strip, the whole of which may be made as a flexible circuit or which 5167 has regularly spaced rigid portions separated by flexible portions la. The substrate may comprise a thin polyiitiide or other suitable plastics base 2 carrying copper tracking 3, 4, with via holes or pillars 5 interconnecting the layers of tracking. The tracking on each side is protected by cover coats of plastics material 6. At appropriate intervals apertures 7 are formed in the cover coats 6 and are "back etched" into the basic substrate to leave metal tracks 3 projecting into the aperture to form fingers or inverse baams 8, to the ends of which the integrated circuit modules 9, or other components, can be attached. The contact pads on the modules can be bonded 9a by thermocompression to gold plated ends of the beams 8, or by ultrasonic welding to aluminium deposited on the beam ends by vacuum metallisation.

The apertures 7 are preferably but not essentially arranged in arrays of rows and columns. Locating holes 10 are formed in regularly spaced positions with respect to the arrays of apertures. Between the columns of the arrays there are formed regularly spaced holes 11 through which contact can be made with underlying contacts, e.g. the plated through holes 5 which in turn make contact with the copper tracking.

Once all the modules or components have been fixed in place in the apertures the substrate 1 is folded at each flexible portion la, in alternate directions, to form a stack of arrays as shown in Fig. 4. During the folding process 205167 electrical interconnects 12 are placed in position to make electrical interconnections through corresponding holes 11 of adjacent arrays in the stack. The walls 13 of the outer casing are provided with, on one side of the stack, buffers or posts 14 against which the contacts of one endmost array rest. The opposing wall of the casing carries means whereby a retaining compression can be applied to the assembled stack of substrate and contacts. As shown in Fig. 4 these are simply springs 15, but in practice more elaborate arrangements would commonly be used.

To avoid the risk of electrical short circuits between the modules of one array and those of the next the inter-array connectors 12 can carry an insulating separator sheet 16. This separator can also be in the form of a cover coated single or double sided printed circuit, the tracks of which are used to interconnect, selected connectors 12 to allow the running of tracks past the modules or chips in the basic substrate 1.

Thus from any given module to a non adjacent module on the substrate, the designer has a multiplicity of routes available, and instead of any given module having only four immediately adjacent and four diagonally adjacent modules as on a conventional board, with this invention any module has a further 10 immediately adjacent modules on the two layers accessible through the layer to layer connections 12, t- 2 0^167 and a further 8 diagonally adjacent modules.

External connections to the substrate can be made through the pillars 14 and possibly the "springs" 15, and they can also be made at the folds la by folding the flexible 5 substrate over a small piece of rigid material, exposing the copper tracks, and inserting the fold into a conventional p.c.b. edge connector.

Layer to layer connections 12 can be made in a variety of ways. On small units, edge connectors over the folds as 10 suggested for external connections could possibly suffice.

One possible method is the use of double-ended sprung contacts (as used in some types of board testers) carried in plastics strips (Fig. 5). The heads of such contacts 17, 18 pass through the holes 11 in the cover coat 16 to contact 15 the conductors 3, 4. The bodies of the contacts have limited endwise float in the insulating carrier strips 19. In small units in which tolerance build-up would not be excessive the pins can be solid, instead of being sprung, relying on the flexibility of the substrate and the springs 15 at the end 20 of the unit to accommodate all tolerances.

Alternatively contact can be made through thin metal ribbons 20 wrapped around an insulating rod member 21 (Fig. 6). The top and bottom faces of such ribbons would preferably but not essentially gold plated, and could be formed into 25 spring contacts similar to those used in edge connectors. 205\ o7 Flat contact strips as sketched could be used, run over a composite support 21 which has outer layers of a compliant material. In such cases all contact 20 could be "printed" on (etched from copper cn) a thin, flexible substrate -i.e., the contacts would be in the form of a flexible pringed circuit wrapped around the support member 21 and held in place with adhesive or by mechanical fasteners. Alternatively, a known compliant connecting strip comprising thin alternate layers of conducting and insulating material could be used.

When such flat or essentially flat ended inter-layer contacts are used, the substrate 1 would have copper pillars 22 selectively plated through the holes 11 in the cover coat 6, preferably but not essentially gold plated on their ends.

Use of conducting tracks on the insulated separators 16 will necessitate slightly more elaborate arrangements of the inter-layer connectors 12. One possible form would be the use of metal pillars 23 rivetted and/or soldered into through-plated holes in a double-sided or multilayer flexible circuit 24 (Fig. 8) .

Cooling of such a three-dimensionally interconnected stack is best accomplished by immersing the stack in a fluid. In one possible implementation the unit can be immersed in an inert fluoro-carbon liquid of closely defined boiling point. The unit is contained in a sealed container with space above the liquid which forms a condensing chamber with 205167 a substantial outer surface area. Heat generated by the working of the unit vaporises the liquid, and at the limit would cause it to boil locally, the latent heat of vaporisation causing effective heat transfer from modules to liquid (and vapour). The vapour would cool and condense in the upper part of the chamber.

Units which might be inverted or subjected to mechanical « movement when working would have to use sealed, filled cases (with suitable provision for expansion such as a bellows assembly), relying on convection currents in the fluid to conduct heat from the modules to the outer case.

The use of a suitable inert fluid coulc obviate the need for any encapsulation of the chips.

Non-repairable units (e.g. for aerospace) can be potted in an electrically insulating, thermally conducting, compliant compound.

In the arrangements described above, the modules or chips mounted on the substrate are each mounted in an aperture cut in the substrate. However, other methods of mounting can be used. Thus if the modules to be mounted are D.I.P. units, the locations would each have a group of via holes appropriate to the number of terminals of the D.I.P. units, e.g. 14, 16 or 24 holes, in two parallel lines. Again, the substrate can have flat contact areas on one surface, or indeed on both surfaces, of the substrate to 2 0 5 1 6 mount in known manner flat packs, chip carriers, leadless inverted devices, or other mounting types appropriate to other units.

Whilst liquid cooling or encapsulation is to be preferred, the modules could be coated with a suitable encaps-ulant and the whole unit used without a sealed case, using, air cooling, preferrably fan blown.

Claims

x — r 205167 r* What we claim ls:-

1. A method of mounting and interconnecting integrated electronics circuit modules or chips, including the steps of mounting individual modules or chips to a flexible or flexl-rigld substrate with the modules or chips mounted on regions of the substrate which are separated by flexible portions of the substrate, the substrate being provided with conductive tracks to which the modules or chips have electrical connections, folding the substrate at the flexible portions so that the regions on which the modules or chips are mounted are stacked substantially parallel to each other with gaps between adjacent ones of said regions, Interposing between at least some of the stacked regions of the substrate electrical interconnect means, so that modules or chips are connectable to the modules or chips on adjacent ones of said regions of the substrate, and applying retaining compression to the stacked regions of the substrate.

2. A method as claimed in claim 1, and in which the modules or chips include D.I.P. units each of which is retained in place by via holes in the substate into which Its contact pins extend.

3. A method as claimed In claim 1, and in which the modules or chips include flat pack units each of which has conductive pads on its outer surface which are secured, e.g. by soldering, to conductive pads on the substrate.

N-Z. PATENT L' v

0 3FEB J93o

RSOElVm

13

2 0 5 & 6 7

4. A method as claimed in claim 1, and in which the modules or chips are each mounted in an aperture in the substrate.

5. A method of mounting and interconnecting a plurality of integrated electronics circuit modules or chips, including the steps of mounting individual modules or chips in apertures in a flexible or flexi-rigid substrate, said apertures being formed in spaced apart arrays in the substrate the arrays being separated by flexible portions of the substrate, the substrate being provided with a pattern or patterns of conductive tracks to which the modules or chips have electrical connections, which patterns also have regularly distributed electrical contact means positioned between apertures in each array, folding the substrate at each flexible portion between the arrays whereby the arrays are placed into parallel stacked relationship one with another, interposing between successive parallel arrays electrical interconnect means which make electrical connections between corresponding contact means of adjacent arrays, and applying retaining compression to the stacked arrays.

6. A method as claimed in claim 1 or 5, in which the substrate includes a layer of an insulating plastics material which bears said conductive tracks on one or both of its faces, and a coating of an insulating material overlaying the or each said face which bears conductive tracks, in which

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205167

each said aperture 13 made by removing said coating or coatings and back-etched into the insulating material to leave the conductive tracks exposed, and In which portions of the exposed tracks are removed to leave metal fingers of beams projecting into . the aperture the modules or chips being secured to said fingers or beams.

7. A method according to claim 1, 2, 3, ^, 5 or 6, including interleaving between adjacent arrays insulating separator sheets adapted to carry the electrical interconnect means.

8. A method according to claim 1, 2, 3, 5, 6 or 7,

wherein said electrical interconnect means comprise double ended spring contacts. .

9. A method according to claim 1, 2, 3, 4, 5, 6 or 7,

wherein said electrical Interconnect means comprise a plurality of metal ribbons wrapped around an insulating rod.

10. A method according to claim 1, 2, 3, 4, 5 or 6, wherein the electrical interconnect means comprise flexible printed circuit being wrapped around a supporting rod.

11. A method according to claim 7, wherein the separator sheets incorporate cover coated printed circuit tracks to make additional interconnections between electrical interconnects carried by the separator sheets.

12. A method according to any preceding claim including the step of making electrical connections to conductors in the flexible portions of the substrate when the latter form folds between adjacent layers in the stacked arrays.

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13- A method according to any preceding claim including enclosing the stacked arrays in a sealed container containing a cooling liquid which can flow through the spaces between the arrays in direct contact with the circuit modules.

I1!. A method according to any preceding claims, wherein the substrate portions in which the aperture arrays are formed are rigid.

15- A method of mounting and Interconnecting a plurality of integrated electronics circuit modules substantially as described with reference to the drawings.

16. Apparatus for high density packaging of integrated circuit modules or chips including a substrate having a plurality of module or chip mounting apertures arranged in regular spaced apart arrays, the arrays being separated by flexible portions of the substrate, the substrate being provided with a pattern or patterns of conductive tracks to which contact means of modules or chips mounted within the apertures make electrical connections, said patterns having regularly distributed electrical contact means positioned between the apertures in each array, the substrate being foldable at each flexible porcion between the arrays whereby the arrays can be placed In parallel stacked relationship one with another, electrical interconnect means arranged to make Interconnections between corresponding contact means of adjacent arrays in the stack, when placed in said stacked relationship, and means for applying retaining compression to said stacked arrays when in said stacked relationship.

N.Z. PATENT OFFICE

2 7 JUN1986

16

205167

17. Apparatus as claimed in claim 16, and in which the modules or chips include flat pack units each of which has conductive pads on its outer surface which are secured, e.g. by soldering, to conductive pads on the substrate.

18. Apparatus as claimed in claim 16, In which the substrate includes a layer of an Insulating plastics material which bears said conductive tracks on one or both of its faces, and a coating of an insulating material overlaying the or each said face which bears conductive tracks, and in which in each said aperture there are projecting conductive beams or fingers each integral with a respective ones of said conductive tracks, the modules or chips being secured to said fingers or beams.

19. Apparatus according to claim 16, Including insulating separator sheets interleaved between adjacent arrays, the sheets being adapted to carry the electrical Interconnect means.

20. Apparatus according to claim 16 or 19, wherein said electrical interconnect means comprise double ended spring contac ts .

21. Apparatus according to claim 16 or 19, wherein said electrical interconnect means comprise a plurality of metal ribbons wrapped around an insulating rod.

22. Apparatus according to claim 16 or 19, wherein the electrical interconnect means comprise flexible printed circuit conductor strips wrapped around a supporting rod.

Hi. PATENT Oi-PXJE

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23. Apparatus according to claim 19, wherein the separator sheets Incorporate cover coated printed circuit tracks to make additional electrical Interconnections between electrical Interconnect means carried by the separator sheets.

24. Apparatus according to any one of claims 16 to 23, Including electrical connection to conductors in the flexible portions of the substrate when the latter form folds between the adjacent layers in the stacked arrays.

25. Apparatus according to any one of claims 16 to 24, Including a sealed container in which the stacked arrays are positioned, the container including a cooling liquid which can flow through the spaces between the stacked arrays in direct contact with the circuit modules.

26. Apparatus according to any one of claims 16 to 25, wherein the substrate positions in which the aperture arrays are formed are rigid.

W-Z. patent vf :<E

2 3 JUL 1936

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27. Apparatus for mounting and interconnecting a plurality of Integrated electronics circuit modules substantially as described with reference to the accompanying drawings.

INTERNATIONAL STANDARD ELELCTRIC CORPORATION

P.M. Conrick Authorized Agent P5/1/1466

_M-Z. FATE-IV • .y-.jg

3 JUL ;*36

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19