NZ203995A - Integrated circuit:integrated capacitors arranged around contact pads - Google Patents

Integrated circuit:integrated capacitors arranged around contact pads

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Publication number
NZ203995A
NZ203995A NZ203995A NZ20399583A NZ203995A NZ 203995 A NZ203995 A NZ 203995A NZ 203995 A NZ203995 A NZ 203995A NZ 20399583 A NZ20399583 A NZ 20399583A NZ 203995 A NZ203995 A NZ 203995A
Authority
NZ
New Zealand
Prior art keywords
integrated circuit
substrate
edge
insulating layer
integrated
Prior art date
Application number
NZ203995A
Inventor
L Micic
D Mlynek
F Schmidpott
Original Assignee
Itt
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Itt filed Critical Itt
Publication of NZ203995A publication Critical patent/NZ203995A/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
    • H01L27/0218—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of field effect structures
    • H01L27/0222—Charge pumping, substrate bias generation structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0805—Capacitors only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/92—Capacitors having potential barriers
    • H01L29/94—Metal-insulator-semiconductors, e.g. MOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Description

TRUE COPY Priority Date(s): ."M :.?£■ Complete Specification Filed: ; Jj.'&S Class: BO.l fi.ji. MOI m.jlQP.
• * I ;Publication Date: . .. .&4 JAR J986».... P.O. Journal, No: .. .1/7.7.2*........ .'T ,'; NEW ZEALAND PATENTS ACT 1953 COMPLETE SPECIFICATION "MONOLITHIC INTEGRATED CIRCUITS WITH INTEGRATED CAPACITORS" WE, ITT INDUSTRIES INC., a Corporation of the State of Delaware, United States of America, of 320 Park Avenue, New York 22, New York, United States of America, hereby declare the invention for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: 2 03995 The present invention relates to a monolithic integrated circuit with integrated capacitors and a semiconductor substrate wherein the circuit elements are formed at or in the surface of one plane of the substrate, and wherein contact 5 pads are spaced along the edge of said surface.
As is well known, capacitors with values greater than about 10 to 50 pF are difficult to integrate because they require a disproportionately large area on a semiconductor chip; see, for example, the journal "Scientia-Electrica", 10 1963, pages 82 and 83.
An object of the invention is to provide a method by which integrated capacitors can be realized which, with a conventional integrated-circuit layout, would require an amount of area exceeding the limited area of the semiconduc-15 tor substrate. By "conventional layout" is means that the contact pads lie within a stripe along the edge of the surface of one plane of the semiconductor substrate, and that the circuit elements, their interconnecting leads, and the leads connecting them to the pads are arranged essentially in the 20 remaining area of the semiconductor surface, which is enc losed by the stripe just mentioned.
Accordingly, there is provided a monolithic integrated circuit with integrated capacitors and a semiconductor substrate in which the circuit elements are formed at or in 25 the surface of one plane of the substrate, and in which 2 03 9 95 contact pads are spaced along the edge of said surface, wherein at least one of the integrated capacitors is located in the usually uncovered surface areas between contact pads and between the latter'and adjacent circuit elements and the edge of i the substrate, and encloses at least part of at least one contact pad.
The invention will now be explained in greater detail with reference to the accompanying drawing, in which: Fig. 1 is a schematic plane view of one corner of a 10 monolithic integrated circuit with integrated capacitors arranged in accordance with the invention; Fig. 2 shows the structure of a preferred embodiment of a capacitor as used in the invention, and Fig. 3 is a plane view of a corner of another embodiment 15 of a monolithic integrated circuit with capacitors connected to further circuit elements.
Fig. 1 shows one corner of a monolithic integrated circuit according to the invention in a schematic plane view. Disposed in a stripe-like arrangement along the edge of the 20 substrate 1 are the contact pads 21, 22, 23, 24, 25, 26, 27, 28, which may be spaced at different intervals, as shown in Fig. 1; this spacing is dependent on the specific circuit layout. The elements 3 of the integrated circuit are not shown in Fig. 1, since they may be of any kind; it is illus-25 trated, however, that these circuit elements 3 are arranged 2 03995 essentially within the stripe formed by the contact pads 21..., but the stripe between the contact pads 23, 24, which extends up to the edge of the substrate 1 indicates that circuit elements may also tie disposed between the contact pads if necessa-5 ry.
According to/ the invention, those areas of the surface which lie between the contact pads and between the latter and adjacent circuit elements 3 and the edge of the substrate 1 include capacitors 4, 5, 6 which extend around at least part 10 of at least one contact pad. For example, the contact pads 22; 24, 26; 28 are enclosed by the respective capacitor 4; 5; 6 on all sides, while the contact pads 21, 23; 25, 27 are enclosed only in part. The specific layout will depend on the regui-rements of the integrated circuits to be designed. It should 15 be pointed out that in Fig. 1 the capacitors 4, 5, 6 are shown only with their maximum possible area for simplicity, without regard to their contact areas and connections. The areas occupied by the capacitors are thus separated from the adjacent circuit elements 3 and the adjacent or enclosed contact pads 20 by the respective safety distance, as shown in Fig. 1.
Fig. 2 shows schematically the structure of a preferred embodiment of a capacitor for an insulated-gate field-effect transistor, i.e. MOS, integrated circuit. Fig. 2a shows a plane view of the MOS capacitor, and Fig. 2b is a cross section 25 taken along line A-A of Fig. 2a. The first plate of the MOS 2 03995 capacitor is the semiconductor region 10 (Fig. 2b) below the (gate-) insulating layer 7 of the same thickness, which is formed together with the gate-insulating layer of the field-effect transistbrs. The dielectric of the MOS capacitor is thus aa insulating layer whose material and thickness correspond to those of the gate insulating layer of field-effect transistors. Outside the edge of the insulating layer 7, the region 10 passes into the edge region 11 of the same conductivity type, which partially encloses the capacitor.
This edge region 11 is formed simultaneously with the source and drain regions of the field-effect transistors and, consequently, is of the same conductivity type and has the same penetration depth and resistivity as these transistors.
The semiconductor region 10 is given the conductivity type opposite to that of the substrate either already during fabrication or during the operation of the integrated circuit. In the first case, the capacitor of Fig. 2 is a' type comparable to a depletion-mode transistor, i.e., a "depletion-mode" capacitor. In the latter case, it is an "enhancement-mode" capacitor.
The second plate of the capacitor of Fig. 2 consists of the conductive layer 8 overlying the insulating layer 7 and having an extension 9 which does not cover the insulating layer 7, see Fig. 2a, where that edge of the insulating layer 7 located at the extension 9 is indicated by a broken line. 203995 Thanks to this extension 9, electric contact to the second plate, i.e. the conductive layer 8, need not be made via the insulating layer 7; this would pose problems, particularly in an embodiment in which the conductive layer 8 is of polycrys-talline silicon, because the aluminium generally used as a contact metal may penetrate the polycrystalline silicon and reach the insulating layer 7, thereby destabilizing the threshold-voltage conditions in the "enhancement-mode" capacitor. Contact to the conductive layer 8 is, therefore, made in the area of the extension 9; this is indicated in Fig. 2a by the aluminium contact 13. Likewise, contact to the edge region 11 is made via an aluminium layer 12. In Fig. 2a and in Fig. 3, which will be explained below, such contact layers are marked with a cross. The cross-sectional view of Fig. 2b shows that outside the insulating layer 7 and the conductive layer 8, the substrate 1 is covered with a thicker insulating layer 18, through which contact is made to the edge region 11.
Fig. 3 is a place view of one corner of a monolithic integrated circuit according to the invention with capacitors 4, 5, 6 arranged for a preferred use. In an insulated-gate field-effect transistor integrated circuit, this preferred use consists in a combination with a substrate-bias generator circuit 17. Such generator circuits are known per se, ane one example consists of an integrated oscillator circuit and a rectifier N.Z, PATErn'OFfjeE -5s\sOVJ985 6 RECEIVED 2 03 9 95 circuit which uses parasitic capacitances of the integrated circuit as smoothing capacitors.
In the arrangement of Fig. 3, one of these parasitic capacitances, namely that between the substrate terminal and the ground^terminal, is enlarged considerably by one of the capacitors, namely the capacitor 5, so that the smoothing and buffering effect on the rectifier portion of the substrate-bias generator circuit 17 is greatly enhanced. The capacitor 5 is therefore connected to the substrate-terminal lead 16, which generally runs along the edge of the substrate 1, and, on the other hand, to the grounded lead 15, which is also connected to the contact pads 21, 27. When making contact to the capacitors, care must, of course, be taken to ensure that the correct polarity is chosen. In Fig. 3 it is therefore assumed that the integrated circuit is an n-channel circuit, so that the supply voltage is positive, and the substrate bias negative. In the case of the capacitor 5, therefore, the conductive layer 8 is connected via the extension 9 and the extension contact 13 to the positive voltage, i.e., the grounded lead 15, while the semiconductor region 10 is connected via the edge region 11 and the contact 12 of the latter to the lead 16 running to the generator circuit 17.
The capacitor 4 lies between the supply-voltage lead 14 and the grounded lead 15. It has at the point of connection with the lead 14 a contact corresponding to 9 in Fig. 2a, and 2 03 9 95 V at the point of connection with the lead 15 a contact corresponding to 12 in Fig. 2a. Through the capacitor 4, an improvement in the frequency response of the integrated circuit i with respect to, the supply voltage is thus obtained.

Claims (10)

2 03 9 9 5 What we claim is:
1. A monolithic integrated circuit with integrated capacitors and a semiconductor substrate in which the circuit elements are I formed at or in the surface of one plane of the substrate, and in whiah contact pads are spaced along the edge of said surface, wherein at least one of the integrated capacitors is located in the usually uncovered surface areas between contact pads and between the latter and adjacent circuit elements and the edge of the substrate, and encloses at least part of at least one contact pad.
2. A circuit as claimed in claim 1 which is integrated using insulated-gate field-effect transistor (MOS) technology, wherein the first plate of each of the capacitors is a semiconductor region which lies below a "gate" insulating layer formed simultaneously with the gate-insulating layer of the field-effect transistors and having the same thickness as the semiconductor region, and which, outside the edge of the insulating layer, passes into an edge region of the same conductivity type enclosing part of the edge of the insulating layer, and that the second plate is a conductive layer overlying the insulating layer and having an extension not covering the insulating layer.
3. An integrated circuit as claimed in claim 2, wherein the semiconductor region and the edge region were given a conductivity type opposite to that of the substrate already during fabrication. 2 03 9 95
4. An integrated circuit as claimed in claim 2, wherein only the edge region is given a conductivity type opposite to that of the substrate during fabrication, while the semiconductor region » has the opposite conductivity type during operation of the integrated circuit.
5. An integrated circuit as claimed in any one of claims 2 to 4, wherein the conductive layer with the extension is made of polycrystalline silicon.
6. An integrated circuit as claimed in claim 5, wherein at least part of the extension is covered with an aluminium contact.
7. An integrated circuit as claimed in any one of claims 2 to 4, wherein the conductive layer with the extension is made of aluminium.
8. An integrated circuit as claimed in any one of claims 2 to 7, wherein contact to the edge region is made via an aluminium layer covering at least part of said edge region.
9. An integrated circuit as claimed in any one of claims 2 to 8 and including a substrate-bias generator circuit, wherein a first capacitor, lying between contact pads, is connected to a supply-voltage lead and a grounded lead, and that a second capacitor, lying between other contact pads, is connected to a grounded lead and a lead connected to the substrate.
10. An integrated circuit substantially as herein described with reference to Figs. 1-3 of the accompanying drawings. It2. PATENT 0FPC8 ^ ITT INDUSTRIES, INC. i 2^31983 ■-P.M. Conrick : " " Authorized Agent 5/1/1224 - 10 -
NZ203995A 1982-05-07 1983-04-26 Integrated circuit:integrated capacitors arranged around contact pads NZ203995A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP82710027A EP0093818A1 (en) 1982-05-07 1982-05-07 Integrated monolithic circuit with integrated capacitors

Publications (1)

Publication Number Publication Date
NZ203995A true NZ203995A (en) 1986-01-24

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
NZ203995A NZ203995A (en) 1982-05-07 1983-04-26 Integrated circuit:integrated capacitors arranged around contact pads

Country Status (4)

Country Link
EP (1) EP0093818A1 (en)
JP (1) JPS58206150A (en)
AU (1) AU561266B2 (en)
NZ (1) NZ203995A (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60176557U (en) * 1984-04-28 1985-11-22 沖電気工業株式会社 integrated circuit chip
US4866567A (en) * 1989-01-06 1989-09-12 Ncr Corporation High frequency integrated circuit channel capacitor
JP2645142B2 (en) * 1989-06-19 1997-08-25 株式会社東芝 Dynamic random access memory
SE470415B (en) * 1992-07-06 1994-02-14 Ericsson Telefon Ab L M High capacitor capacitor in an integrated function block or integrated circuit, method of producing the capacitor and using the capacitor as an integrated decoupling capacitor
JP5052007B2 (en) * 2005-12-28 2012-10-17 住友電工デバイス・イノベーション株式会社 Semiconductor device

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3460050A (en) * 1967-07-18 1969-08-05 Westinghouse Electric Corp Integrated circuit amplifier
US3689803A (en) * 1971-03-30 1972-09-05 Ibm Integrated circuit structure having a unique surface metallization layout
US3911466A (en) * 1973-10-29 1975-10-07 Motorola Inc Digitally controllable enhanced capacitor
JPS5758351A (en) * 1980-09-24 1982-04-08 Toshiba Corp Substrate biasing device

Also Published As

Publication number Publication date
JPS58206150A (en) 1983-12-01
EP0093818A1 (en) 1983-11-16
AU1412883A (en) 1984-11-08
AU561266B2 (en) 1987-05-07

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