NO990075D0 - Storage cell with floating port and reduced charge leakage - Google Patents

Storage cell with floating port and reduced charge leakage

Info

Publication number
NO990075D0
NO990075D0 NO990075A NO990075A NO990075D0 NO 990075 D0 NO990075 D0 NO 990075D0 NO 990075 A NO990075 A NO 990075A NO 990075 A NO990075 A NO 990075A NO 990075 D0 NO990075 D0 NO 990075D0
Authority
NO
Norway
Prior art keywords
charge leakage
reduced charge
storage cell
floating port
floating gate
Prior art date
Application number
NO990075A
Other languages
Norwegian (no)
Other versions
NO990075L (en
Inventor
Bradley J Larsen
Tsung-Ching Wu
Original Assignee
Atmel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atmel Corp filed Critical Atmel Corp
Publication of NO990075D0 publication Critical patent/NO990075D0/en
Publication of NO990075L publication Critical patent/NO990075L/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
    • H10B41/46—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with an inter-gate dielectric layer also being used as part of the peripheral transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Non-Volatile Memory (AREA)

Abstract

A process for fabricating a floating gate memory cell (60) with reduced charge leakage. An oxide regrowth (73) is formed over the sides of the floating gate (69) and is then covered with an oxide protective coating (64, 66). The structure is applicable to salicide and non-salicide memory cells and is especially useful in floating gate memory cells with gate stacks having abnormally shaped side walls.
NO990075A 1997-05-09 1999-01-08 Storage cell with floating port and reduced charge leakage NO990075L (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US85369197A 1997-05-09 1997-05-09
PCT/US1998/008709 WO1998050960A1 (en) 1997-05-09 1998-04-30 Floating gate memory cell with charge leakage prevention

Publications (2)

Publication Number Publication Date
NO990075D0 true NO990075D0 (en) 1999-01-08
NO990075L NO990075L (en) 1999-03-08

Family

ID=25316673

Family Applications (1)

Application Number Title Priority Date Filing Date
NO990075A NO990075L (en) 1997-05-09 1999-01-08 Storage cell with floating port and reduced charge leakage

Country Status (7)

Country Link
EP (1) EP0934603A1 (en)
JP (1) JP2000513879A (en)
KR (1) KR20000023619A (en)
CN (1) CN1227001A (en)
CA (1) CA2259631A1 (en)
NO (1) NO990075L (en)
WO (1) WO1998050960A1 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6417046B1 (en) * 2000-05-05 2002-07-09 Taiwan Semiconductor Manufacturing Company Modified nitride spacer for solving charge retention issue in floating gate memory cell
KR100395755B1 (en) * 2001-06-28 2003-08-21 삼성전자주식회사 Non-volatile memory device and method of fabricating the same
CN100382317C (en) * 2003-12-19 2008-04-16 应用智慧有限公司 Spacer trapping memory
KR100634167B1 (en) 2004-02-06 2006-10-16 삼성전자주식회사 Semiconductor device and method for fabricating the same
KR100699830B1 (en) * 2004-12-16 2007-03-27 삼성전자주식회사 Device and manufacturing method of non-volatile memory device for improving the erasing efficiency
WO2006080064A1 (en) * 2005-01-27 2006-08-03 Spansion Llc Semiconductor device and method for manufacturing same

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5479018A (en) * 1989-05-08 1995-12-26 Westinghouse Electric Corp. Back surface illuminated infrared detector
US5424567A (en) * 1991-05-15 1995-06-13 North American Philips Corporation Protected programmable transistor with reduced parasitic capacitances and method of fabrication

Also Published As

Publication number Publication date
WO1998050960A1 (en) 1998-11-12
KR20000023619A (en) 2000-04-25
EP0934603A1 (en) 1999-08-11
JP2000513879A (en) 2000-10-17
NO990075L (en) 1999-03-08
CN1227001A (en) 1999-08-25
CA2259631A1 (en) 1998-11-12

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Legal Events

Date Code Title Description
FC2A Withdrawal, rejection or dismissal of laid open patent application