NO872467D0 - SYNCRONIC FIFO REGISTER. - Google Patents

SYNCRONIC FIFO REGISTER.

Info

Publication number
NO872467D0
NO872467D0 NO872467A NO872467A NO872467D0 NO 872467 D0 NO872467 D0 NO 872467D0 NO 872467 A NO872467 A NO 872467A NO 872467 A NO872467 A NO 872467A NO 872467 D0 NO872467 D0 NO 872467D0
Authority
NO
Norway
Prior art keywords
syncronic
fifo register
fifo
register
syncronic fifo
Prior art date
Application number
NO872467A
Other languages
Norwegian (no)
Other versions
NO170244B (en
NO872467L (en
NO170244C (en
Inventor
Mathias Hofmann
Original Assignee
Siemens Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag filed Critical Siemens Ag
Publication of NO872467D0 publication Critical patent/NO872467D0/en
Publication of NO872467L publication Critical patent/NO872467L/en
Publication of NO170244B publication Critical patent/NO170244B/en
Publication of NO170244C publication Critical patent/NO170244C/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/08—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Communication Control (AREA)
  • Shift Register Type Memory (AREA)
NO872467A 1986-06-16 1987-06-12 SYNCRONIC FIFO REGISTER NO170244C (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CH2418/86A CH671476A5 (en) 1986-06-16 1986-06-16

Publications (4)

Publication Number Publication Date
NO872467D0 true NO872467D0 (en) 1987-06-12
NO872467L NO872467L (en) 1987-12-17
NO170244B NO170244B (en) 1992-06-15
NO170244C NO170244C (en) 1992-09-23

Family

ID=4233345

Family Applications (1)

Application Number Title Priority Date Filing Date
NO872467A NO170244C (en) 1986-06-16 1987-06-12 SYNCRONIC FIFO REGISTER

Country Status (3)

Country Link
CH (1) CH671476A5 (en)
DE (1) DE3718469A1 (en)
NO (1) NO170244C (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2515226A1 (en) * 2011-04-21 2012-10-24 STMicroelectronics SA An arrangement

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL7713708A (en) * 1977-12-12 1979-06-14 Philips Nv INFORMATION BUFFER MEMORY OF THE "FIRST-IN, FIRST-OUT" TYPE WITH FIXED INPUT AND VARIABLE OUTPUT.

Also Published As

Publication number Publication date
NO170244B (en) 1992-06-15
CH671476A5 (en) 1989-08-31
DE3718469A1 (en) 1988-01-14
NO872467L (en) 1987-12-17
NO170244C (en) 1992-09-23
DE3718469C2 (en) 1989-06-22

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