CH671476A5 - - Google Patents

Description

DESCRIPTION The present invention relates to a synchronous FIFO register according to the preamble of patent claim 1.

A FIFO register (first in - first out) is known to be a digital memory with an output, on which the data words appear in the order in which they were written at the input, with a data word remaining at the output until one Read input receives a read signal, which causes the next data word to be routed to the output. Such FIFO registers, which consist of a control circuit and a flip-flop matrix with D-flip-flops arranged along parallel rows or columns, prove to be disadvantageous with regard to their relatively complex implementation.

The invention is therefore based on the object of creating a FIFO register which can be implemented with relatively little outlay on circuitry.

This object is achieved by the measures specified in the characterizing part of patent claim 1. Such a configuration of a FIFO register has the advantage of being very simple to simulate and enables it to be implemented in a particularly cost-effective manner with monolithic integration. Further refinements of the invention are specified in the dependent claims.

The invention is explained in more detail below with reference to a drawing, for example.

It shows:

1 shows the block diagram of a FIFO register according to the invention,

2 shows the circuit diagram of a control stage and a flip-flop column for such a FIFO register,

3 shows a time diagram of various signals in such a FIFO register,

Fig. 4 is a table to illustrate the so-called transparency of such a FIFO register.

The FIFO register according to FIG. 1 has a flip-flop matrix which consists of three series circuits, each with three memory cells U1, U2, U3, VI, V2, V3 and W1, W2, W3. Such a memory cell (data latch) is in principle a statically clocked D flip-flop, as is shown in the book “Semiconductor Circuit Technology” by U. Tietze and Ch. Schenk, Springer Verlag 1978, page 164. The middle memory cells U2, V2 and W2 are acted upon together with a control signal c, which is supplied by a further control stage C2 inserted between two control stages Cl and C3, the control stage C1 jointly comprising the memory cells U1, VI, W1 and the control stage C3 Controls memory cells U3, V3, W3.

Each control stage C1, C2, C3 has an input for a write command signal (strobe) S, S1 or S2, which is converted on the output side into the write signal S1, S2 or S3 for the next stage, if present. In addition, each control stage Cl, C2, C3 has a further input for a fill state signal F, Fl, F2, which is converted into the fill state signal Fl, F2 or F3 for the next stage, if present. The three control stages, which are supplied with a clock Tk, each have an additional input for a feedback write command signal; the first control stage C1 is supplied with the signal S2, the second with the signal S3 and the third with a read command signal r.

The control stage C2 according to FIG. 2 has an edge-triggered D flip-flop KS to which the clock signal Tk is applied, the D input of which is supplied with a new fill state signal g2, which is supplied by an AND gate U1, which is fed through an inverter NI Signal S3 and the output signal of an OR gate Gl summarizes. One input of this OR gate Gl is connected to the Q output of the D flip-flop KS which supplies the signal F2 and the other input is connected to the output of a further AND gate U2 which supplies the signal S2 and which supplies the inverted signal F2 to the output signal of an OR gate G2, which combines the signals F1 and S1. In addition, there is a further AND gate U3 which links the signal S2 to the clock signal Tk conducted via an inverter N2 and supplies the control signal c, it being possible to use a signal (not shown in FIG. 2) instead of the inverted signal Tk, which has the same periodicity as the signal Tk and ensures correct timing.

3, the clock Tk, the signals S1, S2, S3, the control signal c, the refill state signal g2, the data signals u,

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671 476

u2, u ', u'2 and the fill state signals F1, F2 are shown. The clock Tk is a rectangular signal, of which two rising edges at times PI and P3 and a falling edge at time P2 are shown. The time between points PI and P2 is provided for the preparation of the write command signals (straws) and the time between points P2 and P3 for the transfer of the data, which results in a cycle consisting of a control phase and a write phase. The signals S1, S2, S3 and g2 are active during the control phase and the signals c, u2, u '2 and u' during the write phase. The signals Fl and F2 update with the edge P3. The maximum possible clock depends on the one hand on the time that the signals F, Fl, F2, F3 need to go through the entire circuit and on the other hand on the time it takes for the data to get from u to u '. The corresponding maximum delay times determine the greatest possible clock frequency. The clock, however, can be slow.

The FIFO register according to FIG. 1 functions as follows:

The control stages C1, C2, C3 initiate a successive successive transmission of a data bit u = 1 or u = 0 via the three memory cells U1, U2, U3, respectively during the time in which the control signals b, c and d respectively Show value «1». The same always happens simultaneously with cells VI, V2, V3 and W1, W2, W3. The writing of the data u, v, w into stage 1 with the aid of the signal S and the reading u ', v', w 'from stage 3 with the aid of the signal r is extremely controlled in such a way that the two operations are largely independent of one another can be done. All 8 possible values from 000 to 111 are permitted for the control signals b, c, which results in 8 transfer options. The combination 000 for the signals b, c, d results in no data transfer. The successive combinations 000, 100, 010, 001 allow the input bit to be transmitted in a minimum time of three cycles. With the sequence of combinations 000, 110, 001 or 000, 100, 011, the input bit is transmitted in a minimum time of two cycles. The jump from states 000 to states 111 makes the FIFO register transparent in that the input bit reaches the output in a single cycle.

In the control phase of a single cycle, the shift is determined, i.e. it is decided whether a shift (e.g. c = 1) takes place or not (c = 0). At the end of the write phase, the fill level of level C2 is determined, that is, it is registered whether the memory cell of level C2 has been written, read or written and read, because the memory cell must be read once, in order to avoid bit loss or bit duplication to have. Determining whether the fill level is relevant or not is important because the memory cells retain their information even after they have been read.

In Fig. 1 only the last three control stages of a FIFO register are shown. If, for example, stage C1 is the first, the input for signal F or S would have to be grounded; because one of the two signals S or F is sufficient to cause the data to be written.

The circuit according to FIG. 2 works as follows:

The control stage C2 must generate two signals, the signal g2, which indicates the new relevant filling state, and the write command signal S2 (straws), which indicates to the stage C3 that the stage C2 is being written to. The signal F2 relates to the current filling state and states whether this is relevant (F2 = 1) or not relevant (F2 = 0). The new state of the signal g2 is accepted by the signal S3 via the AND gate U1 and is output as a signal F2 by the flip-flop KS with the rising edge P3. The signal g2 is determined by the condition g2 = XS3 • [F2 + (XF2 • (Fl + Sl »]), in which the prefix X is a negative symbol and Fl and Sl are the fill status or the write command status of the previous stage "0" or "1", so the relationships for signals S2, c and F2 apply:

S2 = (Fl + Sl) • XF2

c = S2 • XTk '

F2 (T> Tk ') = [S2 + F2 (T <Tk')] • XS3

where T is a time, X is a negation prefix and Tk 'is a time to which an active edge of the clock Tk corresponds.

The data stored in the cells of the previous stage may or may not be relevant; if they are relevant, they have to be read, that is, transferred, otherwise not.

If the values in the memory cells U2, V2, W2 of the 2nd stage are irrelevant and those of the 1st stage are either relevant or become relevant in this cycle and are to be adopted, the signal SI must be 1 or Fl = 1, so that the memory cells U2, V2, W2 can take over the relevant values during the write phase (Tk = 0). At the same time, level C2 must report whether the cells U2, V2, W2 have adopted relevant values (F2 = 1) or not (F2 = 0). This is done as follows:

If the 3rd stage does not read the relevant values stored in cells U2, V2, W2 of the 2nd stage, then the relevant values remain in these cells and F2 is equal to «1»; otherwise, if these relevant values are read, F2 must become "0". If the 2nd stage has irrelevant values (F2 = 0) and is described, then it would contain relevant values (F2 = 1) and the question remains whether the following 3rd stage reads the 2nd stage during this time or not . If they are not read (S3 = 0), they become relevant (F2 = 1); however, if they are read at the same time (S3 = 1), they remain irrelevant (F2 = 0), even though they were also written in this cycle. The transparency of the inventive FIFO register is verified by this property.

This transparency always exists when a number m of successive memory cells in a row has already been read and therefore has irrelevant values, so that the corresponding fill state signals have the values Fi = 1, F (i + 1) = 0, F (i + 2 ) = 0, ... (F (i + m) and F (i + m +1) = 1, in which Fi does not necessarily have to be Fl. Under these conditions, a new write command of the first stage (S = 1 , F = 0), that the relevant bit in position i jumps to position i + m in a single cycle.This special property is illustrated by means of the table according to Fig. 4, which relates to a FIFO register with 8 in series The signals S and r correspond to those of the same name in FIGS. 1 to 3.

In a further embodiment of the invention, the input OR gate, e.g. the gate G2 is omitted or the corresponding input for the signal S1 can be grounded in order to use only the fill status signal, e.g. to work with the signal Fl in Fig. 2. In this case, the FIFO register is only transparent between these control stages, but the clock frequency can be increased, whereby the clock signal itself can control all stages together. The clock frequency can be increased by a factor of n, for example, if n — 1 stages grounded in this way are present as first control stages among the various groups into which the entire series can be divided.

Preferably, all flip-flops (e.g. KS in Fig. 2) can be provided with a reset input in order to empty all columns of the flip-flop matrix together, if necessary, with the aid of a reset signal RS.

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2 sheets of drawings

Claims (8)

671 476 1. Synchronous FIFO register with a flip-flop matrix controlled by a control circuit for the serial shifting of data bits arriving in parallel (u, v, w), the control circuit having at least one control stage (C2) controlling a flip-flop column of the matrix, and the flip-flops Matrix memory cells are characterized in that the control stage (C2) is acted upon on the input side by a fill status signal Fl and a write command signal S1 and on the output side supplies its own fill status signal F2 and its own write command signal S2, the control stage (C2) being supplied with an additional write command signal S3 becomes, that for these signals the three relationships I S2 = (Fl + Sl) • XF2 II c = S2 • XTk ' III F2 (T> Tk ') = [S2 + F2 (T <Tk')] • XS3 apply, where c is the control signal for the flip-flop column, T is a time, X is a negation prefix and Tk 'is a time to which an active edge of the clock (Tk) corresponds. 2. FIFO register according to claim 1, characterized in that the fill state signal F1 and the write command signal S1 are supplied by a further control stage (Cl) connected upstream of the control stage (C2). 2nd PATENT CLAIMS 3. FIFO register according to one of claims 1 or 2, characterized in that the additional write command signal S3 is the write command output signal of a downstream control stage (C3). 4. FIFO register according to one of claims 1, 2 or 3, characterized in that the additional write command signal of the last stage (C3) is an external write command signal. 5. FIFO register according to one of claims 1 to 4, characterized in that the simplified relationship for at least one control stage S2 = Fl • XF2 applies to the write command signal. 6. FIFO register according to one of claims 1 to 5, characterized in that a flip-flop (KS) is present for implementing the third relationship, the clock input of which is supplied with the clock (Tk) and the D input of which is signal g2, for which the further relationship g2 = S3 • (F2 + S2) applies. 7. FIFO register according to claim 6, characterized in that several control stages (Cl, C2, C3) are each provided with such a flip-flop (KS). 8. FIFO register according to claim 7, characterized in that at least one of these flip-flops can be reset and is connected to a common erase line.