NO791811L - CONTROL SYSTEM. - Google Patents

Abstract

"Control system"

Description

This invention relates to a control system for supplying multiphase loads with an adjustable voltage/frequency derived from an electrical current source.

Such a control system has many applications in various industrial and commercial enterprises. This is particularly the case when the polyphase load comprises a polyphase motor. When this motor is an induction motor, it becomes possible to produce a motor that can work at variable speed while maintaining relatively low costs. Furthermore, when the motor is a multiphase synchronous motor, it is possible to achieve accurate speed control over a wide speed range /

It is consequently an aim of this invention to provide such a control system and this has been achieved by means of a system as specified in the patent claims.

An embodiment of this invention will now be described in more detail with reference to the drawings, where:

Figure 1 is a block diagram of the preferred embodiment

in

of the control system,

Figure 2 is a schematic of an oscillator and a 5 volt logic power supply in the system,

figure. 3 is a schematic of a master clock, switch controls,

and a phase sequence device,

figure 4 is a diagram of a phase control device,

Figure 5 is a diagram of the main switch, and

figure 6 is a diagram showing the fixed voltages

which is applied to an induction motor which

function of time.

With reference to Figures 1 to 6, the preferred embodiment of a control system 112 for a heat pump engine 110 will now be described. A block diagram for this system is shown in figure 1 and furthermore the interconnection of the individual circuits or schemes in figures 2 to 5 is also illustrated in figure 1.

An oscillator 1 supplies a pulse train to a logic power supply 2 and likewise to a phase control device 6. The logic power supply 2 converts the 12 volt DC voltage available from a vehicle battery B14 into a 5 volt DC voltage required for some of the integrated circuits which constitutes the control system 112. A h<p>wood clock 3 supplies a pulse train with a variable pulse repetition rate to a phase sequence device 5, both the main clock 3 and the phase sequence device 5 being controlled by switch control devices 4. A terminal TS on the main clock 3 allows a feedback signal which is derived on which in any known manner, controls the pulse repetition rate of the main clock 3. The output of the phase sequence device 5 is fed to the phase control device 6

which supplies correctly timed switching signals to a main switch 7 which connects each phase of the newly phased delta or preferably mesh-connected induction motor 110 with the correct terminals on the battery B14 in the correct sequence as will be explained in detail below.

In figure 2- are details of the circuits for the oscillator 1 and the logic power supply. 2 shown. The oscillator 1 comprises an integrated circuit IC13 (National 555) and resistors R114 and R115 together with a capacitor C119. Circuit IC13 oscillates at a pulse repetition rate in the range of "60 KHz to 160 KHz, which rate is determined by the resistance value of resistors R114 and R115 in series with charging capacitor C119 until a threshold voltage is reached on capacitor C119, which is then discharged through resistor R114, cycle repeats itself.

The other part of the circuit in figure 2 includes the logic power supply 2 and it is clear that the output from the circuit IC13 is fed to a flip-flop circuit IC14A which is designed to divide the oscillator's pulse repetition rate by 2 and also has complementary outputs with a gain factor ( duty cycle) of exactly 50%.

The output of the circuit IC14A is fed to a dc/dc-current dmformer comprising a counter clock arrangement working through a transformer Till whose primary and secondary windings 1

v

both are provided with a central outlet. The outputs of the circuit IC14A

are each routed through a series connection of a resistor and capacitor (R116 and C110 together with R117 and Clll) to respective buffer transistor switches Qlll and Q112. The series-connected resistors and capacitors prevent overloading of the buffer transistors Qlll and Q112 in the event of a failure of "one of the circuits IC13 or IC14A and likewise in the event of a low input voltage to the circuit IC14A. The resistors R118 and R119 in the collector circuit of the transistors

Qlll and Q112 reduce the load on the outputs of circuit IC14A and also limit the current through transistors Qlll and Q112.

It will be seen that transistors Qlll and Q112 together with their respective connected switching transistors Q113 and Q114 allow current to flow through the respective halves of the primary winding of transformer Till in alternating directions at a rate determined by the output of circuit IC13 through circuit IC14A. Induction coils Lill and L112 in the collector circuits for transistors Q113 and Q114 have a high impedance to parasitic oscillations, while capacitors C112 and C113 introduce positive feedback to the base of transistors Q113 and Q114 to thereby reduce their switching times by removing charge from the base/emitter junctions in these. Resistors R112 and R113 weaken this positive feedback to prevent self-oscillation. Diodes D119 and D110 protect transistors Q113 and Q114 from possible induced voltages of high amplitude and opposite polarity, and also allow the current to die after transistors Q113 and Q114 are switched off.

The Till transformer has a ferrite core and is a step-down transformer with only half the number of secondary turns compared to the number of primary turns. Consequently, a time-varying voltage of about 6 volts will appear across the secondary winding and this voltage is rectified by diodes Dill and D112 and smoothed by a capacitor C114 to provide a 5 volt supply voltage for some of the integrated circuits used throughout the control system. The interconnection between the logic power supply 2 and the other integrated circuits is not illustrated in detail and will be obvious to those skilled in the art.

As shown in Figure 3, the switch control devices 4 comprise a manually operated switch with 3 positions and with mechanically connected contacts Sl and S2, the middle position representing an OFF position while the two working positions represent COLD (forward) and HOT (reverse) .

It will be seen that operation of the switch control devices 4 causes one of two capacitors C121 or C122 to be charged through respective resistors R121 or R122 to the voltage 12 V supplied from the battery B14 while at the same time the other of the capacitors is discharged through a diode D121 or D122 to ground. Consequently, the input of only one of two Schmitt triggers IC9A and IC9B will go positive thereby causing the output of a 0G gate IC8 B,C to go negative. This change in logic state is transferred through an inverting circuit IC11D to a divide-by-2 flip-flop circuit IC14B, as shown in Figure 4, to enable it. In addition to this, the change in logic state is fed through a resistor R123 and a diode D123 to the positive input of an integrating circuit IC1A.

Circuit IC1A is connected to produce a ramp voltage across series-connected resistors R126 and R127 which is initially positive and decreases in amplitude as time increases. The change in logic state produced by the AND gate IC8 B,C ensures that a maximum positive voltage is initially present at the output of the integrating circuit IClA thereby ensuring that the main clock IC2 is slowed down to a low starting rate in the vicinity of 200 Hz. As the voltage at the positive output of the integration circuit IClA falls as a result of the charging of the capacitor C123, the voltage at the negative input of the integration circuit IClA will simultaneously rise due to the current through a resistor R125 and a diode D125 when discharging the capacitor C124. Accordingly, the voltage at the output of the integrating circuit IClA drops so that the voltage at the junction between resistors R126 and R127 is caused to drop and cause an increase in the pulse repetition rate of the main clock IC2 to a preset maximum. This maximum will be determined by the preset value of the resistor R12 0 and likewise by a voltage applied to the terminal TS of a conventional temperature sensor (not shown).

The main clock IC2 is a timing control circuit of the type LM322 .sWi works in astable mode by returning part of the output signal to the circuit's trigger input through a capacitor C126.. The operating frequency of the main clock IC2 is 1/(R120+R129).

(C125) Hz, while the output is a narrow negative pulse with a width of

approached equal to 2(R128) . (C126) -second.

The output of the main clock IC2 is fed directly to a wire W in Figure 4 and also to two cascaded counters IC3 and IC4 through a voltage divider formed by resistors R1212 and R1213. The outputs of the counters IC3 and IC4 are connected to the address inputs of three memory circuits IC6, IC7 and IC12. Counters IC3 and IC4 always count in the same direction and are reset by a NAND gate IC8A.

It appears that the output of the Schmitt trigger IC9B is connected to a flip-flop circuit IC5 which determines whether forward or reverse operation should take place. This is achieved by means of the output of the flip-flop circuit IC5 which comprises the most significant bit for the address input of the memories IC6, IC7 and IC12, as illustrated in Table I. The reset

of the counters IC3 and IC4 through the NAND gate IC8A is the same for both the forward and reverse functions, but the output of the flip-flop circuit IC5 switches the memories 'IC6, IC7 and IC12 into te distinct and different fields for addresses where the forward respectively - and backward programs are saved.

From Table I it appears that the outputs of the memories IC6, IC7 and IC12 comprise 9 bits and the complement of each of these bits is provided by nine inverting circuits IC10A to IC10F respectively IC11A to IC11C. Output bits from the memories IC6,

IG7 and IC12 and their complements are fed directly to the phase control device 6 as shown in Figure 4

Furthermore, the output of the integration circuit IClA in Figure 3 is fed through a resistor R1214 to the Schmitt trigger IC9C whose output is connected to the base of the transistor Q125. Its collector is connected to the 12 V supply voltage

while the emitter is connected by a wire Z in Figure 4. The ramp voltage appearing at the output of the integrator IClA will first activate the Schmitt trigger IC9C and thereby turn the transistor Q125 ON. Consequently, wire Z in Figure 4 is effectively connected to the 12 volt supply voltage from the beginning,

but after a predetermined delay, the transistor Q125 is turned OFF and will thereby effectively disconnect the line Z in figure 4 away from the voltage source 12V.

In Figure 4', circuit details of the phase control device 6 are shown, but only details of a single phase of the 9 phases in the preferred embodiment, so that repetitions are avoided.

Certain aspects of the circuit in Figure 4 are similar to the circuit in Figure 2. A divide-by-2 flip-flop circuit IC14B is, like the flip-flop circuit IC14A of Figure 2 / connected to the output of the circuit IC13 of Figure 2, which forms the output of the oscillator 1 of Figure 1. Moreover, the output of the inverting circuit IC11D in Figure 3 is also connected to the circuit IC14B to provide an on/off control for the operation of the flip-flop circuit IC14B.

In a similar way as shown in figure 2, the outputs from the flip-flop circuit IC14B in figure 4, are led through series-connected capacitors and resistors, respectively C131 and R135, R136, to transistor switches Q135, Q136 respectively Q137,Q138. These transistor switches switch or connect wires X and Y on

Figure 4 alternately to ground at half the rate determined by the pulse repetition rate of oscillator 1.

Each phase of the phase control device 6 comprises two identical circuits which are necessary to produce complementary outputs for the two switches per phase clamp on the main switch 7, as shown in detail in figure 5 Each of. the identical circuits in the phase control device 6 comprise one of several bistable circuits respectively IC15 to IC32, and one of several transformers Tl31

to T14 9 together with associated power circuits. Each of the bistable circuits IC15 to IC32 comprises a National 555 type circuit

which can be reset or switched between a monostable state and a flip-flop state with set/reset.

The trigger input on each bistable circuit IC15 to

IC32 is connected to wire W and therefore receives the output of the main clock IC2. In addition, the output and input of the inverting circuit for each phase in the phase sequence device 5 are connected to the blocking/activation input of the corresponding bistable circuit for the phase in question. Thus, the output (IC10A) of the inverting circuit IC10A is connected to the inhibit/enable input of the bistable circuit IC15 and the input (IC10A) of the inverting circuit IC10A is connected, with the inhibit/enable input of

the bistable circuit IC16.

Each of the bistable circuits IC15 to IC32 is connected to line Z by means of an associated resistor. For example, the bistable circuits IC15 and IC16 are connected to line Z by means of resistors R1324 and R1235, respectively. The output of each circuit IC15 to IC.32 is connected to the center tap of the primary winding of the corresponding transformer and consequently the output of the bistable circuit IC15 is fed to the center tap of the primary winding of the transformer T131.

To avoid the voltage drop in diodes Dill and D112 in figure 2, transistors Q131 and Q132 are connected to the secondary winding of transformer 131 with respective resistors R131 and R13 2 arranged to supply base current to saturate transistors Q131 and Q132 when required to conduct . In this way, the low collector/emitter connection voltage for the transistors will replace the relatively large forward voltage drop in the diodes so that significant power loss is avoided.

After the influence of the switch control devices 4

as described in detail with reference to Figure 3, the wire is first connected to the 12V power supply and therefore each of the bistable circuits IC15 to IC32 work as monostable circuits and deliver a pulse of predetermined duration for each pulse applied to the trigger input through the wire W.

Thus when the bistable circuit IC15 is activated

of the output IC10A for each pulse supplied by the master clock IC2,. a corresponding pulse of predetermined length occurs at the output of circuit IC15 and is applied to the center tap of the primary winding of transformer T131. However, when the circuit IC15 is blocked or deactivated by the output IC10A, no pulses are applied to the transformer T131. Due to the complementary relationship between the outputs IC10A and IC10A, either the bistable circuit IC15 was activated and the bistable circuit IC16 was deactivated, or vice versa.

During the first start-up time, the pulses delivered by the main clock IC2 will have an increasing repetition rate and consequently the output of each of the bistable circuits IC15 to IC32 will comprise a pulse train in which a majority of pulses occur in half the period and no pulses in the remaining part of period, as the ratio between pulses and pulse intervals for the aforementioned plurality of pulses increases as the frequency from the main clock IC2 increases.

In this way, the pulse waveform is as illustrated

in Figure 6 (described later), changed so that the effective voltage of each half-period pulse is reduced by modulation. The modulation is such that the effective applied voltage is reduced from its maximum possible value by providing a

adjustable number of short pulses each of the same duration, during the time allocated for the half-period pulse present during normal operation.

The aforementioned modulation allows the motor 110 to be started smoothly and run up to maximum speed. Thus, an effective phase voltage of only 0.3V is initially applied, in comparison with an effective phase voltage of 12V at full speed.

Furthermore, it is possible to set the first start-up period as well as the maximum speed can be regulated, so that the control system is able to operate a wide range of loads under different conditions. The use of feedback terminals TS makes it possible to carry out this regulation automatically using conventional feedback technology.

This first mode of operation continues until wire Z is disconnected from the 12V supply after a predetermined time thereby causing each bistable circuit IC15 to IC32 to operate in its mode as a changeover/reverse flip-flop circuit. score. In this mode, the first pulse received by e.g. circuit IC15, causing a single pulse to be applied to the center tap of the transformer's primary winding, the duration

of this pulse is determined by the output IC10A resetting the circuit IC15. Accordingly, the output of each bistable circuit IC15 to IC32 comprises a square wave with an efficiency of 50%.

This time sequence is used to allow starting of the engine 110 at a low speed and then, after the aforementioned predetermined period, operation of the engine at a higher speed.

It will be apparent to those skilled in the art that the power circuits assigned to each of the transformers T131 to T14 9 are very similar to those described in figure , except that no filtering of the output from the secondary winding takes place. Considering the transformer T131, the output voltage appearing between the center tap of the secondary winding and the emitters of the transistors Q131 and Q132 will therefore be an amplified or attenuated reproduction of the output voltage from the bistable circuit IC15. The degree of such amplification or attenuation is dependent on the turnover ratio in each of the transformers T131 to T149. In addition to this, the output voltage a from the transformer T13 2 is the complement of the voltage a.

The main switch 7 'on which the phase control device 6

figure 4 is connected with, appears in detail from figure 5. The main switch for the 9 phases A, B, C, D, E, F, G, H and I, each of which has a distance of 40° in time, comprises two transistor switches for each phase. For phase A, one transistor switch comprises a transistor Q141 together with a resistor R141 and a diode D141, while the other switch comprises a transistor Q142, a resistor R142 and a diode D142. The phase clamp A in Figure 5 is connected to the winding for phase A of the 9-phase delta or preferably mask-connected induction motor 110. If desired, however, other types of multiphase motors such as a synchronous motor can be used instead.

The voltage a is applied to the resistor R141 in Figure 5, i.e. the emitter of transistor Q141 is connected to the center tap of the secondary winding of transformer T131 while the base of this transistor is connected to the emitters of transistors Q131 and Q13 2 in Figure<4>.<p>£ similarly, voltage a (the complement of voltage a) is applied across resistor R142.

When the voltage a is positive, the transistor Q141 is turned ON so that the phase terminal A is connected to the positive terminal of the vehicle battery B14. At the same time that the voltage a ceases to be positive, the voltage a becomes positive and therefore the transistor Q14.1 will be turned OFF while the transistor Q142 will be turned ON

so that the phase terminal A is connected to the negative terminal of the battery B14. In this way, a pulsed voltage waveform is generated for each phase as illustrated in figure 6• Due to the inductance in each winding to which the pulse waveform is applied and the mutual connection between the phases, the current in each phase is essentially sinusoidal. Diodes Dl41 and D142 are arranged to allow current to pass when transistors Q141 and Q142 respectively are turned on

OF.

It is clear that, the rate at which the transistors Q141 and

Q142 is switched with, is the rate determined by the main clock IC2 in figure<3>fQg, consequently this rate determines the speed at which the induction motor 110 operates.

Furthermore, the pair of switches for each phase is operated so that each switch in one pair is turned on and off alternately, but corresponding switches in each pair are operated in sequence so that there is an identical time offset between each phase, resulting in the voltage waveform for each phase which is illustrated in figure 6,

except during the first start-up.

Preferred manufacturers of each of the above-mentioned integrated circuits are as follows:

It will also be clear to those skilled in the art that the two cascade counters IC3 and IC4 and the memories IC6, IC7 and IC12 can be replaced by a shift register in which a word comprising twice the number of bits of the memory output is initially stored in the shift register when the power supply is switched on, the circuit is switched on, and this word is shifted cyclically at a rate determined by the master clock. In this way, an output identical to that provided by the memories IC6, IC7

and IC12 be obtained. In such an arrangement, reversal of the motor 110 can be effected by reversing the shift direction in the shift register. It is also possible to achieve the same result with data selectors.

If, moreover, the load were to run from the motor so that the motor acts as a generator, power becomes available for recharging the battery B14 as the diodes D141 and D142 allow current to flow into the battery Bl4. All three features are important when the engine is the drive motor for an electric vehicle or drives a crane, for example.

Claims (8)

1. Control system for a multi-phase load with one phase terminal per phase and energized from a direct current source, which system comprises two electrically actuable switches for each phase of the load, one switch in each pair of which can be brought to connect the corresponding phase terminal of the load with one terminal of the direct current source and the other switch in each pair can is caused to connect the corresponding phase terminal with the other terminal of the direct current source, one sequence device connected to the switches to actuate the switches in each pair alternately and at the same time actuate corresponding switches in all said pairs in sequence, and a clock device connected to the sequence device to con- controlling the operating rate of the sequencer, whereby the operating rate of the sequencer controls the frequency applied to the polyphase load. 2. System according to claim 1, characterized in that the timing device comprises a clock with an adjustable pulse repetition rate. 3. System according to claim 2, characterized in that the sequence device comprises a logic circuit connected to the clock to receive pulses from it and provided with two outputs for each phase of the multiphase load, where the outputs of each pair are complementary and each output comprises a pulse train with pulse/gap ratio approximately equal to 50% and a pulse repetition rate that is directly proportional to the pulse repetition rate from the clock, which outputs from each pair are time-shifted relative to all other pairs by an integral multiple of a minimum time comprising the period of the pulse train divided by number of phases, and each output of each pair of outputs is connected to the corresponding switch in the corresponding pair of switches to influence it. 4. System according to claim 3, characterized in that the amplitude of the pulses in the pulse train is modulated to reduce the effective voltage per phase to which the load is applied. 5. System according to et. of the preceding claims, characterized in that each of the switch pairs comprises two transistors, of which one transistor is connected to one terminal of the direct current source and the other transistor is connected to the other terminal of the direct current source, and the corresponding phase terminal is connected between the two transistors, and all pairs of switches are connected in parallel with each other. 6. System according to one of the preceding claims, characterized in that the multiphase load comprises a multiphase motor. 7. System according to claim 6, characterized in that the direction of rotation of the motor is reversible by reversing the operation sequence of the switch pairs, and the rotation speed of the motor is regulated by the aforementioned timing device. 8. System according to claim 6 or 7, characterized in that the load comprises a motor generator and the said load is capable of recharging the direct current source.