CA1139361A

CA1139361A - Control system for polyphase loads

Info

Publication number: CA1139361A
Application number: CA000328863A
Authority: CA
Inventors: Roy A. Emmerton
Original assignee: LNC INDUSTRIES Ltd
Current assignee: LNC INDUSTRIES Ltd
Priority date: 1978-06-01
Filing date: 1979-05-31
Publication date: 1983-01-11
Also published as: IL57441A; CH633393A5; GB2022808A; NZ190517A; IT7923163A0; IT7923164A0; IL57442A; GB2022808B; IL57441A0; JPS558293A; FR2427733A1; ZA792500B; JPS558588A; IL57442A0; SE7904842L; DE2921678A1; NL7904354A; IT1121073B; FR2427564A1; SE7904843L

Abstract

ABSTRACT
The present invention discloses a control system for supplying a polyphase load from a DC supply. A pair of electrical switches are provided for each phase terminal of the load and the switches are alternately operated in sequence to connect each phase terminal to one or other terminal of the DC supply. Both the frequency and effective average phase voltage may be varied to suit the load.

Description

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The present invention relates to a control system for starting and running polyphase motors from an adjustable voltage frequency derived from an electrical source and in which the phase voltage is modulated during starting.
Such a control system finds a wide application in many industrial and commercial activities. This is especially the case where the polyphase motor is an induction motor, since a motor operable at an adjustable speed is then available at relatively low cost. Furthermore, when the motor is a poly-phase synchronous motor precise speed control over a wide range of speeds is possible.
It is therefore the object of the invention to provide such a control system.
According to the invQntio~ a~ herein broadly claimed there is provided a control system for starting and running a poly-phase motor having one phase terminal per phase and being energized from a d.c. supply, said control system comprising a pair of electrically operable switches for each phase of said motor, one switch of each pair being operative by a phase controller to connect the corresponding phase terminal of said motor to one terminal of said d.c. supply and the other switch of each pair being operative by said phase controller to connect said corresponding phase terminal of said motor to the other terminal of said d.c. supply; only one switch of each said pair of switches being operative at a time and the switches of each pair being operative alternately; said phase controller comprising a plurality of switchable bistable circuits each of which corresponds to one of said electrically operable switches and is switchable by switch means between a bistable running configuration and a . ., _ 1 _ 113~
monostable starting configuration; a master clock connected to said switch means and having an adjustable pulse repetition rate controlled thereby, having one output con-nected to a phase sequencer to control the rate of operation of same and another output connected to a monostable trigqer input of each of said switchable bistable circuits; and said phase, each of said phase sequencer outputs corresponding to, and being connected with, one of said switchable bistable circuits, and each of said pair of phase sequencer outputs having a predetermined phase relationship relative to each other pair of phase sequencer outputs, wherein during running of said motor said switchable bistable circuits are switched to said bistable running configuration to turn said switches on for a half period and off for the other half period at a rate determined by said master clock and in a sequence determined by said phase sequencer but at starting of said motor for an initial period only said switch means switches said switchable bistable circuits to said monostable starting configuration and increases said master clock rate:from a low value to turn said switches off as before but turn said switches on for a predetermined duration an adjustable number of times in each said half period to modulate the voltage applied to each said phase terminal, said adjustable number increasing with said master clock rate.

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One embodiment of the present invention will now be described with reference to the drawings in which:
Fig. 1 is a block diagram of the preferred embodiment of tlle control system, Fig. 2 is a circuit diagram of the oscillator and 5 volt logic power supply, Fig. 3 is a circuit diagram of the master clock, switch controls and phase sequencer, : ~
Fig. 4 is a circuit diagram of the phase controller, Fig. 5 is a circuit diagram of the main switch, and Fig. 6 is a graph of the phase voltages applied to the induction motor as a function of time.

1133~6~
Turning now to Figs. 1 to 6, the preferred embodi-ment of a control system 112 for the heat pump motor 110 will now be described. `A block diagram of the control system of the preferred embodiment is illustrated in Fig. 1 and, in addition, the interconnection of the detailed circuit diagrams illustrated to Figs. 2 to 5 is also illustrated in Fig. 1.
An oscillator 1 provides a pulse train to a logic supply 2 and also to a phase controller 6. The logic supply 2 converts the 12 volt DC voltage available at the vehicle batt-ery 814 to a 5 volt DC supply required for some of the various integrated circuits forming the control system 112. A master clock 3 supplies a pulse train of variable pulse repetition rate to a phase sequencer 5, both the master clock 3 and phase sequencer 5 being controlled by switch controls 4. A terminal TS of the master clock 3 permits a feedback signal derived in any known fashion to control the pulse repetition rate of the master clock 3. The output of the phase sequencer 5 is passed to a phase controller 6 which provides correctly timed switch-ing signals to a main switch 7 which connects each phase of the nine phase delta, or preferably mesh, connected induction motor 110 to the correct terminals of the vehicle battery B14 in the correct sequence as will be explained hereinafter in detail.
In Fig. 2 the circuit details of the oscillator 1 and logic power supply 2 are shown. The oscillator 1 comprises IC13 (National 555) and resistors R114 and R115 together with capacitor Cll9. IC13 oscilates with a pulse repetition rate in the range of 60K Hz to 160K Hz, this rate being governed by the resistance value of resistors R114 and R115 in series which charge capacitor Cll9 until a threshold voltage is reached on the capacitor Cll9 which then discharges through 113~36~
resistor Ril4, this cycle being repeated.
The remainder of the circuit illustrated in Fig. 2 comprises the logic supply 2 and it will be seen that the out-put from IC13 is passed to a divide-by-2 flip flop IC14A which divides the oscillator pulse repetition rate by 2 and, in addition, has complementary outputs with a precise 50~ duty cycle.
The output of IC14A is passed to a DC to DC converter which comprises a push-pull arrangement operating through a transformer Tlll in which both the primary and secondary wind-ings are centre tapped. The outputs of IC14A are each passed through a series connected resistor and capacitor (R116 and CllO together with R117 and Clll) to respective buffer tran-sistor switches Qlll and Q112. The series connected resistor and capacitor prevent overload of the buffer transistors Qlll and Q112 in the event of failure of either IC13 or IC14A and also in the event of low input voltage to IC14A. Resistors R118 and Rll9 in the collector circuits of transistors Qlll and Q112 respectively reduce the load on the out~uts of IC14A
and also limit the current through transistors Qlll and Q112.
It will be seen that transistors Qlll and Q112 together with their respectively connected switching transist-ors Q113 and Q114 permit current to flow through their res-pectlve halves of the primary winding of transformer Tlll in alternate directions at a rate governed by the output of IC13 via IC14A. Inductors Llll and L112 in the collector circuits of transistors Q113 and Q114 respectively present a high impedance to any parasitic oscillations whilst capacitors C112 1~3~61 and C113 introduce positive feedback to the bases of transist-ors Q113 and Q114 so as to reduce their switching times by removal of charge from their base-emitter junctions. Resistors R112 and R113 dampen this positive feedback to prevent self-oscillation. Diodes Dll9 and D110 protect transistors Q113 and Q114 from any induced voltages of high magnitude and reverse polarity, and also permit current to decay after the transist-ors Q113 and Q114 have been switched off.
- Transformer Tlll has a ferrite core and is a step-down transformer having only half the number of secondary wind-ings relative to the number of primary windings. Accordingly, a time varying voltage of approximately 6 volts appears across the secondary winding and this voltage is rectified by diodes Dlll and D112 and smoothed by capacitor C114 to provide a 5V
supply for some of the integrated circuits used throughout the control system. The interconnection of the logic power supply

2 to the remaining integrated circuits is not illustrated in detail and will be clear to those s~illed in the art.
As seen in Fig. 3, the switch controls 4 include a manually operated 3 position switch having ganged contacts Sl and S2, the centre position represents an OFF position whilst the two operative positions represent COLD (forward) and HOT
(reverse).
It will be seen that operation of the switch controls 4 causes one of capacitors C121 or C122 to be charged via resistors R121 or R122 respectively to the 12V supply from the vehicle battery B14 whilst simultaneously the other one of capacitors C121 and C122 is discharged via diode D121 or D122 respectively to ground. In consequence, the ini~ut of only one ~3g36~
of two Schmitt triggers IC9A and IC9B goes positive thereby causing the output of AND gate IC8 B,C to go negative. This change of logic state is passed via inverter ICllD to divide-by-2 flip flop IC14B of Fig. 4 to enable same. In addition, the change of logic state is passed via resistor Rl23 and diode Dl23 to the positive input of integrator IClA.
The integrator IClA is connected to provide a voltage ramp to series connected resistors Rl26 and Rl27 which is initially positive and reduces in magnitude within increasing time. The change of logic state produced by AND gate IC8B,C
ensures that a maximum positive voltage is initially present at the output of integrator IClA thereby ensuring that the master clock IC2 is slowed to a low starting speed in the vicinity of 200Hz. As the voltage on the positve input of the integrator IClA decays, due to the charging of capacitor Cl23, simultaneously the voltage at the negative input of integrator IClA rises due to current through resistor Rl25 and diode Dl25 discharging the capacitor Cl24. In consequénce, the voltage at the output of integrator IClA falls, thereby causing the voltage at the junction of resistors Rl26 and R127 to fall and producing an increase in tne pulse repetition rate of the master clock IC2 to a preset maximum. This preset maximum will be be determined by the preset value of resistor Rl20 and also by a voltage applied to the terminal TS by a conventional temp-erature sensor (not illustrated).
The master cloc~ IC2 is an LM322 timer operating in an astable mode by feeding a fraction of its output bac~ to its trigger input via capacitor Cl26. The operating frequency of the master cloc~ IC2 is l/(Rl20+Rl29).(Cl25) Hz whilst the li3~

output is a narrow negative pulse of width approximately 2 ( R12 8 ) . ( C12 6) seconds.
The output of the master clock IC2 is passed directly to line W of Fig. 4 and also to two cascaded counters IC3 and IC4 via a potential divider formed by resistors R1212 and R1213.
The outputs of counters IC3 and IC4 are connected to the address inpùts of three memories IC6, IC7 and IC12. The counters IC3 and IC4 always count in the same direction and are reset by NAND gate IC8A.
It will be seen that the output of Schmitt trigger IC9B is connected to flip flop IC5 which determines whether forward or reverse operation is to take place. This is achiev-ed by the output of flip flop IC5 comprising the most signifi-cant bit of the address input to memories IC6, IC7 and IC12 !
as illustrated in Table I. The resetting of tne counters IC3 and IC4 via NAND gate IC8A is the same for both forward and reverse functions, however, the output of flip flop IC5 switches the memories IC6, IC7 and IC12 to two distinct and different fields of addresses where the forward and reverse programmes respectively are stored.
It will be seen from Table I that the outputs of the memories IC6, IC7 and IC12 comprise 9 bits and the complement of each of these bits is provided by nine inverters IClOA to IClOF and ICllA to ICllC respectively. The output bits of the memories IC6, IC7 and IC12, and their complements, are passed directly to the phase controller 6 illustrated in Fig.
4 .
In addition, the output of integrator IClA of Fig.

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3 is passed via resistor R1214 to Schmitt trigger IC9C, the output of which is connected to the base of transistor Q125.
The collector of transistor Q125 is connected to the 12V supply whilst the emitter transistor Q125 is connected to line Z of Fig. 4 . The voltage ramp appearing at the output of integrat-or IClA initially enables Scnmitt trigger IC9C thus turning transistor Q125 ON. Therefore initially line Z of Fig. 4 is effectively connected to the 12V supply, however after a pre-determined delay, transistor Q125 is turned OFF, thereby effectively disconnecting line Z of Fig. 4 from the 12V
su~ply.
In Fig. 4, the circuit details of the phase con-troller 6 are illustrated, however, only the details of a single phase of the 9 phases of the preferred embodiment are illustrated in order to avoid repetition.
Some aspects of the circuit of Fig. 4 . are similar to the circuit of Fig. 2 . A divide-by-2 flip flop IC14B is provided and, like the divide-by-2 flip flop IC14A of Fig. ? , IC14B is also connected to the output of IC13 of Fig. 2 which comprises the output of the oscillator 1 of Fig. 1 . In addition, the output of inverter ICllD of Fig. 3 is also connected to IC14B in order to provide an on/off control for the operation of the divide-by-2 flip flop IC14B.
In a manner similar to that of Fig. 2 , the outputs of flip flop IC14B of Fig. 4 are passed via series connected capacitors and resistors C131 and R135, ~136 respectively, to transistor switches Q135, Q136 and Q137, Q138 respectively.

~139;~61 These transistor switches switch the lines X and Y of Fig.4~
to ground alternately at half the rate determined by the pulse repetition rate of the oscillator 1.
Each phase of the phase controller 6 comprises two identical circuits which are required to produce complementary outputs for the two switches per phase terminal of the main switch 7 illustrated in detail in Fig. 5 . Each of the identical circuits of the phase controller 6 comprises one of bistables IC15 to IC32 respectively and one of transformers T131 to Tl~9 respectively togetner with associated circuitry.
Each of the bistables IC15 to IC32 comprises a National 555 which is switchable between a monostable state and a set-reset flip flop state.
The trigger input of each bistable IC15 to IC32 is connected to line W and tnerefore receives the output of master cloc~ IC2. In addition, the output and input of the inverter for each phase of the ~hase sequencer S are connected to the inhibit/enable input of the corresponding bistable for that phase. Thus the output (IClOA) of inverter IClOA is connected to the inhibit/enable input of bistable IC15 and the input (IClOA) of inverter IClOA is connected to the inhibit/
enable input of bistable IC16.
Each of the bistables IC15 to IC32 is respectively connected to the line Z by means of a respective resistor.
For example bistables IC15 and IC16 are connected to the line Z by means of resistors R1324 and R1235 respectively. The out-put of each bistable IC15 to IC32 is connected to the centre tap of the primary winding of the corresponding transformer and 1~39;~6~
therefore the output of bistable IC15 is connected to the centre tap of the primary winding of transformer T131.
In order to avoid the voltage drop of the diodes Dlll and D112 of Fig. 2, transistors Q131 and Q132 are connected to the secondary winding of transformer 131 with resistors R131 and R132 respectively providing base current in order to saturate the transistors Q131 and Q132 when they are required to conduct. In this way the low collector-emitter saturation voltage of the transistors replaces the relatively large forward voltage drop of the diodes, thereby avoiding a sub-stantial power loss.
After operation of the switch controls 4 as described in detail with reference to Fig. 3 , line Z is initlally conn-ected to the 12V supply and therefore each of bistables IC15 to IC32 operates as a monostable producing a pulse of predeterm-ined duration for each pulse applied to the trigger input via line W.
Thus when bistable IC15 is enabled by the output IClOA, for each pulse produced by master clock IC2 a corres-ponding pulse of predetermined length appears at the output of bistable IC15 and is applied to the centre tap of the primary winding of transfor~er T131. However, when bistable IC15 is inhibited by the output IClOA no pulses are applied to the transformer T131. Because of the complementary relationship between outputs IClOA and IClOA, either bistable IC15 is enabl-ed and bistable IC16 is inhibited or visa versa.
During the initial starting time the pulses produced by master clock IC2 increase in repetition rate and thus the output of 113~36~
each of the bistables IC15 to IC32 comprises a pulse train in which there are a plurality of pulses for half the period and no pulses for the remainder of the period, the mark space ratio of the plurality of pulses increasing as the frequency of the master clock IC2 increases.
In this way the pulse waveform illustrated in Fig. 6 (to be described hereinafter) is altered so that the effective voltage of each half period pulse is reduced by modulation.
The modulation is such that the effective applied voltage is reduced from its maximum possible value by the provision of an adjustable number of short pulses each of the same duration during the time allocated for the half period pulse present during normal operation.
The abovedescribed modulation permits the motor 110 to be started smoothly and run up to maximum speed. Thus initially an effective phase voltage of only 0.3V is applied compared with an effective full speed phase voltage of 12V.
Furthermore, the initial start up period is able to be adjusted, as is the maximum speed, so that the control system is able to drive a wide range of loads under different condit-ions. The use of feedbac~ terminals TS permits this adjustment to be automatically achieved by means of conventional feedback techniques.
This initial method of operation continues until the line Z is disconnected from the 12V supply after a predeter-mined time thereby causing each of bistables IC15 to IC32 to operate in a set-reset flip flop mode. In this mode, the first pulse received by bistable IC15, for example, causes a single pulse to be applled to the centre tap of the primary winding of the transformer T131, the duration of this pulse being ~13~3~i1 determined when output IClOA resets bistable IC15. Thus the output of each bistable IC15 to IC32 comprises a square wave of 50% mark space ratio.
This timing sequence is used to permit the motor 110 to be started at a low speed and then, after the abovementioned predetermined period, be operated at a faster speed.
It will be apparent to those skilled in the art that the circuitry associated with each of the transformers T131 to T149 is very similar to that described in Fig. 2 save that there is not filtering of the output of the secondary winding. Thus for transformer T131, the output voltage a appearing between the centre tap of the secondary winding of transformer T131 and the emitters of transistors Q131 and Q132 is an amplified or attenuated reproduction of the output voltage of the bi-stable IC15. The degree of such amplification or attenuation is dependent upon the tunls ratio of each of transformers T131 to T149. In addition, the 113~;~61 output voltage a of transformer T132 is the complement of vol-tage a.
The main switch 7, to which the phase controller 6 of Fig. 4 is connected, is illustrated in detail in Fig. 5 .
The main switch for 9 phases A, B, C, D, E, F, G, H and I" each spaced 40 apart in time, comprises two transistor switches for each phase. For phase A one transistor switch comprises transistor Q141 together with resistor R141 and diode D141 whilst the other switch comprises transistor Q142, resistor R142 and diode D142. The phase terminal A of Fig. 5 is connected to the winding of phase A of the 9 phase delta, or preferably mesh, connected induction motor 110, however, if desired another type of polyphase motor such as a synchronous motor could be used instead.
The voltage a is applied to resistor R141 of Fig. 5 , that is the emitter of transistor Q141 is connected to the centre tapping of the secondary winding of transformer T131 whilst the base of transistor Q141 is connected to the emitters of transistors Q131 and 132 of Fig. 4. Similarly voltage a (the complement of voltage a) is connected across resistor R142.
When voltage a is positive transistor Q141 is turned ON thereby connecting phase terminal A to the positive terminal of the vehicle battery B14. At the same time as voltage a ceases to be positive, voltage a becomes positive and therefore transistor Q141 turns OFF whilst transistor Q142 turns ON there-by connecting phase terminal A to the negative terminal of battery B14. In this way a pulsed voltage waveform as illus-_ 14 1~3~61 trated in Fig. 6 is generated for each phase. Because of the inductance of each winding to which the pulsed waveform is applied and the interphase coupling, the current for each phase is substantially sinusoidal. The diodes D141 and D142 are provided to permit current to flow when transistors Q141 and Q142 have been turned OFF respectively.
It will be apparent that the rate at which transistors Q141 and Q142 are switched is the rate determined by the master cloc~ IC2 of Fig. 3 and therefore this rate determines the speed at which the induction motor 110 operates.
Furthermore, the pair of switches for each phase are operated so that each switch of a pair is turned on and off alternately, however, corresponding switches of each pair are operated in seauence so that there is identical time displace-ment between each phase resulting in the voltage waveform for each phase as illustrated in Fig. 6, except during the initial start up.
The preferred make and type for each of the integrat-ed circuits referred to above is as follows:-ICl(A) National 3900 IC2 " LM322 IC3 " 74LS163 IC4 " 74LS163 IC5 " 4027 IC6 Harris HM7611 IC7 Harris ~M7611 IC8(A-C) National 7400 IC9(A-C) National 74C14 IC10(A-F) National 7404 113~61 ICll(A-D) National 7404 IC12 Harris H~7611 IC13 National 555 IC14(A-B) National 4027 IC15-IC32 National 555 It will alsG be apparent to those s~illed in the art that the two cascaded counters IC3 and IC4 and the memories IC6, IC7 and IC12 can be replaced by a shift register in which a word, comprising twice the number of bits as the memory out-put, is intially stored in the shift register when power is applied to the circuit and this word is shifted cyclically at a rate determined by the master clock. In this way an output indentical to that of memories IC6, IC7 and IC12 can be obtained. In this arrangement reversal of the motor 110 is achieved by reversing the shift direction of the shift register.
The same result is also able to be achieved with data selectors.
In addition, should the load over run the motor so that the motor functions as a generator, then power is avail-able to re-charge the battery B14 since diodes D141 and D142 permit current to flow into the battery B14. This feature is of importance where the motor is the motor of an electric vehicle or is driving a crane, for example.

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Claims

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A control system for starting and running a polyphase motor having one phase terminal per phase and being energized from a d.c. supply, said control system comprising a pair of electrically operable switches for each phase of said motor, one switch of each pair being operative by a phase controller to connect the corresponding phase terminal of said motor to one terminal of said d.c. supply and the other switch of each pair being operative by said phase controller to connect said corresponding phase terminal of said motor to the other terminal of said d.c. supply; only one switch of each said pair of switches being operative at a time and the switches of each pair being operative alternately; said phase controller comprising a plurality of switchable bistable circuits each of which corresponds to one of said electrically operable switches and is switchable by switch means between a bistable running configuration and a monostable starting configuration;
a master clock connected to said switch means and having an adjustable pulse repetition rate controlled thereby, having one output connected to a phase sequencer to control the rate of operation of same and another output connected to a monostable trigger input of each of said switchable bistable circuits;
and said phase sequencer having a pair of complementary outputs for each said phase, each of said phase sequencer outputs corresponding to, and being connected with, one of said switchable bistable circuits, and each of said pair of phase sequencer outputs having a predetermined phase relationship relative to each other pair of phase sequencer outputs, wherein during running of said motor said switchable bistable circuits are switched to said bistable running configuration to turn said switches on for a half period and off for the other half period at a rate determined by said master clock and in a sequence determined by said phase sequencer but at starting of said motor for an initial period only said switch means switches said switchable bistable circuits to said monostable starting configuration and increases said master clock rate from a low value to turn said switches off as before but turn said switches on for a predetermined duration an adjustable number of times in each said half period to modulate the voltage applied to each said phase terminal, said adjustable number increasing with said master clock rate.

2. A control circuit as claimed in claim 1 wherein said switch means is connected to said phase sequencer and is operable to change said predetermined phase relationship to reverse the direction of rotation of said motor.

3. A control system as claimed in claim 1 or 2 wherein each of said switch pairs comprises two transistors, one of said transistors being connected to one terminal of said d.c.
supply and the other of said transistors being connected to the other terminal of said d.c. supply, the corresponding phase terminal being connected between said two transistors, and all said pairs of switches being connected in parallel to each other.