NO750303L - - Google Patents

Description

This invention relates generally to improvements in numerical calculators and is more particularly directed to new and improved computer systems where the computer is a microprogrammed one. device based on integrated circuits.

In the field of digital data processing, it is common practice

to use system structures that have been developed taking into account high equipment costs. This limitation has resulted in the centralization of system management to devices referred to as the central processing unit and main memory units. On

because of this extensive and expensive centralized machine equipment that had to be controlled, operating systems (master control programs - English: "Master control programs") have been developed to

make the utilization of the equipment more general by dividing it into a number of programs or tasks. The system structures that were the result of these considerations are very general and, as a result, unnecessarily complicated in the special cases and ineffective when it comes to a large number of special situations. This type of structure has a division in an irregular way and is implemented mainly by means of sequence logic in fixed current circuits. When microprogramming techniques are used, the basic functional structure of the system is not changed, as the micro-coded processing units or processors still follow a register-oriented, clock-controlled sequential structure.

The new technology based on integrated circuits, e.g.

of the MSI type and the LSI type which provide the essential elements of a computer processor on a single chip, can be effectively utilized only if a new set of design rules or restrictions are followed. LSI technology requires e.g. regularity in the machine equipment and assignment of specialized or complicated algorithms to circuit chips. As memories based on integrated circuits are further interconnect-compatible with logic based on integrated circuits, the register-oriented processor structure can

ning is eliminated by distributing the system's circuit memory throughout the system. This, of course, eliminates the need for a centralized main memory subsystem. When it is possible to distribute the system memory throughout a system, it is desirable to eliminate the previously necessary operating systems for central control.

In order to be able to use LSI technology effectively, a system structure that results in a well-shaped and regularly divisible system is necessary. Although almost all microprogramming techniques that have been used in the past have this underlying purpose, prior art programming techniques have not been able to produce a system that is efficient to program and efficient in the execution of its algorithms. In other words, these previously known microprogrammed systems exhibit a total lack of continuity between what the machine language is and what the user needs in terms of programming and language. This is the case because prior art machine microcode languages are serial and binding in nature, which is in direct contrast to what is required by or in the technology with respect to regularity and non-binding of complex functions.

It is. an object of this invention is to provide a digit processing unit or processor that can be used as a basic component or building block of a calculator, such as a multiprocessor calculator that does not need to use a main control program or require an extensive interrupt or interrupt system and which has improved emulation capabilities.

The inherent problems in central systems and other conditions that are mentioned above and which together relate to the aforementioned purposes, are in this case solved in a binary data system in which data archives are stored - (data files) composed of data fields and data characters, and the current circuits in the system has circuits for receiving these. A data field contains the address of the data archive in the warehouse. The system can generally be described - as will be done in the following - as a data-driven system.

The general purpose of this invention is more particularly achieved by using a multi-character vocabulary in a character-series type data processor where two of the characters are used to define the start and end of a particular data field. Each character is represented by a plurality of binary bis. The data structures are organized in the data archive containing fields in such a way that expansion and contraction or contraction of these fields is permitted. Each data field is preferably terminated by a field end code which triggers a comparison between the count of start and end field characters in the data structure and a reference count. The structure and organization of an archive is described by the content of the first field in the relevant archive. A program or a process is executed under the influence of the "interconnection of pairs of data archives, where each pair has a data archive containing a part of the program and the other data archive contains the operands for this part of the program. One of these data archives can be located in the data process -ren's storage area (static), while the rest is supplied to the processor from outside (dynamic). Arrival of the dynamic data files causes the corresponding data file in the storage to be addressed. In turn, the vector file can cause the execution of the operation indicated by its contents, by using the operands supplied using the incoming operand files. If all operands for the addressed data structure are present or have arrived, the operation specified by the program data structure is performed. The result is transferred to a destination or destination specified by the program data structure. The two associated data archives can be used in K2mbination to produce the result prescribed a v the program data archive.

Other objects and many accompanying advantages of this invention will be apparent from the following detailed description in connection with the drawings, where the same reference numbers denote corresponding parts in the different figures, and where: Fig. 1 is a block diagram for a data processing system according to this invention, based on a single processor or processing unit, Fig. 2 is a logic diagram for the input queue device in the processor of fig. 1, Fig. 3 is a logic diagram for a vector logic unit in the processor of fig. 1. Fig. 4 is a logic diagram for a control unit in the processor •on fig. 1.' Fig. 5 is a logic diagram for an output queue device in the processor of fig. 1. Fig. 6 is a logic circuit for a signal recognition circuit used in the input queue device of Fig. 2. Fig. 7 is an abstract illustration of a vocabulary year with four characters used in the processor of fig. 1. Fig. 8 is an abstract illustration of the general structure of a data archive used in the processor of fig. 1. Fig. 9 is an abstract illustration of a general data structure archive with sub-archives. Fig. 10 is an abstract illustration sotn in tree form representing a particular example of a program which may be executed by the calculator of Fig. 1. Fig. 11 is an abstract illustration of a simple algorithm represented in tree form and the data structure or archive that represents the algorithm used by the processor. fig. 1 to perform the specified operations. Fig. 12 is an abstract illustration of a particular example of cooperation between program and operand data structures in the various main parts of the processor in fig. 1, in order to achieve a desired result. Fig. 1 illustrates a computer-driven computer system with a processor or processing unit and which communicates with a plurality of peripheral units 15, 17, 19 through an input/output exchanger 13. The input/output exchanger 13 can be of a standard type with

switching circuits, e.g. such as are used in telephone exchanges, and in which any of the peripheral units can be connected to the data-driven processor 11 by means of an input cable 31 or output cable 33. The peripheral units can be based on parallel format or serial format. In order to adapt the character-serial mode of operation of the processor 11 when units based on parallel format are used, the input/output exchanger 13 comprises a multiplexer to convert the number of parallel signal paths coming from the peripheral units 15, 17, 19 into the relatively serial signal path input to the processor 11. To enable signal transmission according to the character-series principle from the processor 11 to the peripheral units 15-19 based on parallel format, the input/output exchanger 13 comprises a demultiplexer. The peripheral units 15,17, 19 can have. form of

any known devices, i.e. magnetic tape devices, card readers, card punch devices, keyboard devices, printers, drum or slide storage devices.

The data-driven digital calculator or data processor 11 receives data structures from the peripheral units at its input queue device 21. As will be explained below, these data structures have a special organization and must follow certain syntax rules. The input queue device 21 is fundamentally a buffer unit of the first-in/first-out type, hereinafter referred to as. FIFO unit, which performs the additional function of synchronizing the asynchronous data structures that are received on the input cable 31, according to the system code in the calculator 11. The data structures that are received by the input queue device 21 are received on tegrrse?\ie~

basis.

These data structures can be considered to be passed to the other elements of the calculator 11 on a character-series basis. Data structures, in the input queue device 21 are e.g. transferred to a computing machine storage 25 on a character-series basis over a cable<.>35, to a control unit 23 and from the control unit 23 over a cable 51 to the storage 25-The control communication between the input queue device 21 and the control unit 23 over a cable 37 and the control communication between the control unit 2.3 and the bearing. 25 over a cable 49 will be explained in the following.

Besides the fact that data structures from the input queue device 21 can be transferred to the storage 25, they can be transferred to a vector logic unit 27 using the control unit 23 via a cable 47. Similarly, data structures from the storage 25 can be transferred to the vector logic unit 27 using the control unit 23 over a cable 25. Control communication between the vector logic unit 27 and the control unit 23 through a cable 43 shall. explained later.

The vector logic unit 27 is. fundamentally, an arithmetic unit of the series type such as e.g. performs such.basic functions as addition, subtraction, comparison and send-to and data structures.with variable field length. The vector logic unit can communicate directly with the storage 25 over a data cable 53, and with an output queue device 29 over a data cable -59. Control communication between the vector logic unit 27 and the storage 25 over a control cable 55, and with the output queue device over a control cable 57 will be explained later.

The calculator memory 25 in the computer-driven calculator 11 can be a RAM memory based on integrated circuits and with a preferred size made using chips such as e.g. manufactured by Signetics Corporation. In the company's catalog for 1972 on page 4-24, a 32/2 RAM chip is indicated which can be used for the construction of the storage 25. Building a larger memory with such a memory chip does not present major problems for a person skilled in the art . Another example of a memory chip that can be used to build up the storage 25 is found in Signetics

catalog for 1972 on pages 4-13, illustrating a high-speed addressable memory chip.

The output queue device 29, which can receive data structures from the vector logic unit 27, the store. 25 or the input queue device 21, performs the function of setting the data structures it has received in a form that makes it possible to carry out transmission to the peripheral units 15-19 by means of the input/output switch a 13-Output queue device like the input queue device, is in reality a FIFO unit that accepts data structures of the character-series type and transfers these characters to the input/output switcher.

As can be seen from fig. 2, the input queuing device 21 communicates with the input/output exchanger over the cable 31-This cable is composed of lines 79, 81, 83 and 85 which come from a front or intermediate link logic 6l in the input queuing device 21. The lines 85 are two parallel data lines which receives two bits in parallel from the input/output exchanger (Fig. 1). These two parallel bits represent a character. The other three lines 79, 81 and 83 are control lines between the input queue device. and the output/input exchanger. Line 79 transmits a binary signal level instructing the exchanger to retransmit the data structure when an error is detected in the previously received data structure. Line 8l. carries a binary signal level that activates or deactivates the exchanger with respect to the transfer of data structure. Line 83 carries a signal level generated by the exchanger and arranged to indicate a request to send data structures from one of the peripheral units or the output queue device in the calculator 11. Under the influence of such a request, the signal level on line 8l will activate the exchanger if the input queue device can accommodate additional data.

The data structure of the character-series type received on the lines 85 from the exchanger 13 (Fig. 13), in addition to being passed to the interconnection logic 61, is checked for errors by means of logic circuits, which for the sake of simplicity are here denoted as data limiter recognition logic, and a binary up/down counter 65 which is actuated by the data limiter recognition circuit 63. The count in the counter 65 is transferred to the intermediate link logic 6l via a cable 93. It is sufficient at this point to mention that if the count if the binary up/down counter 65 at the end of a particular data structure is not equal to zero, the interconnect logic 61 requires a renewed transfer over the line 79 because

an error has occurred in the data structure. The specific logic function of the data limiter recognition circuit 63 and its interaction with the up/down counter and the interconnect logic 61 will be explained in more detail later.

As noted above, the input queue device 21 basically acts as a PIFO buffer unit and synchronizes the asynchronous incoming data characters with the calculator's system clock (not shown), which forms part of the interconnect logic 61. The buffer portion of the input queue device is the input queue memory 67, which may be a RAM memory made up of memory chips based on Signetics Corporation integrated circuits listed in the company's 1972 catalog on page 4-20.

The data characters that are received on lines 85 from the peripheral units are transferred to the input queue memory 67 via lines 96

and is stored in memory at the first available location,

as indicated by a write pointer circuit 73. Between the storage of data characters in the input queue memory, data characters are read out of this memory and transferred to other components of the calculator 11 (fig. 1) by means of the control unit 23 (fig. 1). The particular data character that is read out of the memory 67 at a certain time is determined by a read pointer circuit 71. The data character that is read out of the input queue memory is transferred from this through lines 98

to the intermediate connection logic 6l and then to the control unit 23 (fig.

1) above the lines' 35. Control lines 123, 121, which form control cabled

37, carries read-enable and read-request signals. from the control unit 23. The line 123 carries a read activation signal. The line

121 carries a read request signal. Generally speaking, information is thus stored in the input queue memory 67 as quickly as it is received and is read out from the input queue memory 67 in the order first-in/first-out as fast as the control unit 23 requires

this. When the interconnect logic 61 receives data characters over lines 85, it generates a signal on line 97 to a memory cycle controller 69 indicating that a write function is being requested. The memory cycle controller produces, under the influence of this write request, a write activation signal on line 103 to the input queue memory 67, a write selection signal on line 105 to a selector 75 and an increment signal on line 69 to a write pointer 73.

can

The selector 75/be of the type manufactured by Signetics Corporation and listed in the company's 1972 catalog on p. 2-136. Fundamentally, under the influence of a write or read select signal on line 105, the selector selects the write or read pointer output signal supplied to it on cable 109, respectively 111 for transfer over cable M07 to an address register for the input queue memory 67.

The typing wizard. 73 and the read pointer 71 may be a binary counter.from Signetics Corporation indicated in the company's 1972 catalog on pages 2-100.. Increment inputs 99 and 101 on

show the write pointer and the read pointer, from the memory cycle controller 69 is connected to an A input (not shown) of the mentioned counters.

The line 100 from the intermediate link logic 6l to both the reading indicator 71

and the write pointer 73 is connected to reset inputs (not shown) on these counters.

The output from both the writing display and the reading display will be bypassed

to pass through the selector to address the input queue memory 67, sampled by a comparator 77. The comparator may have. form of a comparator or comparator circuit, from Signetics Corporation listed in the company's 1971 TTL/MSI catalog on page 101. This comparator has two output wires that indicate which of the two inputs © is greater and when these are equal. Because the input queue device is of the FIFO type, will write, we see one's count is always greater than the read pointer's count when the input queue memory 67 contains data but is not full. Therefore, a signal on a line 119 from the comparator 77 will indicate to the interconnect logic 61 that the write pointer's count is higher than the read pointer's count. This indicates to the intermediate link logic that there is still data in the input queue memory.

When the write counter's count is equal to the read counter's count,

a signal is transmitted from the comparator above one. line 117 to the intermediate link logic 6l. This signal can mean that the input queue memory 67 is either completely empty or completely full, depending on whether the last memory request generated by the interconnect logic 61 was a read or write request. Interconnect logic 6l interprets the signal on line 117- as that. the input queue memory 67 is full if the last memory operation is a write operation. If the last memory operation was a read operation, the signal on line 117 is taken to indicate that the memory is empty. Interconnect logic 6l knows whether the last memory operation was a write or read operation because it transmitted either a write or a read request over the respective lines 97, 95 to the memory cycle controller 69. When interconnect logic 6l finds that input queue "memory 67 is empty, it generates a reset signal

on line 100 for submission to both the write and read wizard.

The special logic circuits in the memory cycle controller 69 and the interconnect logic 6l shall not be discussed here, because

realization of the functions assigned to these logic circuits is to be regarded as obvious to one. specialist in the field.

The. reference is now made to fig. 3. A series-vector logic unit 27, which can be used in the calculator of FIG. 1, is shown in the basic features to consist of two ROM memories 125 and 129. Both of these ROMs may be of a type manufactured by Signetics Corporation listed in the company's 1972 catalog on page 4-.1. Address registers 124 and 128 for the respective ROM memories 125 and 129 are standard address registers of the parallel-in/parallel-out type. The only constructional difference between the two ROM memories is in the microcode they contain. The ROM memory 125 contains the microcode required for generating the results of dyadic operations such as addition, subtraction or comparison. The ROM memory 129 contains the microcode necessary to generate the result of monadic operations such as complement, eliminate first bit or first bit to zero.

Data structures that arrive on a character-series basis from the storage 25 in the calculator 11 (Fig. 1) by means of the control unit. 23 over lines 45 to the vector logic unit 27, is by a demultiplexer 135 according to a control signal on a line 43a. from the control unit 23 directed to the dyadic ROM memory 125 over a line

139, or to the monadic ROM memory 129 over a line 142 depending on the type of data structure addressed by the data structure. the trip in the entrance queue facility 29. Shared will be explained in more detail later.

Likewise, a demultiplexer 137 receives character-series data over the lines 47. from the input queue device 21 by means of the control unit 23 and directs these either to the dyadic ROM memory 125 over a line 14l or to the monadic ROM memory 129 over a line 143. The output of the memory 125 or the memory 129 is directed to the storage 25 in the calculator or to the output queue device 29 depending on the destination address occupied in the program data structure. This destination address is delivered to demultiplexers 133 and 130 over lines 43d by means of the control unit 23 in the calculator 11 (fig.1).

The demultiplexers 135, 137, 130 and 133 used in this vector logic unit may be of the type manufactured by Signetics Corporation and listed in the company's 1972 catalog on pages 2-132.

If there is e.g. assuming that a dyadic operation were to be performed where an operand A is summed to an operand B, an OP code denoting the dyadic operation, namely addition, will be delivered to the address register 124 either from the storage 25 or from the input queue device 21, as shall be explained in more detail below. Together with this OP code, the two operands are also added on a character-series basis to the address register 124. As a result of this, the output on the cable 126 from the ROM memory 125 will be the sign-series results of the summation of the two operands. What actually happens is that, in addition to the operands, the OP code acts as addresses to the special areas in the ROM memory 125 which store the results of the summation of two special characters from the two operands being summed.

The output of the memory 125 will in this particular example also contain a signal on the line 43c indicating to the control unit 23 that a special character summation has been completed. Furthermore, in the case of addition meant signals are fed back to the input of memory 125 on lines 132 to modify the addition of the next character. In the event that monadic operations are performed in memory 129, return lines 131 may simply constitute a step counter input. to modify the contents, of the address register 128. in the monadic ROM memory, so that the next memory location is addressed.

Briefly, the control unit 23 introduces data structures from the storage 25 and the input queue device 21 to the vector logic unit 27 which affects these two data structures by producing a result plus control signals which are sent back to the storage 25 over lines 53 and 55 or to the output queue device 29 over lines 57 and 59.

Reference is now made to fig. 4, which illustrates the control unit 23 for the calculator 11, which unit is a microprogrammed unit consisting of a plurality of ROM memories and multiplexers. A field analysis ROM memory 146 receives data structures from the input queue device over lines 35 or from the store over lines 51b. The data structure from the input queue device 21 or the data structure from the warehouse. 25 addresses the field analysis ROM memory 146 through an address register 145, causing the memory 146 to be influenced to send control signals to one of several demultiplexers. 148, 150 and 152.

If. e.g. the data structure that enters line 35 from the input queue device is an operand archive, will. the field analyzer causes the demultiplexer 148 to transfer the operand fields over one of three lines 47a, 39a or 51a, of which line 47a leads to the vector logic unit, line 39a. leads to the access queue, and line 51a leads to the warehouse. In this case, the field analyzer will be affected by the description field in the operand archive. Likewise, if a data structure entering line 51b from storage is an operand file or field, the field analysis ROM 146 will direct the demultiplexer 152 over a line 162 to transfer data over line 49b or line 45b, of which line 39b leads to the output queue device, and line 45 leads to the vector logic unit.

It is now assumed that instead of receiving an operand data structure on one of lines 35 or 51b, a program data structure is received. This program data structure will address the field analysis ROM memory 146 and cause it to transfer an address to one of several ROMs - memories. 154, 156, 158. by means of the demultiplexer 150. The memories 154, 156 and 158 form a microprogram library containing special microprograms. These microprograms are addressed by the data structure that enters on one of the data lines 35 or 51b. It is assumed that the data structure that is received by. field analyzer ROM memory 146, begins with a field indicating that the following is a program archive, the field analyzer will generate a plural signals to the demultiplexer 150 which routes the signals, e.g. to the program archive memory 154. Under the influence of these signals which address special areas in this memory, control signals are generated which. is passed over the lines 43 to the vector logic unit (fig. 3), over the line. 4lb to the output queue device (Fig. 5), over the line 151 to the input queue device interconnect logic (Fig. 2), and when applicable, over the line. 144 to the address register 145, indicating that the particular operation is complete.

In addition to receiving data structures over lines 35 and 51b, the address register receives 145 different control signals. E.g. a read enable control signal from the interconnect logic is provided over line 123. for the entry queue facility. Above the line 43c, an operation completion signal is provided from the vector logic unit (Fig. 3). Above the line 4la, the output queue device delivers a holding signal which notifies the control that the device is full. A continue signal is also supplied to address register 145 from the ROM library over line 144.

The address register 145 is a standard register of the parallel-in/parallel-out type, which is well known to those skilled in the art. The field analysis ROM memory 146 may be of a type manufactured by Signetics Corporation indicated in the company's 1972 catalog on page 4-1. The microprogram library memories 154, 156 and 15.8 may be of the same type. Demultiplexers 148 and 152 may be of a type from Signetics Corporation indicated in the company's 1972 catalog on page 2-132. The demultiplexer 150 can consist of a plurality of demultiplexers in cascade where the individual demultiplexers are of one type. manufactured by Signetics Corporation listed in the company's 1972 catalog on pages 2-130.

In fig. 5, the output queue device 29 is shown in the form of a FIFO circuit with double memory. The input control circuit 145 receives data from either the input queue device or the storage over lines 39 by means of the control unit 23. The lines 41 carry the control signal from the control unit; 23. The input control circuit 145 also receives data from the vector logic unit 27 over the lines 59 and further sends and receives control from the vector logic unit 27 over the lines. 57" Data received by the input controller 145 over the lines 39 is recalled either to a RAM operand memory 155 or to a RAM destination address memory 157" depending on whether the received data structure is a destination address determined by the signals on the control line 4l from the control unit 23, or is an operand. determined by the signals on control line 41. Data received on lines 59 of the input control l45 is routed to the operand memory or to the destination address memory depending on the signals on control lines 57-Both the operand memory and the destination address memory can have. form of RAM memory chips manufactured by Signetics Corporation and listed in the company's 1972 catalog on pages 4-20. Both memories are addressed by a write pointer or a read pointer, with the operand memory 155 having a write pointer 147 and a read pointer 163, the destination address memory 157 having a write pointer 149 and a read pointer 160. The operation of these respective write and read pointers is identical to the operation they perform in the input queue device when the input queue memory 67 (Fig. 2) is addressed.

The input control circuit 1.45 acts similarly to the interconnect logic 61 in the input queue device in that it is influenced by signals from comparators 151 and 153 to stop the transfer of information to the input queue device 29 from the input queue device, the storage or the vector logic unit . The respective comparators 151 and 153 indicate for the input control circuit 1.45 the same way as the comparator 77 for the input queue device. fig.. 2 that the respective memories are either full, empty or contain some data.

The output control circuit 159. for. the output queue device 29 produces a read request either from the operand memory or the destination address memory 155j or 157 respectively under the influence of receiving a transfer instruction from the input/output exchanger 13 over a line 167 in the cable 33.' The output control 159 is also affected by a retransmission signal over the line..l65. Depending on signals on one of these lines, the output control circuit 159 may issue a write request signal on line 159 to the input/output switch. When receiving a transmission signal, e.g. over line 167, the data structure, a part of which is located in each of the memories, is transferred character-wise over lines 171 to the input/output exchanger 13. It should be remembered that this exchanger 13 in fig. 1 under the influence of received data structures over the lines 171 from the output queue device 29 will route or direct such data structures in accordance with the address field received from the destination address memory 151• ■ Thus the peripheral unit 1,. 2 or N (fig. 1) receive the data, or the data structure can be routed directly to the input queue for the calculator 11 for further processing.

On. fig. 6, the particular logic of the data limiter recognition circuit 63 (FIG. 2) is illustrated. The circuit 63 has two input conductors 175 and 173 which are each connected to the two input conductors in line 85. The signals on each of these conductors 173 and 175 are fed to the input of an Exclusive OR gate 177 and also to a AND gate 179 over line 173 and an AND gate l8l over a line 195. The output of Exclusive OR gate 177 on line 191 is fed as the second input to the respective AND gates. The output 89 of the AND gate 179 generates a plus one count signal, while

The AND gate 171 on the output line 91 generates a minus one count down signal to the up/down binary register 65. This counter 65 can. be off

a type manufactured by Signetics Corporation .shown. in; the company's catalog for 1972 on p. 2-170. The up/down counter 65 outputs a binary count over lines 197 to the interconnect logic 61 in the input queue device.

(jfig 2) and receives a clock signal. from the interconnect logic circuit 6l over a line 199 in the cable 93-

Fig. 7. illustrates them. preferred two-bit representations' of the four characters used through the calculator 11 (Fig. 1). The left data limiter 174 is represented by a. high signal on a first line and a low signal on another line, and both these signals are received in it. significant at the same time. A right data delimiter 146 is represented by a high signal on the first line and a low signal on the second line, i.e. directly opposite to the representation of the left data delimiter. A binary one character 178 is represented by two high signals. A binary 0 character 171 is represented by two low signals.

With reference to. fig. 6 again, the way of working by • recognition of whether the signals transmitted along the line 85 represent a right or left data delimiter character, or a binary 1 or a binary O character, will be described. Suppose it is e.g. that the binary signal on conductor 175 is a 1 or high, and the binary signal on line 173 is a 0 or low, the output of the Exclusive OR gate 177 will be a binary 1, and the signal on line 193 will be a binary 1, which causes the AND gate 179 to generate a high signal level on line 89. This signal level causes the counter 65 to be counted up by 1. If it is now assumed that the binary signal on line 175 is a 0. and the binary signal on line 173 is a 1, representing a right data delimiter character, the output of gate 177 will be a binary 1, causing the output of AND gate 181 on line 91 to go high. The high signal level on line 91 causes the counter 65 to count down by 1. The count of binary or a '. 65 is fed to the interconnect logic

6l in the entry queue device. When both input lines 173 and 175 to the data limiter recognizer 63 are high, it does not. produced no output on either line 69 or 91, because gate 177 does not generate an enable signal on line 191. The same situation exists when both lines 173 and 175: carry a binary 0.

As can be seen from fig. 8, is the field arrangement or the general, format of. a data archive which is the basic unit of a data structure, illustrated. The. The first field in an archive is a description field. The following fields are data fields. The last field is a termination field. The respective leftmost and rightmost data constraints 201 and 219 define an archive. Suppose that this archive, which can be considered a simple data structure, is transferred; from left to right, the start data delimiter is 201 and the end data delimiter. 219. The first field following the start data delimiter. 201, is a description.sf elt. 203 which itself is limited by two data limiters. The next field that follows the description field can be an operand field. e.g. as illustrated by. the field. 205, or an address field or an operator field.

The data in description.field 20.3 describes the type of and the sequence of the different fields that follow it. The spaces 207, 211, 215 between the data fields 205, 209 and 213 can, for the sake of simplicity, be termed "free space", which allows the data fields 205, 20.9 and 213 to expand if necessary. When these fields contract, they create more free space. All this free space can be used; to later allow these fields to expand. The exact way in which this happens will be explained in more detail later.

The last field in each archive is a termination field 217 which usually does not. will have some data captured in it. m.a.o. here are simply two characters, namely a left data delimiter and a right data delimiter. The termination field 217 and file-end-of-data delimiter 219 consist of three characters representing the termination code of the data structure or file. According to the one in fig. 7 specified convention is this code and is transmitted on a character series basis or two bits at a time in parallel from left to right.

This termination field and the end-of-archive data delimiter are interpreted as an end-of-archive code by the interconnect logic 6l in the input queue device. - When this code appears, the output of the counter will be 65 (fig. 2). be equal to 0 if none had occurred. error in the archive's data field. Fuck. would be the output count of the counter 65 for the general archive structure of fig. 8 behave as follows: 121212121210. Thus, a combination of a 0 count from counter 65 and the appearance of the termination code indicates that the received data structure had no errors. If it. e.g. was an error in a data delimiter character, the counter would not be stepped forward (incremented) or stepped back.. If there was an error in a data character, the -data delimiter counter would be stepped forward' or stepped back incorrectly. In either case, a count other than 0 would be returned at the time the exit code occurs. This would indicate an error, which would require the intermediate link logic to operate. fig. 2 is affected by requesting a new transfer as described above.

The structure of each archive is generally illustrated in fig. 8

and must follow certain syntax rules. These rules are as follows:

(1) No l character or 0 character can appear between equals each other, facing data limiters. E.g. there can be no characters between the start-archive-data delimiter 201 and the start-field data limiter for description.field 203. (2) The first field in an archive must be description.field 203..

<:>(3) The last field in the archive is always the closing field 207. In the example shown, this field has no data.

A data field, such as A-dataf.elte.t 205 on. fig. 8, can itself be composed of a plurality, fields or even a plurality of archives.. For example, shows, fig. 9. the field A as consisting of three sub-archives a, b and c. The Star.tf elt data limiter. 221 and the end-field data delimiter 223 define the data field A. But within these data delimiters, a majority of. what should be termed as. "vector files". The files a, b and c respectively indicated at 225, 229 and 233 illustrate vector files. These archives must of course follow the general syntax rules described for the general archive at fig. 8. That. that is to say that each archive includes a description.sf elt,. then take fields and a final field. As may occur within an archive, the spaces between the vector archives within a field, such as 227 and 231, may allow expansion of the vector archives within the field if desired.

This cohesive, or coordinated structure of. fields within the archive, and the vector archive within, the fields can be better understood if it is considered in the form of a tree structure with nodes representing programs, or operators. As an example, it should be assumed that the in it. the following defined operation must be performed on a plurality of symbols represented, by capital letters, in the alpha-bet: ■ {[ (A+B)-(C+D)] + t(F+G)-J]} -' .{(.[ (K-L) + (M-N)] + [0-Q])-R}-*X This arithmetic combination of 14 different symbols can be represented by the tree structure of; fig. lO.

The wooden structure on, fig. 10 receives as its "leaf" level inputs.t 225. the specified symbols or other operands. which must be processed by the program which. is described, by them. different nodes 227 etc. in the tree structure. Thus it will be. e.g. symbols A and B passed to the addition program operator in node 22.7, symbols C

and D. are passed to the adder operator in a node. 229. The result of these two operations is fed to a subtraction program operator in a node. 231. While this is happening, the symbols F and G may be fed to another adder operator in a node 235, and the result of this summation fed to a subtracter operator in a node 237 along with another symbol. J. At the same time as these previous operations occur, perhaps the symbols K and L are passed to a subtraction program operator in a node. 239,

and the symbols M and N are passed to another subtraction program operator in a node 241, while the symbols 0 and Q are passed to yet another subtraction program operator in a node. 247. The result of the operation in the knot. 239 and the result of the operation in node 24.1 is. led to an addition operator in a node. 243.

The result of the subtraction operator knot. 23I and the result of the subtraction operator knot one . 237. is taken to another addition operator node. 233. The result of the addition operator node 243 and the subtraction operator node 247: is passed to another addition operator node 245. The result of this is passed to a subtraction operator node. 249 which also. is supplied with another symbol R. The results from the minus operator node 24.9 and the addition operator node 233 are passed to another subtraction operator node 251. The result of this node is passed to a send-to-X operation 253.

It appears from this description of the tree structure that the processing of operands according to a tree-structured. flowchart facilitates the processing of operands in a parallel or simultaneous manner. That is, the operations that occur at the same level, such as-in nodes 227, 229, 235, 239,. 241 and 247, all can happen in it. significant at the same time if the associated operands are available. The same applies to all operations on others, e.g. the second level, such as in the knots. 231,. 237 and- 243, if the results of previous operations are all available at the same time.

In the example of fig.' 2. is it; for simplicity only considered dyadic operations, such as addition and subtraction. However, it will be clear that this type of tree-structured process flow chart will enable both monadic and dyadic operations with equal ease. The. it will be understood that in order to utilize the advantage of parallel processing, a system of data processing units or processors must be used.

To illustrate, how they coordinated archive data structures on. fig. 8 and 9 realize the three-structured processing method, the following simple dyadic operations on four symbols shall be considered: (A+B) (C+D).

These operations are illustrated in three-structured. shape in fig. 11. The symbols A, B, C and D on the "leaf" level 255, 257, 259 and. 26l is taken to it. first level of operator nodes, namely summation nodes 263 and. 265. The results from this node level. is carried to the next level or a subtraction node. 267. The result, from this node 269 can be sent to another node or a program operator or to a physical destination.

Each node in the tree structure of fig. 11 can be considered to constitute an archive. Therefore, considering these two levels of node operators, there is an archive that will describe the subtraction node 26.7, shown as a subtraction node archive 271. This archive is delimited by right and left data delimiters and has a; first field, which is a description field 277, which describes the nature of and the order in the archive. In this case, P represents program, which means that this archive is a program-operator archive. As this archive is an operator archive, . will the next, field as. following description. field, be a field 279 containing the operator code OP, In the present example, the operator code describes a subtraction operation. As the operation is dyadic, they will. fields that follow the operator field describe the two operands to be subtracted. These two operands are the results, from the addition nodes. 263 and. 265.

Because the operands are results of other operations, the operand fields are vector files. Therefore, the operands are described by vector files 273 and 275. That; field following the operand fields is a destination address field ,287, which indicates the destination to which the result of the subtraction operation must be sent. The last field in the .subtraction archive is the closing field 289. Free space can appear anywhere between the fields in an archive. E.g. is there free space shown in the subtraction program archive, at 28l? 283 and 285- It is recalled that as the operand fields are in the subtraction program archive. is. vector archives, free space can also appear between the fields within these archives.

Then the two are considered. vector archives in the subtraction program archive, the addition vector archive 273 and the addition vector archive 275. These archives are again structured according to the syntax rules described above. Left and right archive-delimiting data delimiters are used. Within these data limiters, the first field is a description field, which in this case describes the archive as a vector archive. whereby the following field is then reserved for the operator code. In this example, an addition operation is described. The. fields that follow the OP field,. will be the operand fields as in that. the present example is symbols. In addition to operand fields, they contain dyadic vector archives, such as the archives. 273 and. 275 in a larger archive, such as the program archive 271, result fields denoted by R in fig. 11. These result fields store the result. of the dyadic operation described by the relevant vector archive if this result cannot be used at the time when it. appears.

To facilitate understanding, the general operation of the calculator 11 shall be on. fig. 1 is described in relation to the simple program flow diagram illustrated in; fig. 11, which only uses dyadic operators. To further facilitate the explanation and understanding, it shall be assumed that the program data structures. or program archives that are used are dynamic and are received by the input device 21 ;'C|fig. 1). It is clear, however, that the opposite is equally applicable, and that. the operand archives may be stored in the calculator storage. 25, and the program archives can be supplied to the calculator 11 through the input queue device. 21.

To perform, the functions of; fig. 11, the storage in the calculator will contain a program archive as illustrated in fig. 12B under the heading, "stock". The original contents of this store before the calculator receives any operand files is illustrated in position "1". The. first field 291 in this archive is a description field that identifies the archive as a program archive. The first field 301 that follows this description field is

a field that describes the operation to be performed. In that. In the present example, this is a subtraction operation. The next field following operator fields 301 is an operand field, delimited by a left data delimiter 305 and a right data delimiter 327. This operand field is a. vector file representing a dyadic operation. After this operand field comes another operand field which is also a vector file. The field that stands immediately before the end field is a destination address.ef.elt 343. It should be remembered that there may be spaces between the different fields in the subtraction program archive, so that free spaces 303, 329 etc. enables expansion

of the operand fields.

That's how it should be. first operand field, which is a. vector archive, considered. In this particular case, an addition operation is defined. Operand fields' 309 and 313 in this particular archive follow - because a dyadic operation is. defined - by the field that describes the operator. Also, this vector archive contains a result field .321 instead, .for. a destination address.efield. The operand fields.309, 313 and the result field 321 are all located

in a contracted state leaving a significant amount of free space 307, 311, 315 and .323. between themselves. In other words, the fields are simply defined by a left data delimiter followed by a right data delimiter. without any signs occurring between them. These operand fields remain compressed until operands are stored in them, as will be explained in more detail in the following.

The second operand field, for the subtraction program archive is also one. vector file structured in the same way as described, first, operand field. Oet. there are two operand fields 333 and

'335, one result field 337 and an end field 34l. When these fields are empty, they are in a contracted state leaving a considerable amount of free space 331, 339 etc. between them'.

Above is described the intended structure of a program archive in the calculator storage which remains static until an operand data structure or an archive arrives in the input queue device and addresses this particular program archive. The structure of this program archive provides a recursive mechanism that increases the speed of algorithm execution.

An alternative data structure for execution of. the function in fig. 11.would be a structure that uses three program archives instead of one program archive, containing, two. vector archives as illustrated.. Thus, two addition vector archives and the subtraction program archive represent three independent program archives. The 'Resultant field in each, vector archive v would be replaced by a destination address.e.f elt. The destination address field in both addition program archives would address the subtraction program archive. in a manner to be described below. Application of this type of data structure requires that the result of each operation be routed out of the calculator

.and back to the entrance of this one, to get to the next opera torknode. In contrast, the illustrated program eliminates

archive structure the need to send the result of a vector archive operation out of the calculator or processor and back to its input for further processing.

To continue with the illustrated data structure, the data archives that arrive at the input queue device are now considered. It is assumed that the first operand arriving in a data archive is operand A. The archive containing this operand is illustrated on. fig. 12a as an archive structure 1 under the designation, "input queue". The first field in this data archive is a description field 375 which indicates that this particular archive is an operand archive containing a symbol. This description.sf elt. is analyzed by the field analyzer 146 (Fig. 4) in the controller 23, which under the influence of this sets up associated paths to the warehouse 25. for the next field 377 which is a warehouse address field. for addressing of. the special vector archive to which symbol A belongs. The warehouse address. 377 will address the storage location in the store starting with the left data delimiter 305 in the addition vector archive in the subtraction program archive 301. The next field following the address field 377,

is an operand storage space field 379 that indicates whether the operand field 383 that follows afterwards belongs to it, respectively. left or right operand field 309 or 313 in the special vector archive. The operand archive that is received at the input queue device also has a termination field 387 which can have free space 381, 385 between the fields in the archive.

The controller 23 can, by means of its field analysis ROM memory 146 and its sub-routine library consisting of routines 154, 155 and 158, call the addition vector archive once it has been addressed by the operand archive at the input queue device to determine if the •B operand has previously arrived and been stored in its. field 313. As this is not the case in the present example, as indicated for the control according to the empty operand fields 309, 313, the control stores the operand A in the respective field 309. When the operand A is written into the memory, character by character, the operand archive 309 is expanded to accommodate its exact size. The details regarding the practical writing of the operand into the memory are obvious to a person skilled in the art and shall not be discussed here.

As a result of the symbol archive illustrated in position 1 arriving at the input queue, the subtraction program archive in the calculator storage will therefore have the symbol A stored in the relevant operand field 3^7 in the vector archive which was addressed and begins with the left data delimiter 345, as shown at position 2 under the indication "stock" in fig. 12B. Then the symbol A now. is stored in its correct operand field, this field has been expanded, and the free space 349 between, this operand field and its accompanying operand field may be completely used up or greatly reduced.

It is now assumed that the next operand archive that enters the input queue device 21 in the calculator 11 contains an operand D in its operand field 382. as shown in position. 2 under the entry "input queue". In addition to the description field that tells the control unit which fields are to follow, a storage address field 376 and an operand storage ted field 389 are present in this operand archive. The symbol archive at position 2 in the input queue has a storage address field 376 which addresses the addition vector archive in the subtraction program archive at the start data delimiter' 346 (position 2 under the indication, "storage"). When it be'vector archive. is addressed, the control unit will, after seeing the operator field, in the vector archive, i.e. cause the relevant addition microprogram in the microprogram library formed by memory 154, 156 and 158 (fig. 4), to be activated. If this microprogram detects that all the operands necessary to perform the operation are not present in either the input queue or the storage, another microprogram is activated to store the symbol D in an operand field 382

in the input queue archive in the relevant operand field 351 in the addition vector archive , as determined by. the operand storage location code in a. field 389

in the symbol archive at the entrance queue. As a result of the processing of the second symbol archive, the data structure in the warehouse will appear as illustrated by position. 3. under the indication, "stock". The. that is, a symbol A is stored in its correct operand field, and the first addition vector archive and a symbol D is stored in its correct operand field in the second addition vector archive.

The. it is now assumed that the third operand file entering the input queue, . carries a B operand in the operand field. 384. which is to be combined with the A operand. Due to the description field L, the control will detect that .det.te is a symbol archive, and therefore the following field 378 is a storage address that addresses the first vector archive containing the A operand. The control proceeds by reading this addressed vector file, and its field analysis memory 146 (Fig. 4) determines. from the description field. "V" that this is a vector archive containing a program. The; field that must follow this description field is then an operator code field. Under the influence of the operator field, the field analyzer activates the appropriate microprogram from the microprogram library memory 154, 156 or 158 and also causes the triggering of the symbol A from the storage to address, the relevant memory 125 in the vector logic unit (Fig. 3), while simultaneously reading the symbol B. from the entry queue facility. to address the same memory 125

in the vector logic unit.

It should be remembered that the vector logic unit is a serial arithmetic unit that operates on two characters simultaneously, one character of which comes from each of the two operand fields. When the vector logic unit has completed its function of adding operand A with operand B, the microprogram determines whether the result field in the second vector file is full. As it is empty in this case, it will store the result of the addition of the symbols A and B in the relevant result field in the first vector archive. As a result of the third operand archive appearing in the input queue, the subtraction program archive in the store will be structured as shown in position 4 under the indication "store", i.e. that the operand fields which are occupied by the symbols A and B, namely fields 355 and 359 are now empty as they were contracted as read, and the resultant field 359 containing the result of the summation of A and B is full. The symbol D, which is an operand in the second vector file, is also present.

The only missing operand at this point is the symbol C. It is now assumed that an operand archive containing the operand C in field 386 arrives. address the other vector file. The control will then read this, vector file, set the vector logic unit to perform the operation required by the operator code field in this and perform summation of C and D in the same way as described, for the operands A and B. After completion of this operation, however, because the result field 369 in the -first addition program sub-archive is full, besides storing the result of the summation of the symbols C and D in the result field 367, another microprogram is selected as. prev sets or enables the vector logic unit according to the subtraction operator code field in the subtraction program archive. This microprogram causes the control unit, on a character series basis, to supply the vector logic unit with the result of the summation of A plus B, from the resultant field a 369 in the warehouse, as a result of which C plus D is supplied to this, in order to have the two resultants subtracted from each other.

While this operation is being performed, the destination field becomes 343

in the subtraction program archive taken to the destination address memory. 157 in the exit queue facility. 29 (fig. 5). This destination address field' 375 is, as shown in fig. 12B under the indication 'output queue' in position 1, a destination vector archive which has as its: first, field a description field 380 which, in the present example, identifies the archive as a symbol or operand archive, followed by an address field. 383 and an operand storage location field 375 that follows the address field. The operand field, such as field 387, can follow operand-lagerst.ed-f elt et. Since the syntax of an archive structure must be followed, the destination address archive must be terminated with a termination field 391. As the destination address field is a vector archive, it may also have free space between the fields, such as e.g. the free space 389. At this point, nothing is stored in the operand field 387, and this has a contracted form. When the vector logic unit obtains the result of the subtraction of the symbols C plus D from the symbols A plus B, this result, as shown at position 1 under the indication "operand memory" in fig. 12B, sent to the operand memory 155 in the output queue device (Fig. 5).

The output control 159. for the output queue device 29 transmits a message in a. form which is essentially identical to the form received at the entry queue facility. as shown in fig. 12B under the indication "message transmitted". Since the result in this example is a symbol, the transferred archive is an operand archive bounded by a right data delimiter 377 and a left data delimiter 379. The first field is a description field 38l which defines the archive as an operand archive. The second field is an address field 383. As shown in fig. 12B, this address field may be a single field containing a peripheral device identifier 384 or, in the case of a multiprocessor system, may contain composite fields, such as a field 386, indicating a processor unit and a storage-address.field 388 indicating a particular area in the storage of the addressed processor. The field that follows the address field is an operand storage field 385 if this is necessary. The. field following the operand-store-field- is the result field 393. The leaving operand archive, the output queue, ends with a terminating field 391 and a right data delimiter 379.

Briefly summarized, the functional description given above makes it clear that the calculator in fig. 1 performs an operation only after concatenating two data structures, one of which is a program structure and the other of which is an operand structure. With reference to the specific example, the program structure in the form of the program archive is stored in the calculator's storage awaiting the arrival of the operand structures or operand archives that address the respective program archives, which causes the control unit in the calculator to perform the indicated program. This data-driven mode of operation therefore provides a digital data processor which has superior emulation properties and can be used as a basic component or building block in a calculator of the multiprocessor type, - where each of the building blocks has its own. functions defined by the program archives stored in their respective storage areas. Since the arrival of operand archives at the input of a special computer processor causes activation of the addressed program when such a calculator is used as a building block in a multiprocessor type calculator, there will be no need for a main control program or an extensive interrupt system for regulating the cooperation between the processors in the multiprocessor calculator. As can be seen, it is clear from the description given above that the calculator on, fig. 1 hair improved emulation properties. because the four-character vocabulary of a string-type calculator facilitates the use of variable-field-length data structures. These data structures can be easily checked for errors by using simple logic circuits in the paths through which data flows.

Claims (1)

1. Binary data processing system, characterized in that it comprises an input circuit (21), a storage (25), a logic circuit (27), an output circuit (29) and a control device (23) connected to these for communication between them, which storage (25) comprises data archives composed of data fields containing data characters, and which input circuit (21) is arranged to receive data archives composed of data fields with data characters, where one of the data fields contains a storage address for a data archive in the data storage (25). 2. System according to claim 1, characterized in that the data store contains binary information located between the data archives and the data fields to indicate the start and end of the data archives and the data fields. j5. System according to claim 1, characterized in that the data store contains data archives that represent program data, and that the input circuit receives data archives that represent operand data. 4. System according to claim 3, characterized in that the said fields which form a program archive are separated from each other in the program archive by means of free space in which the said fields can expand. 5. System according to claim 5~, characterized in that the program data archive located in the data store contains one or more program archives assigned to a specific program field and a destination address field. 6. System according to claim 1, characterized by the output circuit for receiving a destination address field and operand fields and for combining these to form an output message data archive. 7. System according to claim 1, characterized in that the archives in the storage (25) are structured in a hierarchically coherent order, and that the data archives in the input circuit (21) are structured in a hierarchically coherent order. 8. System according to claim 7* characterized in that the data store contains binary information placed between the data archives to indicate the start and end of the data archive. 9. System according to claim 7, characterized by the output circuit for receiving a destination address field and at least one operand field and combining these to form an output message data archive. 10. System according to claim 7, characterized in that the data store contains data archives representing program data and the input circuit receives data archives representing operand data. 11. System according to claim 10, characterized in that the said fields which form a program archive are separated from each other in i^ograirø^lvelr] by means of free space in which the said fields can expand. 12. System according to claim 10, characterized in that the program data archive located in the data store contains one or more program archives assigned to a special program field and a destination address field. 13- System according to claim 10, characterized in that the fields that form an operand archive are separated from each other in the operand archive by means of free space in which said field can expand. 14. System according to claim 7, characterized in that the data archives that are received by the input circuit comprise an operand field, an operand identification field and a storage address field. 15. System according to claim 1, characterized in that data communication over serial data communication channels (31, 35, 39* ^7, 4-5, 51, 53, 59, 33) takes place on a character-series basis, where a character has a length on two binary bits. 16. System according to claim 15, characterized in that the data store contains binary data placed between the data archives to indicate the start and end of the data archives. 17. System according to claim 16, characterized in that four characters are used to represent all data, where two high signals represent a binary 1 character, where. two lower themselves nals represent a binary 0 character, and a combination of a high fpg a low signal represents either a start data or an end data character. 18. System according to claim 3/57^characterized by the output circuit for receiving a destination address field and an operand field and for combining these to form an output message archive. 19. System according to claim 15, characterized in that the data store contains data archives that represent program data and the input circuit receives data archives that represent operand data. 20. System according to claim 19, characterized in that the program data located in the data store contains operand fields assigned to a program field for forming a program archive, which operand fields are empty and contracted until they are expanded by having the respective operand entered. 21. System according to claim 20, characterized in that the aforementioned fields which form a program archive are separated from each other in the program archive by means of free space in which the archive's fields can expand. 22. System according to claim 19, characterized in that the program data archives located in the data store contain one or more vector archives assigned to a special program field and a destination address field. 23. System according to claim 15, characterized in that the data archives which are received by the input circuit comprise operand fields, an operand identification field and a storage address field which forms an operand archive. 24. System according to claim 2, characterized in that the fields that form an operand archive are separated from each other in the operand archive by means of free space in which the archive's fields can overlap. 25. System according to claim 1, characterized in that the data archives in the storage 25 are composed of data fields containing data characters, which data fields and data archives are separated by means of data start and data end characters, each of which data fields is stored and organized in a data archive according to the following format: ((A) (B) (C) (D) (E)) where the left data delimiters are data start telgn, the . right data delimiters are end-of-data characters, A is a description field that identifies the types of fields that follow, while B, C and D are data fields that can contain operands or operators, and E is an end field, and that the data archives in the input circuit (21) is composed of data fields containing data, which data fields and data archives are delimited by data start and data end characters, which data fields are organized in a data archive with the following format: ((A) (B) (C) ... (D) (E)) where the left data delimiters are data start characters,* the right delimiters are data end characters, A is a description field that identifies the types of fields that follow, while B, C and D are data fields that can contain operands or operators, and E is an end field, and that one of the aforementioned data fields B, CJ~j or D contains a storage address for a data archive in the data storage (25). 26. System according to claim "25, characterized in that the description fields and the data fields are themselves formed from data structured in the aforementioned archive format. 27. System according to claim 25, characterized in that the aforementioned data archives follow the syntax rules below: 1. no binary information between data limiters that face each other 2. the first field in an archive is always the description field 3" the last field in an archive is always the closing field. 28. System according to claim 25, characterized in that the data fields in the data archives are separated from each other by means of free space that can be used to expand the said data fields. 29. System according to claim 25, characterized in that four characters are used to represent all data, where two high signals represent a binary 1 character, two low signals represent a binary O character, and a combination of a high and a low signal represents either a start-of-data or an end-of-data character. 30. System according to claim 29, characterized in that the said description fields and the said data fields can themselves be formed from data that is structured in the said archiyf orrnajt^ | 31. System according to claim 29, characterized in that the data fields in the data archives are separated from each other by means of free space, represented by a plurality of binary characters, which free space is utilized to expand the data fields. 32. System according to claim 25, characterized by the output circuit for receiving a destination address field and an operand field and for combining these to form an output message. 33. System according to claim 32, characterized in that the operand field and the destination address field which are received by the output circuit comprise data structured in the aforementioned archive format. 34. System according to claim 25, characterized in that the description field in the data archives in the data store contains program-identifying data, and that the description field in the data archives in the input circuit contains operand-identifying data. 35. System according to claim 34, characterized in that the description fields and the data fields themselves can be formed from data structured in the aforementioned archive format. 36. System according to claim 34, characterized in that the aforementioned data archives follow the syntax rules below: 1. no binary information between the same data limiters facing each other 2. the first field in an archive is always the description field 3. the last field in an archive is always the termination field. 37. System according to claim 34, characterized in that the data fields in the data archives are separated from each other by means of free space that can be used to expand the data fields. 38. System according to claim 34, characterized in that four characters are used to represent all data, where two high signals represent a binary 1 character, two low signals represent a binary O character, and a combination of a high and a low signal represents either a start-of-data or an end-of-data character. 39- System according to claim 34, characterized in that one of the operand fields in the data archive in the data store is intended for storing a destination address, which operand fields are contracted if they are empty, until they are expanded by the operands in question being entered . 40. System according to claim 1, characterized in that there are arranged data communication channels (31, 35, 39, ^7, ^5. 51, 53*59, 33) which comprise: a device (85) for the transmission of two discrete signal levels in the essentially at the same time, and a device (63) at the receiving end of certain of the aforementioned data communication channels for sensing \o§ interpretation of the two discrete signal levels] that are received, so that two high levels represent a binary 1 character, two low levels" ]represents a binary o character, and a high level and a low level represent a start-of-data character or an end-of-data character. 41. System according to claim 40, characterized in that the transmission device which is connected between the said circuits comprises two conductive paths for electrical signals, and that the device for sensing and interpreting the two discrete signal levels interprets a high level and a low level as a data start- character if the high level occurs on a first signal or conduction path and the low level occurs on a second conduction path, and interprets a high level and a low level as an end-of-data character if the high level occurs on the second conduction path and the low level occurs on the first lead path. 42. System according to claim 41, characterized by an arrangement for counting up by one unit depending on the sensing and interpretation device detecting a data start character, and counting down by one unit depending on the sensing and interpreting device detecting a data end character. 4J. System according to claim 40, characterized by a device for counting up by one unit depending on the sensing and interpreting device detecting a data start character and counting down by one unit depending on the sensing and interpreting device detecting a data end character. 44. System according to claim 1, characterized by the device (65) for checking the occurrence of errors in data by reading certain characters which are transmitted over the said serial data communication channels. 45. System according to claim 44, characterized in that four characters are used to represent all data, where two high signal levels represent a binary 1 character, two low signal levels represent a binary Cp character, and a combination of a high signal and a low signal represents either a start-of-data or an end-of-data character. 46. System according to claim 45, characterized in that the device for checking the occurrence of errors senses and counts the data start and data end characters. 47" System according to claim 46, characterized in that the device for checking the occurrence of an error indicates the occurrence of an error when an end data structure code is detected and the count of data start and data end characters is not equal to 0. 48. System according to claim 44, characterized in that the device for checking the occurrence of errors comprises a device for sensing said characters, which device is a first and a second data input line, where a high signal level on the first and second data input lines is interpreted as a binary 1 character, a low signal level on the first and second data input lines is interpreted as a binary 0 character, a high signal level on the first input line and a low signal level on the second data input line is interpreted as a data start character, while a low signal level on the first data input line and a high signal level on the other input line is interpreted as a data end character, and a device for counting up by one when the sensing device detects a data start character and counting down by one when the sensing device detects a data end character. 49. System according to claim 1, characterized by a recursive mechanism comprising: data structures stored in the warehouse and designed to represent program data organized in a hierarchically coherent order according to program data archives composed of operand fields and a result field assigned to a special program description field, and data structures received by the aforementioned input circuits and arranged to represent operand data organized in a hierarchically coherent order, which data structures bb<y>irk the addressing of certain of the data structures in the store. 50. System according to claim 49, characterized in that a fp^ogram data archive has at least one operand field and a destination address field assigned to a program description field, which operand field is a vector archive composed of at least one operand field, a resultant field and a vector description field. 51. System according to claim 50, characterized in that the operand fields and the resultant fields in the vector archive are contracted when they are empty, until they are expanded by having data entered. 52. System according to claim T49, characterized in that the operant fields and the resultant fields are contracted when they are empty, until they are expanded by having data entered. 53. System according to claim 1, characterized by the wood recursive mechanism, comprehensive data structures stored in the aforementioned storage, which data structures represent program data organized in a hierarchically cohesive order according to program data archives with the following format: ((P) (0P)xxx((V) (OP)xx(A)xx( B)xx(R)( ))xx(C)xx(DA)()) where all bounded areas within data delimiters are fields, P represents a program description field, OP represents an operator field, while A, B and C represent operand fields, V represents a vector description field, R represents a resultant field, and DA represents a destination address field. 54[T\ System according to claim 53, characterized in that the operant field and the resultant field are contracted when they are empty, until they are expanded when data is entered. 55. System according to claim 1, characterized by the recursive mechanism comprising data structures stored in the aforementioned warehouse and arranged, to represent program data organized in a hierarchically coherent order according to a program data archive with the following format: ((P)(0P)xxx((V)(0P)xx(A)xx()xx(R)( ))xx(C)xx(DA)()) where"all bounded areas within data delimiters are fields, P represents ^st program description field, OP represents an operator field, A and C represent operand fields, V represents a vector description field , R represents a result field, and DA represents a destination address field, and data structures received by the input circuit represent operand data organized in a hierarchically coherent order according to the operand archive composed of at least one operand field and a storage address field assigned to a distinct op~jerand description field. 56. System according to claim 55, characterized in that the operand fields and the resultant field in the storage are contracted nH* they are empty, until they are expanded when data is written. 57« Data-driven information processing system comprising a storage unit containing one or more control operators stored therein, and a programmable unit comprising a logic unit for performing operations on data segments, an input device connected to the logic unit for receiving data segments for transfer to the logic unit, and a control unit connected to the input device and the logic unit and the storage unit to provide entry or access to the storage unit for a control operator in response to the receipt of a data segment by the input device and to signal the logic unit to perform an operation on the data segment. 58. System according to claim 57, characterized in that it comprises a source for data segments for delivering data segments to the programmable unit for operation. 59- System according to claim 57, characterized in that a programmable unit is connected to another programmable unit to receive a data segment from this and to perform an operation on this after the other programmable unit has performed an operation on the data segment. 60. System according to claim 57, characterized in that it comprises a connection device for serial data transfer to and from the aforementioned units. 61. System according to claim 57, characterized by. a peripheral data source, and that the programmable device is connected to the peripheral data source to control data transfer between them. 62. System according to claim 5, characterized in that said control unit for the programmable unit comprises a memory in which control signals are stored. 63. System according to claim 1, characterized in that the input circuit comprises a buffer device (67, 75, 69) of the first-in/first-out type to receive the aforementioned data archives. 64. Data-driven information processing system comprising a programmable unit with a logic unit, a storage unit connected to the programmable unit to record one or more control operators stored therein, comprising the following steps: that a data segment is received in the programmable unit, that the access is provided to the storage unit connected to said programmable unit under the influence of said received data segment to retrieve a control operator from the storage unit, and that the logic unit [in] the programmable unit is signaled to perform an operation on the received data segment . 65. System and procedure as described. 66. Numerical calculator with input circuits, output circuits, arithmetic circuits, data stores and control circuits, communication paths between the said circuits and between these circuits and other devices, comprising: a device connected between the said circuits and between disc] circuits and other devices for transmitting two discrete signal levels essentially simultaneously, and a device at the receiving end of the said communication paths for sensing and interpreting the two discrete signal levels that are received, so that two high levels represent a binary 1 character, two low levels represent a binary O character, and a high level and a low level represent a start-of-data character or an end-of-data character. 67. Machine according to claim 1, characterized in that the transmission device which is connected between the said circuits comprises two conducting paths for electrical signals, and that the device for sensing and interpreting the two discrete signal levels interpret a high level and a low level as a data start character if the high level occurs on a first conduction path and the low level occurs on a second conduction path, and interpret a high level and a low level as a data end character if the high level occurs on the second conduction path and the low level occurs on the first conduction path. 68. Machine according to claim 67, characterized by the device for counting up with/unit under the influence of the sensing and interpreting device detecting a data start character, and counting down with a unit under the influence of the sensing and interpreting device detecting a data end character. 69. Machine according to claim 66, characterized by the device for counting up with one unit under the influence of the sensing and interpreting device detecting a data start character, and counting down with one unit under the influence of the sensing and interpreting device detecting a data end character. 70. Binary data processing system, characterized in that data communication between different parts of system eftT takes place on a character-series basis, where a character has a length of a plurality of binary bits, which system comprises: a data input device, a storage device for receiving data from data - the input device, a vector logic device for receiving data from the data input device and the storage device, cf. a data output device for receiving data from the SATA input device, the storage device and the vector logic device, and a device for checking the occurrence of errors in data by counting only certain of the characters. 71. System according to claim 70, characterized in that four characters are used to represent all data, where two high signal levels represent a binary 1 character, two low signal levels represent a binary 0 character, and a combination of a high signal and a low signal represents either a start-of-data or an end-of-data character. 72. System according to claim 71, characterized in that the device for checking the occurrence of errors senses and counts the data start and data end characters. 73. System according to claim 72, characterized in that the device for checking the occurrence of errors indicates the occurrence of an error when an end data structure code is detected and the count of data start and data end characters is not equal to 0. 74. System according to claim 70, characterized in that the device for checking the occurrence of errors comprises: a device for sensing the mentioned characters, which device has a first and a second data input line, where a high signal level' on the first and second data input line is interpreted as a binary 1 character, a low signal level on the first and second data input lines is interpreted as a binary O character, a high signal level on the first data input line and a low signal level on the second data input line is interpreted as a data start character, while a low signal level on the first data input line and a high signal level on the second data input line is interpreted as a data end character, and a device for counting by one when the sensing device detects a data start character and to count down by one when the sensing device detects an end-of-data character. 75* Binary data communication link comprising: a device connected to the sending side or end of the communication link for transmitting two discrete signal levels substantially simultaneously, and a device at the receiving end of the communication link for sensing and interpreting the two discrete signal levels that are received, so that two high levels represent a binary 1 character, two low levels represent a binary Up character, while a high level and a low level represent a data start or data end character. 76. Communication connection according to claim 75, characterized in that it comprises: two conducting paths for electrical signals connected between the sending and receiving ends of the connections, and where the device for sensing and interpreting the two discrete signal levels interprets a high level and a low level as a data start- character if the high level occurs on a first conduction path and the low level occurs on another conduction path and interprets a high level and a low level as an end-of-data character if the high level occurs on the second conduction path and the low level occurs on the first guide way. 77. Communication connection according to claim 76, characterized by the device for counting up with one unit under the influence of the sensing and interpreting device detecting a data start character, and counting down with one unit under the influence of the sensing and interpreting device detecting a data end character. 78. Communication connection according to claim 77, characterized by a device for checking the occurrence of errors in data, by counting only certain of the characters. 79• Communication connection according to claim 78, characterized in that the device for checking the occurrence of errors senses and counts the data start and data end characters. 80. Communication connection according to claim 79, characterized in that the device for checking the occurrence of errors indicates the occurrence of an error when an end data structure code is detected and the count of data start and data end characters is not equal to 0. 81. Communication connection according to claim 75, characterized by the device for counting up with one unit under the influence of the sensing and interpreting device detecting a data start character, and counting down with one unit under the influence of the sensing and interpreting device detecting a data end character. 82. Communication connection according to claim 8l, characterized by a device for checking the occurrence of errors in data by counting only certain of the characters. 83. Communication connection according to claim 82, characterized in that the device for checking the occurrence of errors senses and counts the data start and data end characters. 84. Communication connection according to claim 83, characterized in that the device for checking the occurrence of errors indicates the occurrence of an error when an end data structure code is detected and the count of data start and data end characters is not equal to 0. 8^5j, Binary data processing system, characterized in that data communication within and with the system takes place on a character-series basis, where a character has a length of a plurality of binary bits, which system includes: a data warehouse containing data archives composed of data fields with data characters, which data fields and data archives are delimited using data start and data end characters, each of which data fields is stored in this and organized in a data archive with the following format: ((A) (B) (C) . ... (D) (E) where the left data constraints are data start characters, the right data constraints are data end characters, A is a description field that identifies the types of fields that follow, while B, C*, D are data fields that can contain operands or operators, and E is an end field, and an input circuit for receiving data archives composed of data fields with data, which data fields and data archives are delimited by data start and data end characters, which data fields are organized in a data - archive with foal following format: (A)(B) (C) ... (D) (E) where the left data constraints are data start characters, the right data constraints are data end characters, A is a description field that identifies the types of fields that follows, while B, C, and D are data fields that can contain operands or operators, and E is an end field, as well as one of the data fields B, C, or D containing a storage address for a data archive in the ^data storage. 86. System according to claim 85, characterized in that the description fields and the data fields themselves are formed from data structured in the aforementioned archive format. 87. System according to claim 85, characterized in that the data archives follow the syntax rules below: 1. no binary information between data constraints that face each other 2. the first field in an archive is always a description field 3. (The last field in an archive is always the end field . 88. System according to claim 85, characterized in that the data fields in the data archives are separated from each other by means of free space that can be used to expand the data fields. 89. System according to claim 85, characterized in that four characters are used to represent all data, where two high signals represent a binary 1 character, two low signals represent a binary 0 character, and a combination of a high and a low signal represents either a start-of-data or an end-of-data character. 90. System According to claim 89, characterized in that the description fields and the data fields themselves can be formed from data structured in the aforementioned archive format. 91. System according to claim 89, characterized in that the data fields in the data archive are separated from each other by means of free space represented by a plurality of binary characters, which free space is utilized to expand the data fields. 92. System according to claim 85, characterized by the output circuit for receiving a specific destination address field and an operand field as well as combining these to form an output message. 93" System according to claim 92, characterized in that the operand field and the destination address field that are received of the output circuit, includes data structured in the aforementioned archive format. 94. System according to claim 85, characterized in that the description field in the data archives in the data store contains program-identifying data, and that the description field in the data archives in the said input circuit contains operand-identifying data. 95*System according to claim 94, characterized in that the description fields and the data fields themselves can be formed from data structured in the aforementioned archive format. 96. System according to claim 94, characterized in that the data archives follow the syntax rules below: 1. no binary information between the same data constraints facing each other 2. the first field in an archive is always the description field 3. the last field in an archive is always the closing field . 97" System according to claim 94, characterized in that the data fields in the data archives are separated from each other by means of free space that can be used to expand the data fields. 98. System according to claim 94, characterized in that four characters are used to represent all data, where two high signals represent a binary 1 character, two low signals represent a binary 0 character, and a combination ay a high and a low signal represents either a start-of-data or an end-of-data character. System according to claim 94, characterized in that one of the operand fields in the data archive in the data store is intended for storing a destination address, and that the said operand fields are contracted when they are empty, until they are expanded by the respective operands that are entered. 100. Binary data processing system with data store and input circuits, characterized by a recursive mechanism comprising: data structures stored in the data store and arranged to represent program data organized in a hierarchically coherent order according to program data archives composed of operand fields and a result field assigned to a special program description field, and data structures received by the input circuits and arranged to represent operand data organized in a hierarchically coherent order, which data structures cause addressing of certain of the data structures in the data store. 101. System according to claim 100, characterized in that a program data archive has at least one operand field and a destination address field assigned to a program description field, which operand field is a vector archive composed of at least one operand field, a result field and a vector description field. 102. System according to claim 101, characterized in that the operand fields and the resultant field in weight or-ja)rki know are contracted when they are empty, until they are expanded by getting data entered. l(0[3. System according to claim 100, characterized in that the operand fields and the resultant fields are contracted when they are empty, until they are expanded by having data entered. 104. Binary data processing system with data store and input circuits, characterized by a recursive mechanism comprising data structures stored in the data store and designed to represent program data organized in a hierarchically coherent order according to program data archives with the following format. ((P)(0P)xxx((V)(0P)xx(A)xx(B)xx(R)[(/ )xx(C)xx(DA) ()) where all bounded areas'within data limitations are fields, where P represents a program description field, OP represents an operator field, while A, B, and C represent operand fields, V represents a vector description field, R. represents a result field, and DA represents a destination address field. 105. System According to claim 104, characterized in that the operand field and the resultant field are contracted when they are empty, until they are expanded when data is entered. 106. Binary data processing system with data store and input circuits, characterized by the recursive mechanism comprising: data structures stored in the data store and designed to represent program data organized in a hierarchically cohesive order. according to a program data archive with the following format: ((P)(0P)xxx((V)(0P)xx(A)xx()(R)()xx(C)xx(DA)()) where "all bounded areas within data boundaries are fields, P represents a program description field, Of]represents an operator field, A and C represent operand fields, V represents a vector description field, R represents a result field, and DA represents a destination address field, and data structures received by the input circuits represent operand data organized in a hierarchically coherent order according to the operand archive composed of at least one operand field and a storage address field assigned to a separate operand description field.. 107. System according to claim 106, where the operand fields and resultant fields in the data store are contracted when they are empty, until they are expanded when data is written. 108. Binary data processing system comprising a data store containing data archives structured in a hierarchically coherent order and input circuits for receiving data archives structured in a hierarchically coherent order, which received data archives effect the addressing of certain of the data archives in data - the warehouse. 109- System according to claim 108, characterized in that the data store contains binary information placed between the mentioned data archives to indicate the start and end of the data archive. 110. System according to claim 108, characterized by output circuits for receiving a destination address field and at least one operand field as well as combining these to form an output message data archive. 111. System according to claim 108, characterized in that the data store contains data archives that represent program data, and that the input circuits receive data archives that represent operand data. 112. System according to claim 111, characterized in that the said fields that form a program archive are separated from each other in the program archive by means of free space in which the said fields can expand, 113- System according to claim 111, characterized in that the program data archives located in the data store contain one or more data archives assigned to a special program field and a destination address field. 114. System according to claim 111, characterized in that the said fields which form an operand archive are separated from each other in the operand archive by means of free space in which the said field can expand. 115. System according to claim 108, characterized in that the data archives that are received by the input circuits comprise an operand field, an operand identification field and a storage address field. 116. Binary data processing system, characterized in that the data communication within and with the system takes place on a character-series basis, where a character has a length of two binary bits, which system comprises a data store containing data archives structured in a hierarchically coherent order, and input circuits for reception of data archives structured in a hierarchically cohesive order, which received data archives effect the addressing of certain of the data archives in the data warehouse. 117. System according to claim 116, characterized in that the data store contains binary data placed between the mentioned data archives to indicate the start and end of the data archives. 118. System according to claim 117, characterized in that four characters are used to represent all data, where two high signals represent a binary 1 character, two low signals represent a binary 0 character, and a combination of a high and a low signal represents either a start-of-data or an end-of-data character. A system according to claim 116, characterized by output circuitry for receiving a destination address field and an operand field and for combining these to form an output string file. 120. System according to claim 116, characterized in that the data store contains data archives representing program data, and that the input circuits receive data archives. which represents operand data. 121. System according to claim 120, characterized in that the program data located in the data store contains operand fields assigned to a program field to form a program archive, which operand fields are empty and contracted until they are expanded by having the respective operand entered. 122. System according to claim 121, characterized in that the aforementioned fields which form a program archive are separated from each other in the program archive by means of free space in which the fields of the archive can expand. 123. System according to claim 120, characterized in that the program data archives located in the data store contain one or more vector archives assigned to a special program field and a destination address field. 124. System according to claim 116, characterized in that the data archive which is received by the input circuits comprises operand fields, an operand identification field and a storage address field, which form an operand archive. 125. System according to claim 124, characterized in that the aforementioned fields which form an operand archive are separated from each other in the operand archive by means of free space in which the archive's fields can expand.