NO312983B1 - Digital processing device - Google Patents

Description

The invention relates to a digital processing device P, in particular for processing digital data and signal structures, where the data and signal structures comprise repeated sequences and/or tangled patterns, and where the processing device P is generally configured as a regular tree with n+1 levels So, Si ,...Sn and of degree k.

Processing large amounts of data using repeated or recursive operations on very large amounts of data, even in a limited number, can often become a bottleneck when using conventional microprocessors and is therefore suitable for massively parallel solutions where a very large number of processing elements simultaneously perform different operations in parallel on a large data stream, but possibly also parallel operations on several data streams. If such large amounts of data appear in the form of data or signal structures with repeated sequences and/or tangled patterns, the processing can be made more efficient by being realized in parallel at the same or several different levels.

From US patent no. 4860201 (Stolfo & al.) a parallel processing device structured as a binary tree is known, where a large number of processors are used, each with a separate I/O unit. In general, Stolfo & al. a computer with a large number of processors connected in a binary tree structure such that each processor except those constituting the root and the leaves of the tree, respectively, has a single parent node processor and two child processors. The processors typically work synchronously with data that is fed to them from the parent processor and pass the results on to the closest succeeding processors, i.e. the parent processor's children. At the same time, the child processors of a parent processor can also communicate with each other.

According to Stolfo & al. each node constitutes a processing element comprising a processor in a proper sense, a read/write memory or random access memory and an I/O device. The I/O device provides interfaces between each processing element and its parent and child processing elements so that there is a significant improvement in the speed at which data is sent through the binary tree structure. As the binary tree structure has a processing element in each and every node, the processing device will generally comprise 2n<->l processing elements, i.e. 1023 processing elements if the binary tree is realized with 10 levels. In a preferred embodiment, this has known

parallel processor device a clock frequency of 12 MHz as in case it

using a tree of 1023 processors each having an average instruction cycle time of 1.8 fis gives a processing performance of approximately 570 million instructions per second.

A binary parallel processor of this kind can e.g. be well-suited to handling decomposable or partitionable computing problems, e.g. searching in large amounts of information. A partitionable search problem can be defined as a problem where a question about the relation between an object x and a set of objects corresponds to a repeated use of a commutative and associative binary operator b that has an identity and a primitive search question that is applied between a new object x and each element f in the set F. One then has a partitionable search problem when the logical function OR is combined with the primitive question "is x equal to f applied between the object x and each element f in F. As stated by Stolfo & al., a problem consisting of to answer a question about the set F, is answered by combining the answers to the questions applied to arbitrary subsets of F. In other words, the problem is partitionable or decomposable and suitable for rapid execution using parallel processing. The set F is partitioned into a number of arbitrary subsets equal to the number of available processors.The primitive query q is then applied in parallel on each processor between about the unknown x that is conveyed to all processors and the locally stored element f in the set F. The results are then arbitrarily combined in parallel by log2N repetitions of the operator b, first performing a number of calculations on N/2 adjacent pairs of processors and then a corresponding number of calculations on N/4 pairs of processors with the results of the first calculations. The operations thus move during the process to overlying levels in the binary tree, i.e. from child processors to the parent processor, etc. and is repeated in parallel at each level.

However, there are a number of data processing problems where the data and signal structures comprise repeated sequences and/or tangled patterns such that a processing device of the kind shown in US patent no. 4860201 does not provide the desired flexibility or is not suitable at all to deal with the problem. A binary tree structure as shown there assumes in principle that the problem can be binary partitioned and that the operations take place in parallel at the same level. However, there may be problems that require a different degree of splitting and where the processing must be able to take place in parallel, but at different levels in the tree structure. The problems can also be partitioned so that it would be desirable to have greater partitioning capacity at one and the same level in some of the subtrees in the tree structure, and this would in practice require solutions that take as their starting point a general tree structure that not only has an arbitrary number of levels, but also is of arbitrary degree, while nodes in subtrees are not only connected to the parent node of the tree in question, but can, for example, be connected to a node at the same or underlying levels in neighboring trees. An increased degree of connectivity in tree structure with a desired number of levels and of arbitrary degree will therefore make it possible to reconfigure the original tree structure either in the form of reduced trees or simple or complex graphs. At the same time, one or more of the leaf nodes, i.e. the child nodes, can be combined and take over the function of the relevant parent node.

The purpose of the present invention is therefore to provide a processing device which is particularly suitable for processing large amounts of data in massive parallelism and at different levels in a general tree structure, but which can at the same time be optionally configured into skeined circuits at different levels and preferably under certain conditions such as that a selected configuration at a given level is recursively generated by a configuration at an underlying level. In particular, it is intended that the processing device according to the invention should be able to realize an MIMD processing device, i.e. a processing device that works with multiple instructions and multiple data.

The above and other purposes are achieved according to the invention with a digital processing device which is characterized by the fact that the processing device P is arranged in the form of a circuit Pn at the level Sn and constitutes the root node of the tree, that the nearest underlying level Sn.i is arranged skeined in the circuit Pn and includes k circuits Pn.l5 which make up the root node's daughter nodes, that generally includes an underlying level Sn.q in the circuit Pn, where qe{l,2,...n-l}, kq circuits Pn.q arranged skeined in the kq' 1 circuits Pn.q+i on the overlying level Sn.q+i, as each circuit Pn.q+i on this level includes k circuits Pn.q, that a zeroth level Sn.q is defined in the circuit Pn for q = n = S0 comprises from k"'<1>*! to k<n> circuits P0 which constitute core processors in the processing device P and at this level S0 form leaf nodes in the tree, the core processors P0 being arranged in a skein in a number of 1 to k in each of the k""<1 >circuits Pi on the level Si, that each of the circuits Pi, P2-..Pn on respective levels Si, S2,...Sn comprises a logical unit E which is generally connected to the circuits P0,Pi...Pn-i arranged in a skein in respective circuits Pl5P2...Pn at the respective closest underlying level S0,Si...Sn_i and optionally configures a network of the latter circuits in the respective circuits Pi,P2...Pn, and that each of the circuits P0,Pi,...Pn has identical interfaces I.

Advantageously, a first embodiment of the processing device according to the invention is characterized by the fact that the zeroth level S0 comprises k" core processors P0, that a core processor P0 recursively maps a circuit Pi on the overlying level with a factor r = k, so that the tree is an unreduced or complete tree, and that in general a circuit Pn.q at the level Sn.q recursively maps a circuit Pn-q+i at the overlying level Sn.q+i with the factor r = k.

Furthermore, another embodiment of the processing device according to the invention is advantageously characterized in that the zeroth level S0 comprises rk"'<1 >core processors P0, where l<r<k, that a core processor Po maps a circuit Pi on the overlying level Si with the same factor r, so that the tree is a symmetrically reduced or balanced tree, and that in general a circuit Pn.q on all levels from the level Si maps a circuit Pn.q+i on the overlying level S„.q+i recursively with the factor r = k.

Finally, a third embodiment of the processing device according to the invention is advantageously characterized by the skein in each circuit P! on the level Si are respectively arranged from 1 to k core processors, that at least one of the circuits Pi includes at least 2 and at most k-1 core processors P0, so that the total number of core processors P0 on the level S0 amounts to at least kn' l+ l and at most k <n->l, and the tree becomes an asymmetrically reduced or unbalanced tree, and that in general a circuit Pn.q is mapped at the level Sn.q by the circuits Pn.q.i snared in the respective circuit Pn.q.

Advantageously, according to the invention, the core processor may comprise at least one combinatorial unit C and a memory unit M connected to the at least one combinatorial unit C, with preferably at least part of the memory unit M being configured as a register unit R. In the latter case, preferably the at least one combinatorial unit C and the register unit R be configured as an arithmetic logic unit ALU.

Advantageously, according to the invention, the logic unit comprises at least one combinatorial unit C and a register unit R connected to the at least one combinatorial unit C, the at least one combinatorial unit C preferably being a multiplexer. It is then advantageous that the logical unit E in a circuit Pn.q is arranged to be connected to the logical unit E in a corresponding circuit Pn.q at the same level Sn.q in a neighboring tree.

It is also advantageous that the logic unit E in a circuit Pn.q, is arranged to be connected to the logic unit E in circuits Pn.q.i, Pn-q-2> --.Pi at respective underlying levels Sn.q.i, Sn.q.2, ...Si in a neighbor tree.. Finally, it is also advantageous when the logical unit in a circuit Pn.q is arranged to be connected to one or more core processors P0 in a neighbor tree, either directly or via the logical unit E in the circuit Pi, where the relevant core processor(s) P0 are entwined.

The invention will now be explained in more detail in connection with design examples and with reference to the accompanying drawing, where

fig. 1 shows a first embodiment of the processing device according to the invention,

fig. 2 the embodiment in fig. 1 configured as a regular tree structure,

fig. 3 the tree structure for another embodiment of the processing device according to the invention,

fig. 4a a third embodiment of the processing device according to the invention, configured as an asymmetrically reduced tree,

fig. 4b an example of a subtree with leaf nodes in the tree structure representing the processing device according to the invention,

fig. 4c another example of a subtree with leaf nodes in the tree structure representing the processing device according to the invention,

fig. 5 schematically shows the principle for forming the processing device according to the invention as a skeined circuit by recursive mapping,

fig. 6 an embodiment of the processing device according to the invention as a recursive circuit with three levels and degree four,

fig. 7 another embodiment of the processing unit according to the invention as a recursive circuit with four levels and likewise degree four,

fig. 8 possible connections between the nodes in a tree corresponding to the circuit in fig. 6,

fig. 9 possible connections between the nodes in a tree corresponding to the circuit in fig, 7,

fig. 10 the circuit in fig. 6 and fig. 8 connected as a one-dimensional graph,

fig. Ila schematically a general embodiment of a core processor in the processing device according to the invention,

fig. 1 lb schematically an embodiment of a circuit with a logic unit and a core processor in the form of a comparator unit for use in a search processor device based on the processing device according to the invention,

fig. 12a the comparator unit of fig. 1 lb,

fig. 12b the connection of comparators similar to that in fig. 12a to compare a pattern of e.g. 3 characters, and

fig. 12c a balanced binary tree realized with circuits corresponding to that of fig. 11b.

Fig. 1 schematically shows the structure of a parallel processing device according to the present invention. Formally, the form in fig. 1 is described as follows: Given a circuit P0 with an interface IP() and a further circuit E, a repeated sequence of circuits Pi, P2,..P3, with respective interfaces Ipj, Ip2,... Ipn each consisting of respectively k circuits Po, P2,...Pn-i and a single further circuit E, the interfaces I being identical for all circuits P0, Pi ,...Pn, m.a.o. is IP() = IPl <=> I<p>2... <=> IP[i. In each case, the circuit Pi is configured as a tree network with n+1 levels S and of degree k. Specifically, fig. 1 a digital processing device in the form of the circuit P4 which forms a tree with five levels S and has degree 3. This means, as shown in fig. 1, that the circuit P4 located at the level S4, on the underlying level comprises three circuits P3. Each of the circuits P3 on the level S3 is formed with three circuits P2 on the underlying level S2 and each of the circuits P2 on the level S2 is formed with three circuits Pi on the underlying level Si. Finally, each of the circuits Pi on the level Si is formed with three circuits P0 on the level So. The circuits P0 constitute the actual processor units in the processing device P4 and form P4's core processors. Then the circuit P4 as shown in fig. 2, is structured as a ternary tree, this means that the level S0 comprises a total of 34 = 81 core processors Po, the overlying level Si 27 circuits Pi and the following level S2 9 circuits P2. Finally, level S3 has 3 circuits

P3. Each of the circuits P0, Pi, P2, P3 and P4 constitute nodes in the tree of fig. 2. The core processors P0 constitute the tree's leaf nodes and the circuit P4 the tree's root node. Structured in this way, the tree appears in fig. 2 as a recursive ternary tree, in that a circuit at an arbitrary level S recursively maps the circuit at the next closest overlying level with a mapping factor r = k which in this case is 3. Each of the circuits Pi, P2, P3, P4 also comprises a logical unit E, so that the logical units E in all circuits Pi, P2, P3, P4 physically form the nodes in the tree. By means of the logical unit E, each node in the tree can generally be connected to its parent node or to its child nodes. Through the logical unit, each of the node's child nodes can also be interconnected. Each of the core processors that make up the tree's leaf nodes also has respective circuits Pi as parent nodes and can be connected to each other via these. As is known per se, the problem which the processing device according to the invention is to process is partitioned, and the processing is executed at the level So in parallel by the core processors P0. The results from the core processors P0 are combined and passed on by the respective parent node Pi. This process is repeated until the final result is available on circuit P4.

Both the core processor P0 and the logical unit E shall be described in more detail in the following.

However, the circuit P4 need not be realized as a complete or regular recursive tree. It may well be formed as a symmetrically reduced tree and this implies that the number of leaf nodes or the number of core processors P0, connected to the nodes Pi is reduced so that each circuit Pi includes two or more leaf nodes or core processors P0, but in each case less than k core processors P0 . Since the circuit in fig. 1 has k = 3, it means that the symmetrically reduced tree as shown in fig. 3, comprises two core processors P0 for each circuit Pj. The symmetrically reduced tree in fig. 3 is, in other words, not regularly recursive, since the recursion first takes place from level Si with a mapping factor r = 3. Performed as in fig. 1, each circuit Pi in the tree in fig. 3 besides the logical element E include only two core processors P0.

The recursive mapping of circuits on an underlying level to an overlying level naturally implies that these circuits will be entangled in a circuit on the overlying level and the entire circuit P4 thus appears as an entangled circuit.

If the circuit is an asymmetrically reduced circuit, it may appear as shown in fig. 4a. Here, some of the nodes Pj regularly have three leaf nodes P0, other nodes Pi only two leaf nodes P0 and still other nodes Pi only a single leaf node P0.1 in the latter case, the mapping of the parent node of Pi becomes an identity mapping of it, and as far as the logic element E is looped in the circuits P^ If therefore all circuits Pi include only a single core processor P0, the tree forming the circuit P4 will appear to be completely reduced, as Pi = P0 and the circuit P4 is transformed into a regular recursive circuit P3 with four levels and 27 core processors Po at level S0. Therefore, if the number of levels is n+1, a circuit Pn must have at least k<n>_<1>+l core processors at level So in order not to appear as a completely reduced tree.

A subtree in a maximal asymmetric reduced tree is shown in fig. 4b, as this subtree comprises a node P2 with child nodes Pi, so that only one of the nodes Pi has two core processors or leaf nodes P0, while all of the other nodes Pi in the tree only have a single leaf node Po, so that Pi in these cases is reduced to Po- With five levels corresponding to the circuit in fig. 1 would therefore have a circuit Pi configured as shown in fig. 4b, i.e. with two leaf nodes in a circuit Pi and otherwise only one leaf node in each of the other nodes Pi, appear as a maximally asymmetrical reduced tree and the number of nodes at level S0 is, in other words, 3 +1 =28. Correspondingly, a subtree for the node P2 in a minimal asymmetric reduced tree is shown in fig. 4c. Here, a single node Pi includes two leaf nodes or core processors P0, while all of the other nodes Pi in the tree which previously included three leaf nodes P0. This naturally implies that a minimal asymmetrically reduced tree corresponding to the circuit in fig.1 will in this case comprise a total of 80 core processors P0. A circuit formed like the trees shown in fig. 4 will of course still appear as the skein on all underlying levels S0, Si, S3, but the mapping will no longer be recursive, as a circuit Pi, P2, P3, P4 will be mapped by all circuits located on the respective underlying levels S0 , Say, S2, S3. The advantages of forming the circuit P4 as a symmetrical or asymmetrical reduced tree will be discussed in more detail below.

Fig. 5 shows how a recursively self-imaging processing device Pn according to the invention is formed. The circuit Pn is realized as a tree with n+1 levels and of degree k = 4. Each of the circuits is P0, Pi...Pn.i is entwined in the respective circuits Pl9 P2...Pn on the nearest overlying level Si , S2,...Sn. The number of entwined levels is then naturally n and the circuit Pn will at the zeroth level So defined by the core processors P0 comprise a total of k<n> such core processors. In general, the number of circuits Pn.q at a level Sn.q, where q = 0, 1, 2,...n will be equal to k<q>. Fig. 6 shows a skeined circuit P2 generated as a recursive tree according to the principle of fig. 5. The circuit P2 comprises the logical unit E and the skein on the underlying level Sj four circuits Pi which each in turn comprise the logical unit E and the skein on the underlying level each four circuits or core processors P0. The logic units configure the circuit P2 as a quaternary tree with three levels S0, Si, S2, and a total of sixteen core processors Po or leaf nodes at level S0. Correspondingly, fig. 7 a sequentially generated circuit with five levels S and k = 4. The circuit in fig. 7 constitutes m.a.o. a quaternary configured tree with a total of 64 core processors P0 at level S0. As before, the interfaces I of each circuit P0, Pi P2, P3, P4 are of course identical. Fig. 8 shows the circuit P2 in fig. 6 generally configured as a quaternary tree but also such that, for example, the circuits P]5, i.e. the nodes at level Si, are interconnected with a core processor P0 in the neighboring tree at level S0. In general, the logical unit E in one of the nodes Pi, P2...Pn will not only allow a link up and down in the subtree where the node is located, but also a link to nodes in neighboring trees within the same level or a link to the nearest node at an underlying level in the neighbor tree. For the circuit of fig. 6, the node Pi in a subtree can thus be connected to the first leaf node P0 in the neighboring tree, etc.

Correspondingly, fig. 9 connections in the circuit of fig. 7 which constitutes a quaternary tree with four levels and a total of 64 core processors. Here again, a node at a given level can be connected to the node in the neighbor tree at the same level or to the nearest adjacent nodes in the neighbor tree at any underlying level.

This means that the general tree structure can be configured via the logical element into various more or less complex graphs. An example of fig. 10 is shown where the circuit P2 in fig. 6 or fig. 8 is reconfigured so that P2 in reality constitutes a one-dimensional graph where the sixteen core processors Po are connected sequentially.

Usually, the processing device according to the invention will be realized as a dedicated processing device for a specific task, e.g. image processing. Based on the general tree structure, the configuration can be task-specific, either operationally or physically. If the configuration takes place operatively, the circuit via the interface is supplied with configuring parameters that realize the network appropriate for the processing. The configuration may thus well mean that the circuit is configured with fewer core processors than are actually arranged in the circuit. The processing device according to the invention can then appear as a symmetrically reduced tree, as shown in fig. 3, or an asymmetrically reduced tree, as shown in fig. 4. For certain concrete data processing tasks, a larger number of core processors may be required in one or more subtrees to increase

the processing device's capacity for a specific task.

As mentioned, the processing device according to the invention can also appear as a physically reduced tree, whether it is symmetrically or asymmetrically reduced. This means that the physical circuit solution is in reality realized with a smaller number of core processors than that given by the number of levels S in the tree and the degree k. This can be appropriate to achieve a circuit engineering solution that makes optimal use of the space conditions on the chip. If the number of core processors in a dedicated processing device according to the invention can be physically reduced, this means, for example, a reduction in the physical size of the circuit chip or a better utilization of the space on the chip, depending on the actual architectural solution that is chosen. The prerequisite is, of course, in all circumstances that the task for which the processing device is intended is carried out.

The circuit P0 defines a null, unseeded level in the processing device P and constitutes a core processor in P.

The core processor Po is generally shown in fig. 1 la and comprises a combinatorial unit C connected to a memory unit M. The interface IP() in the core processor P0 which is of course identical to the interface I of the other circuits Pi,... Pn is schematically indicated on the side of P0 with arrows denoted "In " and "Out" for input side and output side respectively. The combinatorial unit C receives on the input side data in the form of operational parameters that comprise the data to be processed. In addition, the input side also supplies data in the form of configuring parameters for the core processor Po. These configuring parameters can consist of instructions as well as setting parameters for sub-elements in the combinatorial unit C and the memory unit M. If the data to be processed takes the form of structures with repeated sequences and/or tangled patterns and the processing of the data is specifically aimed at certain sequences and patterns with the use of a relatively limited instruction set, the memory unit can advantageously be fully or partially configured as a register unit R, as each register unit can comprise a number of registers with a fixed length and address respectively, depending on the operations to be performed during the processing. The output side of the interface delivers the results of the processing e.g. to a not shown external I/O interface for the entire processing unit P„ or delivers the results to other core processing units P0 in the circuits Pi or to the input interfaces in circuits P2, P3 ...Pn at superordinate levels S2, S3....Sn.

A specific embodiment of a circuit Pi for use in a search processor device is shown somewhat schematically, but with all the main components in fig. 11b. The interface is shown respectively as an input interface Iin and an output interface Iout. The input interface Iin is connected to a multiplexer MUX with outputs respectively to the output interface Iout, a comparator unit COM corresponding to the core processor unit P0, a first D flip-flop and a sequence control unit SC. The comparator unit COM is used in a search operation to compare characters or strings of characters that form given patterns. In this way, it can be determined whether a given pattern can be found in the form of one or more elements in a quantity formed by different patterns. The comparator unit COM forwards the received data to the output interface Iout and the result of the comparison to a latency unit LAT which can be used to delay a positive binary value a given number of cycles. The latency unit LAT is therefore connected via the D flip-flop Di to an output of the multiplexer MUX and itself delivers the result of the comparison to the sequence control unit SC which is arranged to respectively require that a core processor connected before or after the present one reports a match before the present core processor itself can report a match, and allows comparison of patterns in case certain parts of the pattern are missing and also comparison of patterns where certain parts of the pattern may be repeated. The sequence control unit SC is connected on the input side to the D flip-flop Di and on the output side to the D flip-flop D2, the number of flip-flops must be equal to the number of characters compared by the comparator unit COM. The sequence control unit SC must be able to receive results from a comparison operation in the preceding or following processor unit and is therefore connected to the input interface Iin and the multiplexer MUX and itself reports the results of the comparison operation further over the output interface Iout. Finally, the circuit Pi in this embodiment also includes a result selector RS which is used to combine two result values from other core processors or other result selectors. The result selector RS is therefore connected to the input interface Iin and the output interface Iout respectively and can perform Boolean operations on two result values or compare operations of the type greater than, less than or equal to across a set of processors.

In a specific embodiment, a digital processing device P can be arranged for various forms of numerical data processing in massive parallelism, and the combinatorial unit C and a register unit R will then be configured as an arithmetic logic unit ALU. Each core processor P0 can also include a memory unit M configured as RAM and can thus implement an intelligent RAM (IRAM) so that latency problems are reduced or eliminated in data processing of this kind.

At each entangled level Si, S2,...Sn, a further circuit is also arranged in the form of a logic unit E which can itself be a processor unit consisting of a combinatorial unit C and a register unit R. The logic unit E is generally identical for all circuits Pi, P2-. Pn- For the circuit P, for example, the logic unit E corresponds to all the components shown in fig. 11b with the exception of the interface I and the comparator (core processor COM). In a regular binary tree, the circuit P[ in fig. 1 lb have two core processors, i.e. two connected comparator units COM. Advantageously, the circuit E at each level Si, S2...Sn will function as a processing unit for the purpose of configuring the network at the respective level and possibly underlying levels where the circuit E is included in each node in the network. By supplying the circuit E with suitable network configuring parameters, a network at a given level can be optimally configured for the processing task to be performed. The logical unit E is designed to be connected to nodes at the same or underlying level in neighboring trees and, starting from a regular tree structure, can transform this into more or less complex graphs and networks to better handle task-specific data volumes and data rates, e.g. in the case of problems that cannot be balanced partitioned.

The combinatorial unit in the core processor P0 realized as a comparator unit COM and used in a search processor device is shown in fig. 12a. Here, a register x contains the data word that is currently in the comparator unit COM and register a contains the data word that x is to be compared with. It can be seen from fig. 12a it is easily seen that four comparisons can be performed, namely x = a, x>a, x?ta or x < a, and the result is delivered to the output of the multiplexer MUX. With an interconnection of comparator units as shown in fig. 12a, simple patterns in the form of character strings can be compared. The principle is shown in fig. 12b where the shown and connected units will be able to compare the string abc, i.e. a directly followed by a b, directly followed by a c.

If the processing device according to the present invention is to be implemented as a search processor device, an unreduced and balanced binary tree can be used. For each internal node in the tree, i.e. all nodes with the exception of the root node and the leaf nodes, a multiplexer is used to determine whether two subtrees are to receive the same data elements in parallel or whether they are to receive data in sequence. This corresponds to connecting nodes at two different levels in neighbor trees, as already discussed.

Fig. 12c shows a search processing device realized as a binary tree with 8 core processors, here shown as circuits 0, 1, ...7.1 in this connection it should be noted that when the results are obtained from two circuits or two core processors these will be combined using logical operations . This happens in the result selector RS. The logic unit E in each circuit comprises, as shown in fig. 1 lb a result selector RS which also allows only one of the results to be selected. The result selectors used in a binary tree will e.g. return a single result from a group of processing elements. At the same time, the search processing device in the form of a binary tree must also obtain the results of a comparison of characters or character strings made before or after the comparison of the character or character strings currently being processed by the core processor or the comparator unit COM. Using a sequence control unit in the logical unit, the tree can be configured so that a comparison operation can be performed by selecting the results either to the right or to the left of any elements that compare different characters or character strings. Moreover, when a series of comparator units compare the same characters or character strings, their preceding and succeeding results are the same. These results can be found by using the same multiplexer MUX that controls the data flow, so that a comparison result is passed on to any of the neighboring elements that compare the same character or string of characters. This is also realized in the search processor device as shown in fig. 12c. In this connection, it should be noted that the same multiplexer set is now used for three separate purposes, namely, to allocate data, to route bits of memory through the correct number of flip-flops, and to obtain or deliver the result of comparisons of preceding or succeeding characters or character strings. However, the results from different core processors can also be combined using a lookup table unit which can be connected between the subtrees and the output of the search processor device. The lookup table unit will then replace the result selectors RS shown in fig. 12c.

The skeined and possibly recursively formed processing device P according to the invention can be used to form task-specific processing devices for processing large amounts of data in massive parallelism. Examples of such tasks can be searching in large amounts of data structured in the form of documents, where the search takes place simultaneously in parallel in all or a large number of documents and e.g. can be aimed at finding, identifying and comparing patterns. Furthermore, the processing device according to the invention can for example be configured for image processing, encryption and decryption as well as processing based on recursive procedures in general. Used as a pure numerical processor, the processing device according to the invention could be arranged for factorization.

As mentioned, the core processors P0 can be based on standard microelectronic components, and these can, for example, be implemented as a so-called field-programmed gate group (FPGA) or as an application-specific integrated circuit (ASIC), in both cases with a varying scale of integration. As the processing unit according to the invention can be scaled in several dimensions, e.g. with regard to processor capacity or connectivity, however, the realization is not locked to a specific technology or a specific technological level, but can in practice be implemented based on the technological level available at any time, so that the performance of the processing unit can be improved in line with technical development.

In principle, the processing device P according to the present invention could be realized with an arbitrary degree k and an arbitrary number of n+1 levels S. In each case, the number of core processors will be given by k<n>. In reality, however, both k and n will be limited by the microelectronic technology available to realize the processing device P and, in particular, by the available integration scale. Depending on both the technology and the specific processing tasks processing devices P are to be realized for, the chosen values for k and n can be made the subject of a trade-off, e.g. depending on the need for parallelism and degree of partitioning. In a practically realized implementation, e.g. the processing unit Pn realized with k = 8 and n = 3, i.e. 512 core processors P0 at the level So-

When using standard microelectronics based on conventional inorganic semiconductor technology, for example silicon technology, the connectivity, i.e. the interconnection of the circuits in a network, can present problems in the form of complexity and long signal paths if the processing unit P is realized integrated in mainly planar technology on a substrate. In principle, however, the network is reconfigurable, i.e. a network configured for one task can be configured to another network, e.g. with the use of suitable configuration parameters via the logical unit E. However, for certain tasks within massively parallel processing, it may be desirable to have a high degree of connectivity and ideally with total connectivity, i.e. that all nodes are interconnected. In that case, the degree of connectivity for m nodes will scale as m<2>/2, and even for a limited number of m, for example 512, will be difficult to realize using conventional circuit topologies. One possibility to realize a circuit topology is to stack circuits based on organic thin film technology on top of each other in a volumetric configuration and use both vertically and horizontally conducting structures to form connections between the individual nodes or circuits, so that a three-dimensional network topology is obtained that will allow a very high degree of connectivity. Such technologies are shown in NO patent application 19982518 (Gudesen, Leistad and Nordal) which is aimed at an integrated scalable data processing device with MIMD architecture and realized as a volumetrically structured unit, including optimal network topologies and a high degree of connectivity for massively parallel processing.

Claims (12)

1. Digital processing device P, in particular for processing digital data and signal structures, where the data and signal structures comprise repeated sequences and/or nested patterns, and where the processing device P is generally configured as a regular tree with n+1 levels S0, S3, ...Sn and of degree k, characterized by that the processing device P is arranged in the form of a circuit Pn at the level Sn and constitutes the root node of the tree, that the closest underlying level Sn.\ is arranged skeined in the circuit Pn and includes k circuits Pn_i, which constitute the child nodes of the root node, that generally includes an underlying level Sn.q in the circuit Pn, where qe {l,2,...n-l}, kq circuits Pn.q arranged skeined in the k<q_1> circuits Pn.q+i on the overlying level Sn .q+i, as each circuit Pn.q+i at this level includes k circuits Pn.q, that a zeroth level Sn.q = S0 defined in the circuit Pn for q = n includes from k<n>"'+l to k<n> circuits P0 which constitute core processors in the processing device P and at this level So form leaf nodes in the tree, the core processors P0 being arranged skeined in a number of 1 to k in each of the k"'<1 >circuits Pi at level Si , that each of the circuits Pi, P2...Pn at respective levels Si, S2,...Sn comprises a logic unit E which is generally connected to the circuits P0,Pi arranged in a skein in respective circuits Pi,P2...Pn. ..Pn-i on the respective nearest underlying level S0,Si...Sn_i and optionally configures a network of the latter circuits in the respective circuits Pi,P2...Pn, and that each of the circuits P0,P], ...Pn have identical interfaces I. 2. Digital processing device P according to claim 1, characterized in that the zeroth level So comprises k<n> core processors P0, that a core processor P0 recursively maps a circuit Pi on the overlying level with a factor r = k, so that the tree is an unreduced or complete tree, and that in general a circuit Pn.q at the level Sn.q recursively maps a circuit Pn-q+i at the overlying level Sn.q+1 with the factor r = k. 3. Digital processing device P according to claim 1, characterized in that the zeroth level S0 comprises rk<n>"' core processors P0, Kr<k, that a core processor P0 maps a circuit Pi on the overlying level Si with the same factor r, so that the tree is a symmetrical reduced or balanced tree, and that in general a circuit Pn.q on all levels from the level Sj maps a circuit Pn.q+i on the overlying level Sn.q+i recursively with the factor r = k . 4. Digital processing device P according to claim 1, characterized in that the skein in each circuit Pi at level Si is arranged respectively from 1 to k core processors, that at least one of the circuits P] comprises at least 2 and at most k-1 core processors P0, so that the total number of core processors P0 at level S0 amounts to at least k<n>"'+l and at most k<n->1, and the tree becomes an asymmetrically reduced or unbalanced tree, and that in general a circuit Pn.q is mapped at the level Sn.q of the shunted circuits Pn.q-i in the respective circuit Pn.q. 5. Digital processing device P according to claim 1, characterized in that the core processor Po comprises at least one combinatorial unit C and a memory unit M connected to the at least one combinatorial unit C. 6. Digital processing device P according to claim 5, characterized in that at least part of the memory unit M is configured as a register unit R. 7. Digital processing device Pi according to claim 6, characterized in that the at least one combinatorial unit C and the register unit R are configured as an arithmetic logic unit ALU. 8. Digital processing device P according to claim 1, characterized in that the logical unit E comprises at least one combinatorial unit C and a register unit R connected to the at least one combinatorial unit C. 9. Digital processing device P according to claim 8, characterized in that the at least one combinatorial unit C is a multiplexer. 10. Digital processing device P according to claim 9, characterized in that the logical unit E in a circuit Pn.q is arranged to be connected to the logical unit E in a corresponding circuit Pn.q at the same level Sn.q in a neighbor tree. 11. Digital processing device P according to claim 9, characterized in that the logical unit E in a circuit Pn.q is arranged to be connected to the logical unit E in circuits Pn.q.i, Pn-q-2> ... Pi at respective underlying levels Sn_q_i, Sn_q_2, ...Si in a neighbor tree. 12. Digital processing device P according to claim 11, characterized in that the logical unit E in a circuit Pn.q arranged to be connected to one or more core processors P0 in a neighboring tree, either directly or via the logical unit E in the circuit Pi, where the relevant core processor(s) P0 are snared.