NO20024781L - Page mode deletion in a flash memory layout - Google Patents

Page mode deletion in a flash memory layout

Info

Publication number
NO20024781L
NO20024781L NO20024781A NO20024781A NO20024781L NO 20024781 L NO20024781 L NO 20024781L NO 20024781 A NO20024781 A NO 20024781A NO 20024781 A NO20024781 A NO 20024781A NO 20024781 L NO20024781 L NO 20024781L
Authority
NO
Norway
Prior art keywords
rows
deletion
storage cells
flash memory
volts
Prior art date
Application number
NO20024781A
Other languages
Norwegian (no)
Other versions
NO20024781D0 (en
Inventor
Anil Gupta
Steven J Schumann
Original Assignee
Atmel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atmel Corp filed Critical Atmel Corp
Publication of NO20024781D0 publication Critical patent/NO20024781D0/en
Publication of NO20024781L publication Critical patent/NO20024781L/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups

Abstract

I en sektor i en flashlagergruppe er det fremskaffet SIDESLETTING- og FLERSIDESLETTING-operasjonsmodi. I SIDESLETTING- og FLERSIDESLETTING-operasjonsmodiene blir et foretrukket tunnelnedbrytingspotensial på omkring -10 volt påtrykt portelektrodene til flashlagercellene på den rad eller de rader som er valgt ut for sletting, og bit-linjene som er tilkoblet slukelektrodene til flashlagercellene blir drevet til en foretrukket spenning på omkring 6,5 volt. For å redusere uttilsiktet sletting av lagerceller i andre rader enn den valgte rad eller de valgte rader, blir en foretrukket forspenning på fra omkring 1 til 2 volt påtrykket portelektronene til alle flashlagercellene i andre rader enn den valgte rad eller de valgte rader.In a sector of a flash memory group, SIDE DELETION and MULTI PAGE DELETE operation modes are provided. In the SIDE DELETION and MULTI-SIDE DELETION operating modes, a preferred tunnel degradation potential of about -10 volts is applied to the gate electrodes of the flash storage cells on the row or rows selected for deletion, and the bit lines connected to the flash storage electrodes of the flash storage cells are driven to the about 6.5 volts. To reduce accidental erasure of storage cells in rows other than the selected row or rows, a preferred bias voltage of from about 1 to 2 volts is applied to the gate electrons of all flash storage cells in rows other than the selected row or rows.

NO20024781A 2000-04-04 2002-10-03 Page mode deletion in a flash memory layout NO20024781L (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/542,434 US6359810B1 (en) 1998-03-13 2000-04-04 Page mode erase in a flash memory array
PCT/US2001/010948 WO2001075899A2 (en) 2000-04-04 2001-04-03 Page mode erase in a flash memory array

Publications (2)

Publication Number Publication Date
NO20024781D0 NO20024781D0 (en) 2002-10-03
NO20024781L true NO20024781L (en) 2002-11-29

Family

ID=24163815

Family Applications (1)

Application Number Title Priority Date Filing Date
NO20024781A NO20024781L (en) 2000-04-04 2002-10-03 Page mode deletion in a flash memory layout

Country Status (10)

Country Link
US (1) US6359810B1 (en)
EP (1) EP1269478A2 (en)
JP (1) JP2003529886A (en)
KR (1) KR20030014383A (en)
CN (1) CN1432181A (en)
AU (1) AU2001253141A1 (en)
CA (1) CA2408402A1 (en)
NO (1) NO20024781L (en)
RU (1) RU2002129292A (en)
WO (1) WO2001075899A2 (en)

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ITMI20022240A1 (en) * 2002-10-22 2004-04-23 Atmel Corp FLASH MEMORY ARCHITECTURE WITH MODE CANCELLATION
KR100705221B1 (en) 2004-09-03 2007-04-06 에스티마이크로일렉트로닉스 엔.브이. Flash memory device and method of erasing the flash memory cell using the same
US7257033B2 (en) * 2005-03-17 2007-08-14 Impinj, Inc. Inverter non-volatile memory cell and array system
US7679957B2 (en) 2005-03-31 2010-03-16 Virage Logic Corporation Redundant non-volatile memory cell
KR100749736B1 (en) * 2005-06-13 2007-08-16 삼성전자주식회사 Flash memory device and erase method thereof
KR100739256B1 (en) * 2006-05-12 2007-07-12 주식회사 하이닉스반도체 Flash memory device with a function for changing selectively size of memory cell block in erase operation and erase operation method of the same
JP2007317247A (en) * 2006-05-23 2007-12-06 Nec Electronics Corp Nonvolatile semiconductor memory device and operating method of nonvolatile semiconductor memory device
US7593259B2 (en) 2006-09-13 2009-09-22 Mosaid Technologies Incorporated Flash multi-level threshold distribution scheme
US7646636B2 (en) * 2007-02-16 2010-01-12 Mosaid Technologies Incorporated Non-volatile memory with dynamic multi-mode operation
US7577059B2 (en) * 2007-02-27 2009-08-18 Mosaid Technologies Incorporated Decoding control with address transition detection in page erase function
US7804718B2 (en) * 2007-03-07 2010-09-28 Mosaid Technologies Incorporated Partial block erase architecture for flash memory
US7719896B1 (en) 2007-04-24 2010-05-18 Virage Logic Corporation Configurable single bit/dual bits memory
US7577029B2 (en) * 2007-05-04 2009-08-18 Mosaid Technologies Incorporated Multi-level cell access buffer with dual function
JP4712769B2 (en) * 2007-07-09 2011-06-29 ルネサスエレクトロニクス株式会社 Nonvolatile semiconductor memory device
US7826262B2 (en) * 2008-01-10 2010-11-02 Macronix International Co., Ltd Operation method of nitride-based flash memory and method of reducing coupling interference
KR101468098B1 (en) * 2008-06-23 2014-12-04 삼성전자주식회사 Flash memory device and memory system including the same
US9588883B2 (en) * 2011-09-23 2017-03-07 Conversant Intellectual Property Management Inc. Flash memory system
CN105489244A (en) * 2014-10-11 2016-04-13 北京兆易创新科技股份有限公司 Erasing method of nonvolatile storage
CN105575430B (en) * 2014-10-11 2020-02-07 北京兆易创新科技股份有限公司 Erasing method of nonvolatile memory
CN105575427B (en) * 2014-10-11 2020-02-04 北京兆易创新科技股份有限公司 Erasing method of nonvolatile memory

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US5099297A (en) 1988-02-05 1992-03-24 Emanuel Hazani EEPROM cell structure and architecture with programming and erase terminals shared between several cells
EP0550751B1 (en) * 1990-09-25 1998-01-07 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory
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US5416738A (en) * 1994-05-27 1995-05-16 Alliance Semiconductor Corporation Single transistor flash EPROM cell and method of operation
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US6118705A (en) * 1998-03-13 2000-09-12 Atmel Corporation Page mode erase in a flash memory array

Also Published As

Publication number Publication date
US6359810B1 (en) 2002-03-19
RU2002129292A (en) 2004-03-10
WO2001075899A2 (en) 2001-10-11
CA2408402A1 (en) 2001-10-11
NO20024781D0 (en) 2002-10-03
CN1432181A (en) 2003-07-23
JP2003529886A (en) 2003-10-07
EP1269478A2 (en) 2003-01-02
AU2001253141A1 (en) 2001-10-15
WO2001075899A3 (en) 2002-02-21
KR20030014383A (en) 2003-02-17

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