NL8901502A - Audio or video signals recording system - uses two heads to double recording speed without raising bit-rate for compact disc - Google Patents

Abstract

The input signal (Vi) to the recording system (120) is fed to a converter (121) which consists of an input buffer (126), microprocessor (127) and two series to parallel converters (128, 129), converting the signal into two bit streams (i1, i2) each having a bit rate lower than that of the input signal. The two signals are fed to conventional 'CIRC' encoders (13a, 13b) in the head drive systems (1a, 1b). The operation of the converter and the head drive control processors (11a, 11b) are controlled via a main processor (123) by a control panel (122). The disc is 'played back' using a complementary double head unit.

Description

N.V. Philips' Incandescent light factories in Eindhoven and Philips and Dupont Optical in Nieuwegein.

Method for recording information.

The invention relates to a method for recording an information signal with a determined bit frequency.

Such a method is known from European patent application EP-A 0265984 (PHN 12.063). There, the recording of a standard CD audio signal on a record carrier of a recordable type is described. A standard CD audio signal includes a series of digitized samples of an audio signal sampled at a frequency of 44.1 kHz. The number of bits per sample is sixteen. Especially for professional applications, there is a desire to record digitized audio signals obtained with a higher sampling frequency and where the number of bits per sample is greater than sixteen. This means that the number of information bits per time unit to be recorded is higher than is possible with the known recording device.

The object of the invention is to adapt the recording method according to the opening paragraph in such a way that recording of a larger number of information bits becomes possible.

This object is achieved according to the invention in that prior to recording the said information signal is converted into at least two information signals, each having a second bit frequency lower than the determined bit frequency, each of the latter information signals being recorded by means of a separate recording device which recording devices are suitable for recording information signals having a bit frequency equal to or higher than the second bit frequency, but less than the first determined bit frequency.

Further embodiments as well as the advantages thereof will be described in detail hereinafter with reference to Figures 1 to 8, in which Figure 1 shows an embodiment of a recording device, Figure 2 shows an embodiment of a reading device, Figure 3 schematically converting the bitstream with a first format in a bitstream with a second format, figure 4 shows how the conversion rules for the conversion process shown in figure 3 can be recorded, figures 5 and 6 shows embodiments for a reformation circuit for applications in a recording and reading device, figures 7 and 8 serve to illustrate the method according to the invention.

Figure 1 shows a recording device 1 according to the invention. The recording device 1 is provided with drive means, for instance in the form of a drive motor 2 and a turntable 3, for rotating about an axis 9 for a disc-shaped record carrier 4 of a writable type, for instance a plate writable with the aid of a radiation beam. A recording head, for example an optical recording head 5 of a conventional type, is arranged opposite the rotary record carrier 4. The speed at which the record carrier 4 is advanced along the recording head 5 (in short the recording speed) is controlled at a reference value determined by a reference source. Such a reference source may consist of an oscillator 6 which generates a periodic signal with an adjustable frequency indicative of the desired recording speed. In the case of a record carrier with a track track with a periodic track modulation, which is described in detail in Dutch patent application NL-A-8800152 (PHN 12.399), which is hereby incorporated by reference in the description, the control of the recording speed are realized using phase-locked loop techniques. A signal having a frequency, which is determined by the frequency of the track modulation, is thereby extracted from the recording head 5 and supplied to a phase detector 7. The phase detector 7 detects the phase difference between the signal from the recording head 5 and the reference signal from the oscillator 6. A signal indicative of the determined phase difference is applied to an excitation circuit 8, which, depending on the determined phase difference, controls the motor 2 such that this phase difference remains essentially constant. Furthermore, the recording device is provided with a reformating circuit 10 for converting an information signal Vi into a series of information bits i [n] which is divided into blocks according to conversion instructions which can be set by means of a control circuit 11, for example a microcomputer 4. Information regarding these conversion rules can be input by means of input means, for example a control panel 12 of a usual type, into the microcomputer 11, which passes this information to the formatting circuit 10. The series of information bits i [n] at the output of the 10 is supplied. to a cascade circuit of a CIRC encoder 13 and an EFM modulator 14 which convert the sequence of information bits i [n] into a sequence of code bits c [n] modulated according to the CD standard. The series of code bits c [n] is supplied to a control circuit 15 for driving the recording head 5 in order to produce a pattern of registration marks corresponding to the series of code bits c [n] on the record carrier 4 moving along the recording head 5 bring. The clock signals for the CIRC encoder 13 and the EFM modulator 14, which are in a fixed relationship to the recording speed, are also generated by the oscillator 6 and are supplied via signal lines 16 and 17 to the CIRC encoder 13 and the EFM modulator 14 The fixed relationship between the clock signals and the recording speed is chosen such that on the record carrier 4 the number of coded bits per unit length (recording speed) complies with the standard prescribed by the CD standard. The frequencies of the signals generated by the oscillator 6 can be set by the microcomputer 11 via a signal line 18, after they have been calculated by the microcomputer using the data on the conversion rules, for example by determining the number of information bits, or code bits that is issued per unit of time. On the record carrier 4, speed information is recorded which is indicative of the thus calculated setting of the oscillator 6 and thus indicative of the recording speed and the bit frequency of the series of information bits i [n] and series of code bits c [n]. After all, there is a fixed relationship between the bit frequencies of the information bits, the bit frequency of the code bit sequence and the recording speed. The velocity information is preferably recorded prior to the recording for the series of information bits i [n]. The speed information is recorded in a retrievable place on the record carrier 4, for example in a run-up track on the record carrier 4. To this end, the microcomputer 11 is provided with a suitable program, which extracts the speed information to be drawn from the conversion instructions entered via control panel 12 prior to recording. . Then, by the computer 11, a conventional positioning system for the write head 5, which system, for example, a motor 19 including a spindle 20, is positioned opposite the lead-in track, and at a nominal recording speed prescribed by the CD standard, the speed information, together with information indicative has been recorded in the run-up track for the conversion regulations. The speed information can be recorded separately. However, the rate information may also be included in the information about the conversion rules, as will be described in detail later. Then, by setting the oscillator 6, the recording speed is set according to the derived speed information. And the writing head 5 is positioned under the control of the microcomputer 11 opposite the track portion in which the sequence of code bits c [n] derived from the information signal Vi is to be recorded. After reaching this track section, recording is started under the control of the microcomputer 11. The embodiment shown in figure 1 has the advantage that it can be obtained from a standard CD recording device with the aid of adaptations that are easy to realize technically. By keeping the ratio between the frequency of the signal added to the phase detector 7 and clock frequencies of the CIRC encoder 13 and the EFM modulator 14 constant, the ratio between the recording speed and the bit frequencies of the bit series i [n] also remains constant. and c [n] constant. This means that the recording density on the record carrier remains within the standard prescribed by the CD standard, and is therefore legible. In addition, since information about the recording rate is recorded on the record carrier itself, the reading rate can be readily adjusted according to the recording rate upon reading, so that the bit rate of the information bit sequence on reading is equal to that on recording. This is particularly important if audio or video information is recorded, because for true transmission of this information it is necessary to keep the bit frequency the same during recording and reading.

Figure 2 shows an embodiment of a read-out device 30 according to the invention in which the read-out speed is set in accordance with the speed information recorded on the record carrier 4. The reading device 30 comprises drive means, for instance in the form of a motor 41 and turntable 42, for rotating the record carrier 4 about an axis 43. Opposite the rotating record carrier 4, an optical read head 44 of a conventional type is arranged, which is arranged by means of a positioning system comprising, for example, a motor 45 and spindle 46, can be moved radially with respect to the record carrier 4. A readout signal representing the readout code bit sequence c [n] is output from the readout head 44 and is fed to a conventional cascade circuit of an EFM demodulator 47 and a CIRC decoder 48, which converts readout code bit sequence c [n] in a conventional manner in the information bit sequence i [n]. The EFM demodulator 47 and the CIRC decoder 48 are controlled with clock signals cl1 and cl2 which are derived from the read-out signal by means of, for example, a phase-locked loop circuit 49. In the CIRC encoder 48, the information is temporarily stored in a buffer which is loaded at a rate determined by the clock signal cl2, and which buffer is read at a rate determined by each frequency of a clock signal cl3 which is received by an oscillator 50 cheerful. A signal Vg indicating the fill level of the buffer contained by the CIRC encoder 48 is output from the CIRC encoder 48 and applied to a motor control circuit 51 for the motor 41. The motor control circuit 51 controls the motor 41 such that the signal Vg indicated degree of filling remains essentially constant. Thus, the speed at which the record carrier is advanced along the reading cap 44 is controlled at a value fixed by the frequency of the clock signal cl3.

The reading device is furthermore provided with a control circuit, for example a microcomputer 52 for controlling the reading process. The microcomputer 52 is provided, inter alia, with an input for receiving the series information bits i [n] from the CIRC decoder 48. The series of information bits i [n] is also supplied to a reformer circuit 53, which converts the series of information bits into a different format, according to conversion rules supplied by the multiple computer 52 via a bus 54 to the reformatting circuit 53. The microcomputer 52 is loaded with a suitable program for controlling the readout. This program contains a step in which the readout speed is set to nominal speed by setting the frequency of the clock signal cl3 output by oscillator 50 via a signal line 55 to a value corresponding to the nominal speed. In addition, under the control of the microcomputer 52, the read head is positioned opposite the run-up track in a conventional manner. Subsequently, the address, the speed information and the conversion information of the signal to be read out are read from the lead-in track. Thereafter, the frequency of the clock signal cl3 is set to a value corresponding to the read out speed information, and the read out conversion information 53 is applied to the reformatting circuit 53. In addition, the read head under the control of the microcomputer 52 is positioned in a conventional manner opposite the track in which the information to be read is recorded, after which the reading of the desired information can commence. Since the read rate is set to the same value as the rate at which the information is recorded, the bit rate of the read out sequence of information bits is the same as that at the recording. In addition, because the series of information bits i [n] is reformatted according to the same conversion scripts, the format of the signal Vi 'at the output of the reformatting circuit 53 is the same as the signal Vi received at the recording.

Since the information can be recorded in a different format than that offered, the format used in the recording can be adapted to make more efficient use of the available recording capacity of the record carrier 4. This applies in particular if the information signal is drawn Vi is offered in a universally applicable digital audio interface format, such as the format described in the IEC-958 standard. For many applications, such a format contains a large number of bits that are not used. For example, in the. IEC format 24 bits reserved for each audio sample, while for most applications the number of bits per sample is significantly lower. Furthermore, the IEC format. in a number of subcode channels, which generally are not all used. Furthermore, it is sometimes desirable to add user information to the recorded information in a manner not provided for in the IEC format.

An example of the conversion from IEC format to a more efficient format for recording will be described below.

Figure 3 schematically shows a digitized stereo audio signal Vi, formatted according to the IEC-950 standard. In this format, the data signal Vi is divided into frames. Each frame contains a fixed number, in this case 2, of subframes 60 the length of 32 bits each, which subframes represent a corresponding pair of samples of a stereo audio signal. The number of frames to be transferred per second can be chosen according to the IEC standard between 32,000, 44,100 and 48,000 frames per second. Each subframe 60 includes a 4-bit (bit 0-3) synchronization portion 61 for synchronization, a 24-bit portion 62 (bit 4-27) for transmitting a digitized audio signal sample . The last 4 bits (bits 28-31) are intended for the transfer of four subcode signals V, U, C and P.

Now suppose that for the signal Vi the number of frames per second is 48,000. The number of bits per sample is 16, for which the bits 12-27 are used for the subcode frames. Furthermore, it only contains. subcode C-channel interesting information for the user. Furthermore, the user wishes to add three bits of user information to each sample when recording. In addition, the user wishes the information to be divided into blocks such that each block contains audio information for a time interval of 1/250 second. This means that each block contains 384 signal samples (two for each sample). There in it. subframe 60 uses only 16 of the 24 bits available for the transmission of a signal sample, only 16 bits need to be recorded for each signal sample. In addition, since only the C subcode channel in subframes 60 contains useful information for the user, only 1 subcode bit per signal sample need be recorded. Furthermore, 3 bits of user information must be transferred per signal sample, which means that 20 bits must be recorded per signal sample. This can be done by assembling bit groups of 20 bits each. Such a group is indicated in Fig. 3 with reference numeral 63. The bit group 63 comprises a portion of 16 bits corresponding to bits 12-27 of the subframe 60, a portion 65 corresponding to bit 30 of the subframe 60, and a portion 66 containing the 3-bit user information. The 20-bit groups 63 are grouped into blocks 67 of 384 groups, to which is additionally added a 14-byte group 68, which includes a synchronization group 69 and an address group 69a indicating the block number. Furthermore, the block 67 may include a second address group 69b, indicating where the conversion rules are stored which have been used in converting the signal Vi into the series of consecutive blocks 67. These conversion rules may, for example, be recorded in the lead-in track of the record carrier 4. together with a table of contents indicating the addresses of the various signals recorded on the record carrier.

Figure 4 gives an example of how information about the conversion regulations can be indicated. This information includes a protocol group 70, designated PR1, PR2 and PR3, for each of the three portions 64, 65 and 66 in the bit groups 63. Each protocol group contains a number of bytes which are divided into a number of groups 71, ..., 83. The group 71 (IN) indicates the beginning of the protocol group. Group 72 (x / y) denotes the sequence number (x) in a series (y) of protocol groups 70. For example, group 73 can be used to indicate whether to record the information in the lead-in area, program area, etc. of the record carrier. The group 74 (psc), by means of a code, indicates the type of data stored in the associated part in the 20-bit groups 63. For example, the code "MAIN" in protocol group PR1 indicates that it. section 64 of group 63 concerns main information. The code "SUB" in PR2 indicates that the associated section 65 is sub-information. The code "USER" in PR3 indicates that the associated portion 66 is additional user information. The group 75 (bytes / block) indicates the number of bytes contained by block 67. In this case, this number is 974. Groups 76 (start) and 77 (end) indicate the start address and the end address of the recorded signal to which the protocol group applies. The group 79 (I / O ID) indicates the type of format or interface device from which the relevant data originates in the associated parts of group 63. In the protocol group PR1 and PR2, the code "IEC" indicates that the data in groups 64 and 65 comes from a signal formatted according to the IEC standard. In protocol group PR3, the code "MEM" indicates that the data in part 66 comes from an internal memory. Groups 80 (LSB) and 81 (MSB) indicate which bits are used from the format specified in group 79 Group 82 (frame / sec) indicates the number of frames per second that comprise the format specified by group 79. Group 83 indicates the number of subframes (channels) per frame In the present case where the frames include stereo samples this number equals two.

As is apparent from the foregoing, the protocol groups 70 fully define the conversion rules for converting the information signal Vi into blocks 67. It will also be clear to those skilled in the art that numerous different transposition rules can be established by means of the protocol groups.

It is further noted that the invention is not limited to applications in which the signal is presented in IEC format, the invention is also applicable for other formats such as the SCSI or RS232 format. The information about the conversion rules can be supplied via the control panel 12 of the recording device 1 to the microcomputer 11, which then supplies this information to the reformatting circuit 10. The. however, it is also possible that the information about the conversion rules together with the signal Vi, for example in a subchannel of this signal Vi, is supplied directly to the reformatting circuit 10.

Fig. 5 shows an embodiment of the reformatting circuit 10. Herein is a user-type receiving circuit 90 which converts the signal Vi formatted according to the IEC-958 into arrays of 32-bit subframes which are loaded into a buffer memory 91. A microcomputer 92 is coupled to the buffer memory 91 via a bus for reading the buffer memory 91. Furthermore, the formatting circuit 10 comprises a second memory 93 which can be loaded via a bus 95 by the microcomputer 11 and which can be read via a bus 96 by the microcomputer 92 included by the reformatting circuit. A parallel-serial converter 97 is parallel-loadable through the bus 99 by the microcomputer 92. The serial output of the converter serves as the output of the reformatting circuit 10 for outputting the reformatted series of information bits i [n]. The clock signal for the parallel-serial converter 97 is derived by a control circuit 102 from a clock signal generated by the oscillator 6 which is applied to the control circuit via signal line 103. The operation of the reformatting circuit 10 is as follows: prior to recording, the microcomputer 11 supplies the information about the conversion rules, and optionally the memory 93 is loaded with the user information to be recorded along with the information contained by the signal Vi . In addition, the protocol groups 70 by which the conversion rules are recorded are recorded in a designated place on the record carrier, for example in the table of contents in the lead-in area of the record carrier. Then the recording speed is adjusted.

Then, the signal Vi is applied and the buffer memory 91 is loaded with the subframes 60. The stored subframes 60 are read by the microcomputer 92 in the order in which they are stored. In addition, the user information is retrieved from memory 93 in the desired order. From the retrieved subframes and the retrieved user information, the groups 63 are assembled and assembled into blocks 67 according to the received conversion rules. The information thus reformatted is fed bytes to the parallel-serial converter 97, which outputs the received information in synchronism with the clock signal received via signal line 103, after which the information bit sequence i [n] is converted into the code bit sequence c [n] which is recorded .

Figure 6 shows an embodiment of the reformatting circuit 53. The circuit 53 includes a buffer memory 110 for storing the series of information bits .i [n] outputted from the CIRC decoder 48. A microcomputer 111 is connected to the buffer memory 110 via a bus for the purpose of reading the buffer memory 110. The microcomputer 111 is also connected to the microcomputer 52 for the transfer of the information about conversion rules via the bus 54. Furthermore, the microcomputer 111 connected via a bus to a buffer memory 112 for the output of information to this buffer memory 112. A transmission circuit 113 is connected to this buffer memory 112 via a bus for reading out the buffer memory 112. The transmit circuit 113 is one of a user-type that converts information read from the buffer memory 112 into the signal Vi formatted in the IEC format. The transmission circuit 113 is controlled by a clock signal generated by an oscillator 114 with a frequency that is adjustable via a signal line 115 by the microcomputer 111. The operation of the reformatting circuit 53 is as follows: Before reading the record carrier 4 recorded information, the protocol groups 70 for the signal to be read are read at nominal read rate, and the microcomputer 111 is loaded with conversion rules established by the protocol groups, indicating how the flow of information bits i [n] is again in the format desired for output , in this case the IEC-958 format, can be converted. Thereafter, the reading speed and the frequency of the reading by the oscillator 114 are adjusted, and the reading of the information is started.

The series of information bits from the "CIRC" decoder are loaded into the buffer memory 110 during reading. The microcomputer 111 reads the information bits loaded into the buffer memory 110 bytes and converts this information about the conversion rules into subframes conforming to the IEC-958 standard. In addition, the bits of the user information are separated and output via a signal line 116. The subframes composed by the microcomputer 111 are transferred via the buffer memory 112 to the transmission circuit 113, which outputs the information synchronously with the clock signal generated by the oscillator 114.

In the previously described embodiment of the protocol groups 70, information about the rate at which the information is recorded is included. After all, by the groups 80 and 81 within the protocol groups PR1, PR2 and PR3, the number of bits of the groups 64, 65 and 66 becomes data, so that the total number of bits of the groups 63 is known. Furthermore, the total number of groups per unit time is known from groups 82 and 83. In the case shown, this number is equal to 96000. Furthermore, the number of bytes per block is known from group 75, in this case 974. Furthermore, the number of bytes used per sector for the "header" is always equal to 14. This means that per block 67 net 960 bytes are transferred. This corresponds to 768 20-bit groups 63. From this, the number of bit groups per second, and thus the number of blocks, is 67 per second. The bit frequency and thus the desired recording speed can again be calculated from the number of blocks 67 per second. In the above-described embodiment, the protocol groups are recorded separately from the other information. However, the protocol groups can also include the "Headers" 68 of the blocks. This can be done, for example, by reserving a number of byts in the "header" 68, for example 8 to alternately transfer a block number, a time code and a part of the protocol groups in time multiplex form.

In the foregoing, the recording speed has been increased in order to make it possible to record a signal with a bit frequency greater than that prescribed by the CD standard. However, instead of increasing the recording speed, it is also possible to convert the presented information signal into two or more sub-signals having a bit frequency equal to or less than the standard prescribed by the CD standard. The individual partial signals can then each be recorded on a separate record carrier by means of a separate recording device.

Figure 7 shows an embodiment of a recording device 120 for performing the above-described method. The recording apparatus comprises a conversion circuit 121 of a kind corresponding to the circuit shown in Figure 5, but which converts the information signal instead of an information bit sequence into two simultaneously generated bit sequences i1 [n] and i2 [n] with a bit frequency which preferably corresponds to the bit rate prescribed by the CD standard. The conversion circuit 121 may consist of an input buffer 126 to which the input signal Vi is applied. With the aid of a microcomputer 127, the input buffer is read out and converted according to certain conversion rules into two partial signals, which are fed byte-wise to two serial-parallel converters 128 and 129. Information series i1 [n] and i2 [n] are output from the outputs of the serial-parallel converters 128 and 129. The conversion rules can be supplied, for example, via a control panel 122 to a control unit, in the form of, for example, a microcomputer 123, which then carries out these conversion rules to the conversion circuit 121. Furthermore, the recording device 120 comprises two recording devices 1a and 1b which are of one type which corresponds to the recording device shown in figure 1, but whose recording speed is preferably set to a value corresponding to the CD standard. The conversion rules for converting the signal Vi to the information bit sequence i1 [n] can be indicated by protocol groups 70 in the manner shown in Figure 4. Similarly, the conversion rules for converting the signal Vi into the information bit sequence i2 [n] can be indicated. The conversion instructions indicated in this way are again recorded on the record carriers in a designated place. For this purpose, the microcomputer 124 is coupled via buses 124 and 125 to the microcomputers 11a and 11b of recording devices 1a and 1b, respectively. After the conversion rules have been recorded, the information bit series i1 [n] and i2 [n] are simultaneously recorded by recording device 1a and 1b, respectively. The information bit series i 1 [n] and Ï2 [n] are applied for this purpose to the CIRC encoders 13a and 13b of the recording devices 1a and 1b, respectively. The control of the recording is performed by microcomputers 11a and 11b, which are provided with the necessary control data for this purpose by the microcomputer 123.

Figure 8 shows an embodiment of a reading device 130 for reading the information recorded by recording device 120. The reading device 130 comprises two reading devices 30a and 30b of a kind corresponding to the reading devices 30 shown in Figure 2, but for which the reading speed is preferably set to a fixed value determined by the CD standard. The microcomputers 52a and 52b for controlling the readers 30a and 30b are coupled via a bus 131 to a control unit, for example a microcomputer 132. Furthermore, the outputs of the CIRC decoders 48a and 48b are coupled to the microcomputer 132 and a conversion circuit 133 Prior to reading the desired information, the information about the conversion rules is read by the readers 30a and 30b and supplied to the microcomputer 132. The microcomputer 132 passes this information to the conversion circuit 133, which is of a kind which is the supplied information bit series i1 [n] and i2 [n] converts to an information signal Vi 'in a manner inverse to the conversion performed by conversion circuit 121. Subsequently, the microcomputer 132 initiates the reading of the desired information via the bus 131 such that the bit sequences i1 [n] and Ï2 [n] are read in substantially the same time relationship as they are recorded. In order to compensate for possible deviations in the time relationship, the conversion circuit 133 can be provided with buffer memory 134 and 135. The deviations in the time relationship can be determined on the basis of the block numbers in the "headers" 68 of the blocker 67. When the blocks of the information bitstreams i1 [n] and i2 [n] are combined, blocks with the same block number are each retrieved from the buffer memories 134 and 135 by a microcomputer 136, which is included by the conversion circuit 133, and which is the one from the buffer memories 134 and 135 converts retrieved blocks according to the conversion instructions received from the microcomputer 132, and then supplies the converted information byte-wise to a parallel serial converter 137, the serial output of which serves as an output of the signal Vi '.

Claims (1)

Method for recording an information signal with a certain bit frequency, characterized in that, prior to recording, said information signal is converted into at least two information signals, each having a second bit frequency lower than the determined bit frequency, each of the latter information signals recorded by means of a separate recording device, which recording devices are suitable for recording information signals with a bit frequency which is equal to or higher than the second bit frequency, but which is smaller than the first determined bit frequency.