NL8900813A - QUICK-ACTING OUTPUT BUFFER. - Google Patents

Description

* V.0. 208ί "

Title: Fast acting output buffer «

The invention relates to information processing systems and more particularly to a fast-acting output buffer for use with an integrated circuit memory device.

5 Reference will now be made to Fig. 1.

As shown in Fig. 1, a conventional information processing system 1 uses a central processor unit 8 which supplies an address signal over an address rail 12 to a memory 4 to cause the memory 4 to output output information to an information rail 6 during an output interval. . Numerous methods have been used to increase the rate of information transfer within a conventional processing system, as shown in Fig. 1. However, many of these methods have generally led to changes in the system or memory architecture, as illustrated, for example, in U.S. Patents 4,589,020, 4,577,293, 4,692,901, 4,694,431. Other known approaches have included reformatting the output information using information shifting operations, referring, for example, to U.S. Patents 4,573,141 and 4,561,071.

Reference will now be made to Figure 2, which shows an integrated memory circuit 4, which is commonly referred to as a memory "picture". In a conventional system, information is transferred from a memory device such as the picture 4 using an output buffer 20 which causes a high or low voltage on an output line 46 to represent a "1" or "0" during the output interval 30. The output signal is supplied via a line 46 to an output pin 24 and from the pin 24 to an information rail and / or a processor unit.

A limitation imposed on the rate of information transfer from the memory device, such as the wafer 4, is in the period required 8900813.

-2- fv * to load the output line 46 to the required high or low voltage, more particularly in the worst case where the output information during adjacent output intervals is shifted by a full logic level (i.e. from "0" to "1" or from "1" to "0").

To accomplish a full logic swing from "O" to "1", a conventional fast-acting output buffer, such as that shown in FIG. 2, will more specifically output-line voltage from a low 0-volt state to shift a high 5-volt state over an interval of 5 ns, as shown in Figure 3.

Such a rapid shift causes strong noise in the power sources, potentially leading to information errors. Such problems will be aggravated as the load at the output line increases and the time to swing to full voltage decreases.

Various mechanisms have been used to increase the rate of information transfer in view of the output line-20 loading problem; however, these methods have not focused on optimizing the loading time of the output line itself.

For example, U.S. Patent No. 4,613,957 uses a voltage difference generator instead of a reference potential generator to detect whether an information signal exceeds or falls below a threshold, causing a sense amplifier to be immediately inverted to another logical level. As another example, US Patent 4,575,823 discloses an electrically modifiable non-volatile memory with capacitive members to allow rapid latching of a sense amplifier. The capacitive shutdown means utilize a buffer circuit, which can perform level shifting over a logic level during their recording operation.

Furthermore, it is known that the charging time of the output 8900813.

-3- LO line can be reduced by applying more power to the output line during the exit interval.

However, this approach increases the likelihood of power surges, which can lead to memory corruption and component melting.

Therefore, it is an object of the invention to provide an output buffer, which transmits information with great speed and reduced noise during full logic sweeps.

A further object of the invention is to provide a fast-acting output information buffer, which is intended to transfer information from either an integrated memory circuit or an integrated processor circuit.

A further object of the invention is to provide a fast information transfer without otherwise changing the normal information transfer during a conventional output interval.

A further object of the invention is to provide a method for reducing the load time of an output line during an output interval.

A further object of the invention is to provide the method of increasing the rate of information transfer while minimizing the need for additional power during the output interval and the risk of exposure of an integrated circuit to high power.

The invention is useful in a fast-acting information processing system that includes an output line driven to a high voltage or low voltage to represent a logic "1" or "0" as output information during an output interval. According to the invention, the line is mid-balanced between the high and low voltage levels during a pre-equilibrium interval, which ends just before the next output interval. In this way, the system achieves the required logic swing on the output line during the output interval at a higher speed and with less 8300813.

-4- * noise. The pre-balance circuits are located on the plate at a distance from the memory core and at the output pins to further minimize power hazards.

The invention will be explained in more detail below with reference to the drawing. In the drawing: Fig. 1 shows a block diagram of a conventional information processing system; FIG. 2 is a schematic diagram of an information output circuit 10 for a conventional memory card of a known type; FIG. 3 is a waveform diagram of the voltage on the output line during the start of an output interval; Fig. 4 is a diagram of an information output circuit according to an embodiment according to the invention; Fig. 5 shows a diagram of a voltage equalization circuit which is used according to the invention; Fig. 6 is a time diagram to illustrate the relative tempering of the pre-balance interval according to the invention; Fig. 7 is a diagram showing different output line voltages during the initial part of an output interval according to the prior art and according to the invention; Fig. 8 is a diagram of another embodiment according to the invention; FIG. 9 is a timing chart of pre-balance control signals used in the embodiment of the invention shown in FIG. 8; Fig. 10 is a simple diagram showing the use of a delay control circuit for generating pre-balance control signals according to the invention; Fig. 11 is a partial schematic of another embodiment of the invention; and Fig. 12 shows a diagram of another embodiment according to the invention.

8900313.

4> * -5-

Reference is made to Fig. 1. Fig. 1 shows a conventional information processing system 1 of known type. In the information processing system 1 there is a central processor unit 8 which is connected by a number of rails, including an image selector rail 10, an address rail 12 and an information rail 6, to a number of memory plates 4, 4A, 4B and 4C.

For the information processing system shown in FIG. 1, an image select signal will initially be applied to image 10 select input of the memory image 4 and an address signal will be applied to an address input pin of the image 4. As is known, the memory tag uses the address signal to determine the location in the memory core from which the output information is to be supplied and will then output the output information from an input / output pin.

Reference is now made to FIG. 2. FIG. 2 is a diagram of a memory plate 4 with an output information buffer 20 to drive an output line 46 in response to a signal consisting of a digital 1 or a digital 0 from an address in the memory core to a high or low voltage.

Fig. 2 shows an INFORMATION input line from the core memory (not shown) coupled to the gate electrode of a transistor 1.4 and an inverse INFORMATION line -25 from the memory core (not shown) coupled to the gate electrode of a transistor 1.4. transistor 16. The drain electrode of transistor 14 is connected to a reference voltage which is 5 volts at the circuit shown.

The supply electrode of the transistor 16 is grounded. The input electrode of the transistor 14 is coupled to the output electrode of the transistor 16 and to an output line 46. The output line 46 has an output line voltage, which is representative of a digital "1" or "0", which during a output interval to the output pin 24 is applied.

During operation, the chain according to Fig. 2 functions as 8900813.

* · -6- follows. A logic 1 from the memory core causes a voltage across the INFORMATION line to be applied to the gate of the transistor 14 and cause the inverse INFORMATION line from the memory core to the gate of the transistor 16 to remain inactive. Therefore, the voltage on the gate of transistor 14 will cause the reference voltage (5 volts) to be applied to line 46. Since the inverse INFORMATION line to the gate electrode of the transistor 16 is inactive, no charge will flow across the transistor 16 to ground. Therefore, when a 1-digit digital signal is supplied to the memory, the output line 46 will be driven to 5 volts, thereby representing a digital "1" on the output pin 42.

On the other hand, when a digital core is supplied by the memory core, the inverse INFORMATION line will become active and supply a voltage to the gate of the transistor 16, and the INFORMATION line at the gate of the transistor 14 will become inactive. In this case, the voltage on line 46 across transistor 16 will be applied to ground 20, so that no voltage will be applied to output pin 24.

Reference is now made to FIG. 3. FIG. 3 shows the voltage on output line 46 as it swings from a 0 level to a 5 volt level during the start of an output interval. More specifically, as indicated in Figure 3, voltage swing occurs over an interval of 5 nanoseconds. Due to the steep and fast shift required from 0 volts to 5 volts, the sweep will cause a lot of noise, increasing the probability of a perceived information error.

Reference is now made to FIG. 4. FIG. 4 is a schematic of an embodiment of the invention. Fig. 4 shows an output buffer 2, which includes a first transistor 38 with a drain electrode connected to a reference voltage of 5 volts, and a transistor 36 with a supply electrode grounded, as in the prior art 8900813.

The circuit of FIG. 2. The supply electrode of the transistor 38 is coupled to the drain electrode of the transistor 36 and to the output line 46. An INFORMATION line extends from the memory core to the gate electrode of the transistor 38 and an inverse INFORMATION line extends from the memory core to the gate electrode of the transistor 36. A drain electrode of a transistor 32 is coupled to the INFORMATION line and the supply electrode is grounded. A transistor 34 has a drain electrode coupled to the inverse INFORMATION line and a supply electrode grounded. A clock type pre-balance control signal, Φ, is applied to the gate electrode of transistors 32 and 34.

Still referring to FIG. 4, the output line 46 has an output pin 24 coupled to the output end of the line. The transducer 40 of the transistor 40 is coupled to the output line 46 and the supply electrode is coupled to an equalizing circuit 12. The equalizing circuit 12 comprises a sense amplifier 42. The equalizing circuit 12 serves to provide an equalizing voltage of 2.5 volts across the transistor 40 at the output line during a pre-balance interval in response to the control signal i.

The circuit of Figure 4 operates as follows. During an output interval, the INFORMATION line or the inverse INFORMATION line from the memory core will supply a voltage to the gate electrode of either transistor 36 or 38 depending on the logic value of the information from the memory.

In case the logic value is equal to 1, a voltage is applied to the gate of transistor 38 and no voltage is applied across the inverse INFORMATION line to gate of transistor 36. Consequently, a voltage of 5 volts from the 5 volt reference source across the transistor 38 to the output information line 46 and to the output pin 24 to simulate a logic 1 for the output interval. In the event that the memory provides a logic 0, the 8900813 receives.

The gate electrode of the transistor 38 has no voltage across the INFORMATION line from the memory core, but a voltage across the inverse INFORMATION line is applied to the gate electrode of the transistor 36. As a result, a voltage 5 on line 46 across transistor 36 will be applied to ground to mimic an "0" information output for the output interval.

The operation of the control signal φ according to the invention will now be explained.

The control signal φ serves to provide a mechanism for pre-balancing the voltage on the information line 46 during the pre-balance interval at the level of 2.5 volts, so that the output line 46 does not travel the entire distance from a 15 during an output interval. level from 0 volts to a level of 5 volts need to be changed in case of a change in the output information from a 0 to a logic 1, and vice versa. Therefore, the control signal φ from a control circuit is applied to the gates of transistors 32, 34 and 40 during a pre-balance interval. When the control signal φ is applied to the gate electrode of the transistor 32, a voltage on the INFORMATION line across the transistor 32 will be grounded, thereby preventing the transistor 38 from applying a voltage to the line 46. Similarly, when the control signal φ is applied to the gate electrode of transistor 34, a voltage on the inverse INFORMATION line will be applied to ground, thereby preventing transistor 36 from grounding line 46. Therefore, during an initial period of 30 the pre-balance interval, the voltage on line 46 floats at approximately the last output level until an equalization voltage is applied through transistor 40. The control signal φ is applied to the gate of transistor 40 to cause an equalization voltage to be applied from equalizer circuit 12 across transistor 40 to output line 46. Consequently, the 8900813. " -9- voltage driven from either the 0-volt level or 5 volts to 2.5 volts during the pre-balance period. It may seem that this method presents a difficulty in the case where the information for the next output interval turns out to be the same as the information for the previous output interval except that the speed of conventional information output systems is based on the worst case, with a full logic swing between successive output intervals. In the worst case, such as with a swing from "0" to "1", the circuit of the invention pre-balances the output line at a voltage midway between the high and low output line voltages, so that only half of the full charge, which is required to flow during the exit interval.

As will be discussed in more detail below, the pre-balance interval is selected to begin upon receipt of an address signal for the next output signal and to end before the start of the next output interval.

The invention takes advantage of the fact that towards the end of a current output interval, the output information value is already established in a receiving unit, such as the central processor unit.

Reference is now made to FIG. 5. FIG. 5 shows an equalizing circuit 12 used to provide a constant equalizing voltage across transistor 40 to output line 46. Equalizing circuit 12 includes a sense amplifier 42 having a positive input and a negative input. The supply electrode of transistor 40 is coupled to the negative input of the sense amplifier 42 over an input line. A reference voltage is applied to the positive input of the sense amplifier 42 over a reference voltage line. The supply electrode of the transistor 52 is coupled to the reference voltage line.

A transistor 54 is also shown, the drain electrode of which is coupled to the supply electrode of transistor 52 8900 813 4 * -10. The drain of the transistor 52 is coupled to a reference voltage of 5 volts and also to the gate of the transistor 52. The drain of the transistor 54 is coupled to the gate of the transistor 54. The supply electrode of transistor 54 is grounded. One output of the sense amplifier 42 is connected to the gate of the transistor 48 and the second output to the gate of the transistor 50.

The drain of the transistor 48 is coupled to a power supply (in this case 5 volts) and the supply of the transistor 48 is coupled to the drain of the transistor 50. The supply electrode of the transistor 50 is grounded. The supply electrode of the transistor 48 and the drain electrode of the transistor 50 are coupled via the input line to the negative input of the sense amplifier 42.

During operation, within the equalizing circuit 12 shown in FIG. 5, the sense amplifier 42 adjusts the difference between its positive and negative input signals 20 to provide a constant voltage of 2.5 volts across transistor 40 during a pre-balance interval according to the invention. to provide. The circuit in FIG. 5 is illustrative only and other circuits may be used in accordance with the invention which are capable of supplying a voltage of 2.5 volts during the pre-balance interval.

Reference is now made to FIG. 6. FIG. 6 shows the timing for various steps in processing an output information request in a memory chain and more particularly shows the pre-balance interval relative to other output events. As indicated in Fig. 6, during an initial period, an address signal from, for example, the central information processing unit is received on an address pin of the memory tag. The address signal is received during an initial interval 35 which is conventionally determined as an "address transition detection" (ATD) signal interval, which in Fig. 6 is 89008) 3.

-11- shown as the interval from T1 to T2. Upon receipt of the ATD signal, the address is inserted into the memory core, which takes a period of T2 to some time ending before the next output interval. Once the information is found, the information is output as output information from the memory core during an output interval, which interval as indicated in Fig. 6 starts at time T5. For a typical system, the time from T1 to T5 records the design considerations. The interval 0th from T1 to T5 represents the time during which the memory chain must receive the address signal, receive the output information from the memory core, and be ready to supply the output information from the output pin to the output information rail.

As shown in Fig. 6, the pre-balance interval is selected to start after receiving the address signal and to end just before the start of the next output interval.

Reference is now made to FIG. 7. FIG. 7 is a diagram for the output line voltage at a number of pre-balance scenarios. Line 110 represents an output line voltage representative of a logic 1 during an output interval. Line 120 represents an output line voltage representative of a logic 0 during the same interval. At time T3 in Figure 7, the pre-balance interval begins and the voltage on line 46 is driven through the voltage equalization circuit to 2.5 volts (line 200). This result occurs regardless of whether or not the voltage on line 46 is previously represented -30 by a 1-level logic level, as shown by line 110, or a 0-level logic level, as suggested by line 120.

In the prior art, if the voltage on the output line was representative of 0 i.e. 35 was at 0 volts or a low voltage level, and the following output information to be presented would be & 9 0 0 813 t -12- equals 1, the output line from O volts to 5 volts, more specifically over an interval of 5 nanosec. as represented by the line 170. Lines 130, 140 and 150 and 160 represent different output line voltage scenarios according to the invention. Line 130 sets the drive of voltage on line 46 from the pre-balance voltage level proposed by line 200 to a full logic 1 voltage level in 2.5 nanoseconds. As it turns out, this approaches the prior art drive ramp but the logic 1 level is obtained in half the time. If the full 5 nanosec. required to drive the line voltage from the pre-balance voltage to the full level of 5 volts, line 140 shows that a much more gradual slope is possible, thereby reducing noise, slope speed, and information error. Lines 150 and 160 show the results of lines 130 and 140 but represent driving the line voltage from the pre-balance voltage to 0 volts during an output interval.

Reference is now made to FIG. 8. FIG. 8 shows another embodiment of the invention similar to that shown in FIG. 4, except that other control signals are used to control the gates of transistors 32, 34 and 40. In Fig. 8, a first control signal φ 1 is applied to the gate electrode of transistors 32 and 34 throughout the pre-balance interval. A second control signal φ 2 is applied to the gate electrode of the equalizing transistor 40 during a lower portion of the pre-balance interval. During the pre-balance interval, the voltage is first applied to the gate electrode of transistors 32 and 34 in order to cause the control signal φ 1 to be any voltage on the INFORMATION line and the inverse INFORMATION line is coupled to ground.

Therefore, for an initial period during the pre-balance interval, the voltage on line 46 will be at 89 00 813.

-13- value during the applicable output interval seven.

Thereafter, the control signal φ 2 is applied to the gate electrode of the transistor 40 in order to apply an equalizing voltage to the line 46 during the pre-balance interval. The control signal φ2 is applied to the gate electrode of transistor 40 during a control interval, which expires just before the end of the control interval of φ1, so that the equalizing circuit is turned off just before the transistors 32 and 34 are turned off. line 46 is isolated.

Fig. 9 is a generalized diagram showing the time relationship between the control signals φΐ andφ 2. The timing shown in FIG. 9 further prevents an inadvertent coupling of the equalizing voltage to the output line when the line is charged or grounded by transistors 36 and 38.

Reference is now made to FIG. 10. FIG. 10 is a block diagram of a simple mechanism for generating the pre-balance control signals to be used according to the invention. Fig. 6 shows that the ATD signal has a measurable duration and predetermined time relationship to the start of the output interval. Therefore, it is possible to delay the ATD signal in the control circuit 60 during predetermined periods to obtain the output control signals φ, φ1 and φ 2.

Reference is now made to FIG. 11. FIG. 11 shows an information output system 60 provided with a memory for receiving an address signal. The memory provides as an output signal an information memory signal which, depending on the information in the memory, is a www or "0". The address signal is also received by a control circuit which delays the signal to generate the control signal φΐ. Fig. 11 also shows two circuits 92 and 94, which provide a voltage across the INFORMATION line and the inverse INFORMATION line depending on 8900813.

-14- the logical output signal (information memories) from the memory core. In case the logical output signal (information memory) is 0, the circuit 92 supplies a high voltage to the inverse INFORMATION line. In the event that the logic output signal is 1, the circuit 94 supplies a high voltage on the INFORMATION line. The circuit 92 comprises a reference voltage of 5 volts, which supply electrodes of transistor 70 with a p-channel are supplied. The gate electrode of the transistor 70 is coupled to the memory and the drain electrode is coupled to the drain electrodes of the transistor 72. The transistor 72 is connected to the ground electrode and the gate electrode is also connected to the memory. The drain of the transistor 70 and the drain of the transistor 72 are coupled to the inverse INFORMATION line. In the circuit 94 of a p-channel transistor 80, a supply electrode is connected to a reference voltage of 5 volts and the gate electrode is coupled to a memory. The drain of the transistor 80 is coupled to the drain of the transistor 82. The supply electrode of the transistor 82 is grounded and the gate electrode of the inverter transistor 82 is also coupled to the memory. The drain of transistor 80 is coupled to the INFORMATION line.

Referring still to Figure 11, it shows two pre-balance circuits according to another embodiment of the invention. As shown in FIG. 11, it contains a first front balance circuit 96 included in the inverse INFORMATION line, and a second front balance circuit 98 included in the INFORMATION line. The circuit 96 30 consists of a transistor whose supply electrode is coupled to the drain electrode of transistor 70 and a drain electrode coupled to the output buffer over the inverse INFORMATION line. A control signal φ1 is applied through an inverter 74 to the gate of transistor 76. In the circuit 98 of a transistor 86, the supply electrode is coupled to the drain electrode of the 8900 & 13. -15 transistor 80, and the drain electrode is coupled to an output buffer over the INFORMATION line. A control signal Φ 1 is applied via an inverter 84 to the gate electrode of transistor 86. During operation, the 5 chains 96 and 98 deactivate the INFORMATION line and inverse INFORMATION line during the pre-balance interval when the control signal Φ 1 is active. The output buffer is connected to an output pin via an output line. The output buffer and circuits 92, 94, 96 and 98 should be located as close as possible to the output pin and as far away from the memory core as possible.

Reference is now made to Fig. 12, which shows another embodiment of a pre-balance characteristic output circuit 3 according to the invention. In the output circuit 3, the output signal from the memory core and the control signals are passed through logic circuits to control the voltage on the INFORMATION line and inverse INFORMATION line during pre-balance intervals. Both the INFORMATION and the inverse INFORMATION line are inactivated if Φ 1 is active 20 because the input signals to AND gates 220 and 230 from inverters 260 and 270 are set to 0 in this case. The INFORMATION line will also be inactive if the core output signal is equal to 0 and the inverse INFORMATION line will be inactive if the core output signal is equal to 1.

The above-described embodiments of the invention, which can be used as an output buffer, should be physically positioned as close to the output pin as possible on a memory card, for example, in order to further reduce the potential hazards to the memory core caused by energy bursts.

It is possible according to the invention to apply these to chains other than integrated circuits and integrated circuit elements other than memory plates, for example at chains, which transfer information from the central processor unit. In addition, the pre-balance control signals relative to output events other than addressing can be defined depending on the output environment.

8900813.

Claims (7)

A method of providing a fast digital information output, characterized in that an output line is driven to a low voltage for representing a digital 0 and to a high voltage for representing a digital 1 during output intervals , and the output line is driven to a voltage between these high and low voltages during a pre-balance interval preceding each output interval. 2. Fast-acting information output buffer characterized by an output line, means for driving the output line to a low voltage during output intervals to represent a digital 0, means for driving the output line to a high voltage during output intervals to represent a digital 1 and means for driving the output line to a predetermined voltage between the high voltage and the low voltage during the pre-balance interval preceding each output interval. 3. Information output circuit characterized by an output line, means for providing a 1 or 0-20 signal for indicating a digital output signal during an output interval, first circuit means for supplying the output line during output intervals where said signal is 1 to a high voltage driving, second circuit means for driving the output line to a low voltage during output intervals where said signal is 0, means for inactivating the first and second chains during pre-balance intervals preceding each output interval, and means for the output line drift during pre-balance intervals to a voltage which is approximately midway between the high and low voltages. 4. Fast-acting system for providing an output information characterized by circuit means to provide digital 1 and 0 signals for output information 8900813. -18- during output intervals, a first transistor connected to a reference voltage and an output line is connected, a second transistor, which is grounded and connected to the output line, the output line being coupled between the first transistor and the second transistor, the first and second transistors each including a gate electrode , first means for applying a voltage to the gate of the first transistor when the digital value is 1 to drive the output line to a high voltage, second means for applying a voltage to the gate of the second transistor when the digital value 0 in order to drive the output line to a low voltage is first means around said first inactivate driving means 15 during the pre-balance interval preceding each output interval, second means to inactivate the second driving means during the pre-balance intervals, and means to drive the output line to a predetermined voltage during the pre-balance intervals in order to drive the speed of the output line to increase the high and low voltages during the output intervals. 5. Information processing system for supplying output information during an output interval in response to an address signal supplied to the system, characterized by a memory for supplying a digital signal; to indicate the output information, upon receipt of the address signal, a first circuit which is coupled to the memory to generate a first signal, a second circuit, which, with an output interval 30 at which the logic value is equal to "1", the memory is coupled to generate the first signal during an output interval at which the logic value is "0", the first circuit generating a second signal when the logic value is "0" during a pre-balance interval, which pre-balance interval begins after 8900813. -19- reception of the address signal and ends before the start of the next output interval, and the second circuit generates the second signal when the logic value is n1 ", namely during the pre-balance interval. System according to claim 5, characterized by an output line, a third circuit, which is coupled to the output of the first chain to drive the output line to a high voltage in response to the first signal, a fourth circuit, which is connected to the output of the second circuit 10 is coupled to drive the output line in response to the first signal to a low voltage, with the third and fourth circuits being inactivated in response to the second signal, and a fifth circuit around the output line during the pre-balance interval predetermined tension. The fast-acting information output buffer of claim 2, wherein the output buffer and the output circuit are housed in an integrated circuit device having a memory core and an output terminal, the buffer 20 and the chain being located at the terminal and away from the memory core. 89 00 813.