NL8900469A - METHOD AND APPARATUS FOR APPLYING EPITAXIAL SILICONE AND SILICIDES - Google Patents

Description

METHOD AND APPARATUS FOR APPLYING EPITAXIAL SILICONE AND SILICIDES

The present invention relates to a method and apparatus according to resp. claims 1 and 2. The prior art known to the applicant comprises the following publications: - EP patent application no. 0070751; - EP patent application No. 0157052 - EP patent application No. 0133121 - EP patent application No. 0230652 - S.P. Murarka and D.B. Fraser: "Silicide formation in thin cosputtered (titanium + silicon) films on polycrystaillin silicon and SiC> 2" - T. Makino, N. Sato, M. Takeda, Y. Furumura, and K. Imaoka: "a stacked-source- drain mosfet using selective epitaxy "- TPHF Wendling, C. Wieczorek, K. Hieber: "selective CVD or TaSi2"

Because the substrate or wafer is not brought out of the vacuum, the contact resistance between silicide and epitaxial silicon can be reduced, most likely because the silicide is grown epitaxially on the epitaxial silicon.

The epitaxial silicon growth can be used for both MOS and bipolar integrated circuits; this concerns, for example, the SAC technique (self-aligned contact for applying an emitter contact of silicide, wherein the emitter consists of epitaxial silicon, or silicide contacts on epitaxially arranged source and drain regions.

Shallow and gradual junctions at a drain are possible to prevent hot-carrier effects and to counteract short-channel effects, such as occur with the so-called LDD technique. With SSD technology, phosphorus (P) and arsenic (As) can be combined.

Further advantages include the possibilities for three-dimensional integration, better planarization, solving the so-called thermal mismatch, an overall reduction in the process temperature and obtaining a higher aspect ratio through selective growth.

The present invention is schematically illustrated in the attached figure. Wafers can get into a first vacuum 2 one by one or in batches via a lock 1, after which they can be introduced into a reactor 3 one by one or in batches via a transport mechanism (not shown) for applying an epitaxial silicon layer. The wafers are then introduced one by one, for example by means of so-called frog arms rotatably arranged in space 2, into a reactor 4 for applying silicides.

If necessary, wafers can be reacted in the reactors 3 resp. 4 or subsequently be brought into a cleaning space 5 also connected to the vacuum space 2.

The following specifications apply to the reactor 3 for applying an epitaxial silicon layer: maximum temperature: 1050 ° C adjustable temperature range: 650eC - 1050 ° C adjustable pressure range: 0.05 - 50 For temperature uniformity on the wafer (s): ± 5 ° C in -situ plasma and / or NP3 cleaning: optional at 800 ° C: 10-6 Torr background pressure at 1000 ° C: 10 "3 Torr maximum leak at 25 ° C: 5 10-6 mbar I / sec 'gases (max. mass -flow controller flow rates): HCI (2slm),

SiH2Cl2 (500 scan), H2 / N2 (5slm),

SiH4 (500 sccm), 2 dopant / H2 lines total gas flows at process pressure: 0.2-1 sim at 0.05 - 0.1

Torr 2 sim at 1 Torr ports: sure port for mass spectrometer desired deposited layer thicknesses: 0.1 - 1 ym

The following conditions apply to the reactor 4 for applying silicides:

Nature of the module: -LPCVD

furnace or RTP reactor (single-wafer) source provided for metal precursor (W and

Co) maximum temperature: 1000 ° C adjustable temperature range: 150-900 ° C temperature uniformity wafer: 5 ° C in situ plasma cleaning and / or NF3 max.room wall temperature: 150 ° C background pressure: 25 ° C: 10-7 mbar 800 ° C : 10 "6 mbar 1000 ° C 10-3 mbar maximum leak at 25 ° C: 5xl0-6 mbar / sec gases and gas pipes (flow rates to be determined): - in situ cleaning: NF3 pipe provided (option) - heated pipe for metal precursor - non-corrosive gases: 4 pipes (SiH ^^ / Ar and 1 reserve) - 2 pipes for corrosive gases total gas flow at process pressure: - o.05 - 0.1 mbar: 0.2-1 sim lmbar: 2 sim flanges: - 3 blind; 1 optical window - all center axis flanges facing the wafer (s)

Finally, it is noted that the low temperatures are particularly suitable for (further) reducing the size of an integrated circuit.

Claims (3)

A method for applying epitaxial silicon layers and silicide layers, on a substrate or waver, wherein the substrate is placed in a first vacuum space; - the substrate under vacuum in a device for also applying epitaxial layers at low temperature (less than 1000 ° C) under vacuum; the substrate is brought from this device under vacuum, e.g., via the first vacuum space, to a device for the selective application of silicide layer, e.g. an LPCVD device therefor. Device for carrying out the method according to claim 1. Apparatus according to claim 2, wherein an apparatus for cleaning a substrate is connected to the first vacuum space via a vacuum channel, so that a substrate can be transferred to this cleaning space under vacuum.