NL8800449A - Transmitting or recording high definition TV signal - operating on video signal with control of spatial and or temporal consistency of image produced - Google Patents

Abstract

A TV signal to be supplied to the channel is created in accordance with one of a number of possible operations on the video signal providing mutually different distributions of spatial and/or temporal resolution. The selection includes consistency control of a selection relating to a part of an image compared to selections relating to spatially and/or temporally neighbouring parts of the image. A transmitting section has signal paths for at least three classes of motion, each with a preprocessing circuit (143, 145, 147) which are provided with circuits for individual sampling. The sampling circuits function in accordance with separate sampling patterns so that each preprocessing circuit gives a signal suitable for a display with an optimum distribution of resolution for the associated class of movement. Dependent on the class of movement determined, one fo the preprocessing circuits is coupled to a channel (170). The signal supplied to the channel gives a display with optimum resolution for the given class of motion. A high-definition receiving section has at least three signal paths with postprocessing circuits (43, 45, 47). The correct postprocessing circuit is selected in accordance with the class of motion.

Description

-IP

«PHN 12,440 1 N.V. Philips' Incandescent light factories in Eindhoven.

System for transmitting and receiving a television signal, as well as a transmitting part and a receiving part suitable for the system, a method for transmitting or storing the television signal, and a television receiver.

The invention relates to a system for transmitting and receiving a television signal over a channel, at least comprising a transmitting part and a receiving part coupled to the channel, which television signal comprises a video signal, wherein the transmitting part is provided with a sampling circuit, of a plurality of transmit signal paths coupled to respective signal inputs of a transmit output circuit and of a motion processing circuit comprising a motion detecting circuit for measuring the magnitude of motion in the video signal, the sampling circuit being of a type arranged to output a sampled frame of the video signal according to a frame shifted to frame to be output shifted sampling pattern, the motion processing circuit having an output coupled to a control signal input of the transmitter part output circuit coupled to the channel, the o Receiving section is provided with a plurality of receiving sub-signal paths coupled to the channel which are coupled to respective inputs of a receiving sub output circuit.

The invention also relates to a transmitting part and a receiving part suitable for the system.

The invention further relates to a method for transmitting or storing a television signal over a channel or on a storage medium, which television signal comprises a video signal, comprising sampling the video signal 25 shifted from one frame to be delivered to another to be delivered. sampling pattern, measuring the magnitude of the movement in the video signal for forming a television signal to be delivered to the channel or to be stored on the storage medium on the basis of this magnitude of the movement, from results of a number of possible operations on the video signal.

The invention also relates to a television receiver comprising means for generating a video signal to be displayed .8800449 PHN 12.440 2 from results of a number of possible operations on a received television signal, which television signal comprises a video signal.

Such a system, transmitting part and receiving part, such a method and such a television receiver are described in European patent application EP-A 0.252.563 (PHN 11.819). In the MAC-compatible television transmission system described herein, a broadband video signal from, for example, 1250 lines per image, interlaced between 2 frames at a frame frequency of, for example, 100 Hz, is sampled according to at least 4 different sources from a high-definition source. Grid to Grid sampling patterns shifted at least horizontally. MAC is an abbreviation of "Multiple Analog 15 Components" herein; in a MAC television transmission system, analog luminarity and chrominance signals are transmitted in time multiplex. With the aid of raster and / or line shifts it is possible to transfer the high definition video signal sampled in this way with the higher frame number and / or line number than the frame number or line number 20 of a normal definition MAC video signal compatible with the MAC television transmission system. to transmit the relatively narrow-band channel. Compatibility with the MAC television transmission system means that also MAC receivers without special facilities must be able to process a television signal broadcast by the transmitter part of the system. Here, signals suitable for a display with each time a different distribution of spatial and / or temporal resolution are presented at the signal inputs of the transmitter part output circuit.

In the receiving part, depending on a measured amount of movement in the video signal, a video signal obtained by spatial interpolation within one received frame can be mixed by the receiving part output circuit with a video signal obtained from a set of four consecutive received frames. . In the case of still images or images with little movement, the mixing result will mainly be determined by the video signal obtained by this set. Because all sampling values from four consecutive 8800449 PHN 12.440 3 frames can be used, a display with a maximum spatial resolution can be achieved, at the expense of a temporal resolution that is of no importance for still pictures and for pictures with little movement is of little importance. The temporal resolution is understood to mean a number of phases of movement per unit of time. With fast movements, on the other hand, the mixing result will mainly be determined by the video signal obtained by spatial interpolation, so that motion blur is avoided as much as possible. Since the sampling values of only one frame are now used, the spatial resolution here is less than with still images.

In this context, use is made of the fact that a spectator is less sensitive to shortcomings in the spatial resolution in the image during fast movements, so that space is created for a greater temporal resolution with a simultaneous decrease in the spatial resolution. It will be clear that in view of the limited bandwidth of the channel it is not possible to transmit a video signal suitable for a display with a large temporal and a large spatial resolution at the same time. It is possible, depending on the amount of movement in the images to be reproduced with the video signal, to always transmit a video signal suitable for reproduction with the most favorable combination of spatial and temporal resolution for the viewer.

The object of the invention is, firstly, to indicate a MAC-25 compatible system, in which system the various transmission sub-signal paths are better equipped for outputting a video signal suitable for a reproduction by the receiving section with an optimal distribution of temporal and / or spatial resolution for the given motion size.

The object of the invention is, secondly, to indicate a method for transmitting or storing the video signal, in which method the various operations on the video signal are more focused on the output or storage of a video signal suitable for a display with an optimum distribution of temporal and / or spatial resolution for the given motion size.

The object of the invention is, thirdly, to indicate a television receiver, wherein the various operations on the received .8800449 i PHN 12.440 4 video signal are more focused on the output of a video signal to be displayed suitable for a display with an optimal distribution. of temporal and / or spatial resolution.

According to the invention, a system of the type mentioned in the preamble is characterized in that the number of transmit partial signal paths is at least equal to three and the movement processing circuit is arranged for classifying the magnitude of the movement into a number of classes, which number of classes 10 is equal to the number of transmit signal paths, the transmit signal paths each comprising separate sampling circuits of said type, which sample according to separate sampling patterns, and an anti-fold back filter adapted to the sampling pattern of the sampling circuit in the transmit signal path, wherein the transmit output circuit is a changeover switch, wherein in the receive portion the number of receive subsignal paths is at least equal to three, where receive subsignal paths are arranged to combine mutually different numbers of received frames, and the receive suboutput circuit is an inverter.

According to the invention, a method of the type mentioned in the preamble is characterized in that the number of possible operations on the video signal is at least equal to three and the magnitude of the movement is classified in a number of classes, which number of classes is equal to the number of possible operations on the video signal, the various operations on the video signal comprising sampling the video signal according to separate sampling patterns as well as, prior to sampling, anti-fold-back filtering of the video signal adapted to the sampling pattern, and forming the television signal to be delivered to the channel or to be stored on the storage medium comprises selecting an operation on the video signal from the number of possible operations on the video signal.

To this end, a television receiver of the type mentioned in the preamble is characterized according to the invention in that the number of possible operations on the received video signal is at least equal to three and each operation corresponds to a different one each at .8800449 - ... .. ....................

4 ♦ PHN 12.440 5 at least three different sampling patterns according to which the received video signal may be sampled for transmission, operations comprising combining together different numbers of frames received and forming the video signal to be displayed comprising selecting an operation on the received video signal from the number of possible operations on the received video signal.

The transmitter part of the system according to the invention has separate transmitter part signal paths for at least three classes of motion sizes, each of which is provided with separate sampling circuits. These sampling circuits sample according to separate sampling patterns, so that each signal path outputs a signal suitable for display with an optimal distribution of temporal and / or spatial resolution for the corresponding class of motion sizes. The transmitter output circuit is a changeover switch in the system according to the invention. The signal to be delivered to the channel is therefore not compromised by a weighted averaging of a signal suitable for a display with a large temporal resolution and a signal suitable for a display with a large spatial resolution, but instead a signal suitable for a display with an optimal distribution of temporal and / or spatial resolution for the given class of motion sizes.

A normal definition MAC receiver is capable of displaying the compatible transmitted signal, but without taking advantage of the possibility of a higher spatial resolution display with little or no movement.

The high definition receiving portion of the system according to the invention also has at least three receiving portion-30 signal paths, each of which decodes a received signal in a manner associated with the respective receiving portion signal path. From signals output from these receive sub-signal paths, the receive sub output circuit selects the correct one. In the receiving part of the system according to the invention, with decreasing movement, a display with an increasing spatial resolution can be achieved, in that reception partial signal paths will then be successively selected by the receiving part output circuit which receive increasing numbers of 4 * 8800449% PHN 12,440 6. merge grids.

The invention will be further elucidated by way of non-limiting example with reference to the accompanying drawing, in which - figure 1A shows a block diagram of a transmitter part suitable for the system according to the invention, figure 1B shows a block diagram of a receiver part suitable for the system according to the invention, figure 2 shows a block diagram of a motion processing circuit 10 suitable for the transmitter part according to figure 1A, figures 3A, 3B1, 3B2 and 3C show block diagrams of pre-processing circuits suitable for the transmitter part according to figure 1A, figures 4A, 4B1, 4B2 and 4C illustrate the operation of sampling shifting circuits in the roughing circuits according to FIGS. 3A, 3B1, 3B2 and 3C, as well as backsliding circuits in a receiving section suitable for the system according to the invention, FIGS. 5A, 5B1, 5B2 and 5C sketching frequency responses of anti - fold-back filters in the roughing circuits according to figure 3A, 3B1, 3B2 and 3C, Figure 6 shows a block diagram of an intermediate processing circuit suitable for the receiving part according to Figure 1B, Figure 7 shows a block diagram of a high-resolution finishing circuit suitable for the receiving part according to Figure 1B, Figure 8 shows a block diagram of a mid-resolution finishing circuit suitable for the receiving part according to figure 1B, figure 9 shows a block diagram of a low-resolution finishing circuit suitable for the receiving part according to figure 30 1B, figure 10 shows a block diagram of a sampling pattern conversion circuit suitable for the finishing processes according to figures 7, 8 or 9 Figure 11 shows a block diagram of a motion compensated interpolation circuit suitable for use in series with the high-resolution post-processing circuit of Figure 7 or with the mid-resolution post-processing circuit of Figure 8, and. FIGS. 12A, 12B and 12C show a block diagram of a switchable delay member suitable for the motion compensated interpolation circuit of FIG. 11.

In Figure 1A, inputs of a

transmitter part a broadband video signal from a high definition camera is supplied. For example, the high definition video signal has a line number and a number of picture elements that can be distinguished per line, both of which are twice as high as the line number and the number of picture elements that can be distinguished per line from a normal definition signal, for example a MAC video signal . MAC is an abbreviation of "Multiple Analog Components" herein; in a MAC television transmission system, analog luminance and chrominance signals are transmitted in time-division multiplex. In order to be able to transmit the line number and the number of picture elements that can be distinguished per line from the high definition video signal over a relatively narrow-band channel that is suitable for a normal definition MAC video signal, the high definition signal in the transmitter must perform a number of operations described below. undergo. The R, G and 20 B inputs of the transmitter are connected to inputs 101R, 101G and 101B of an RGB-to-YUV converter 103, of which outputs 105U, 105V and 105Y via low-pass filters (LPF) 107U, 107V and 107Y with analog / digital (A / D) converters 109U, 109V and 109Y respectively are connected. Output signals at an output 25 111U of the A / D converter 1090 and at an output 111V of the A / D

converter 109V are combined with the aid of a switch 113 into a chrominance signal C at a terminal 115. An output 111Y of the A / D converter 109Y is connected to an input 123 of a memory 125, and to an input 127 of a motion processing circuit 129. The memory 125 compensates for a delay experienced by the signal in the motion processing circuit 129. An output 131 of the motion processing circuit 129 is connected to a control input 133 of a changeover switch 135, three inputs 137, 139 and 141 of which are connected to an output 149 of the memory 125 via respective preprocessing circuits 143, 145 and 147. An output 151 of the changeover switch 135 outputs a processed luminance signal Y 'and is connected to a first input 159 of a MAC coding circuit 163. A processed chrominance signal C 'is applied to a second input 161 of the MAC coding circuit 163 to a .8800449 * \ PHN 12,440. For example, this processed chrominance signal C 'can be obtained in the same way from the chrominance signal C as the processed luminance signal Y' is obtained from the luminance signal Y. However, based on the insight that the chrominance signal C is not suitable for a display with a spatial resolution as high as for which the luminance signal Y is suitable, it is also possible to use only two signal paths for the operations on the chrominance signal C. can be with a less complex realization of the chrominance signal processing circuits. A data output 117 of the motion processing circuit 129 is connected to an input 119 of a bit rate reduction circuit 121, an output 167 of which is connected to a data input 165 of the MAC encoding circuit 163. The data signal applied to the data input 165 of the MAC encoding circuit 163 is also referred to as the DATV signal. DATV is an abbreviation of "Digitally Assisted Television", which means that in addition to the video signal, an auxiliary signal (the DATV signal) is also transmitted, by means of which the high definition receiving part 20 decodes and processes the received television signal. The MAC encoding circuit 163 performs a number of operations known per se to encode the television signal according to a selected MAC television transmission standard and to be able to transmit over a channel. It should be noted here that the television signal to be output by the transmission part 25 of the system can be reproduced by an ordinary MAC receiver, and is thus compatible with a normal definition television signal according to the chosen MAC television transmission standard, but still is more broadband than this normal definition television signal. An output 169 of the MAC coding circuit 30 163 outputs a television signal to be transmitted to a channel 170, for which a satellite dish 171 is symbolically shown. Naturally, channels other than a satellite channel are also possible; the system according to the invention can for instance also be used as a storage and display system, wherein the channel is a storage medium.

35 The operation of the headpiece is as follows. Depending on an amount of motion to be determined by the motion processing circuit 129 in a high definition video signal supplied to the R, G and B inputs of the transmitter, 880 0449 ΡΗΝ ΡΗΝ 12,440 9, which is classified as (virtually) none, small or large motion, the changeover switch 135 selects which preprocessing circuit 143, 145 or 147 is coupled to channel 170. The preprocessing circuit 143 is hereby arranged for preprocessing a high definition video signal with (virtually) no motion, with a high resolution video signal at the input 137 from the inverter 135 is output which is suitable for a display with the highest possible spatial resolution, but with a low temporal resolution. The temporal resolution is hereby understood to mean a number of phases of movement per unit time. Because the transmitted spatial resolution of the high resolution video signal, as indicated by a solid line in Figure 5A, is twice that of a still normal definition video signal, for example, a MAC signal, as shown in Figure 5A with a dashed line , it follows that the temporal resolution should be twice as low. In Figure 5A, as in Figures 5B1, 5B2 and 5C, vertical vertical frequencies Fv are plotted, expressed in cph (Cycles per Picture Height) and horizontal horizontal frequencies Fh, expressed in cpw (Cycles per Picture Width). In other words, the spatial resolution of this high-resolution video signal transmitted with (virtually) no motion is therefore four times as high, and the temporal resolution is therefore four times as low as that of a frame of a normal definition video signal.

Conversely, the preprocessing circuit 147 is adapted to preprocess a high-definition, high-motion video signal, outputting a low-resolution video signal at input 141 of inverter 135 suitable for displaying a temporal resolution equal to that of a frame of the normal definition video signal, which, because the signal to be transmitted is transmitted over a MAC channel, means that, as indicated by a solid line in Figure 5C, the spatial resolution is also comparable to that of a frame of the normal definition video signal: with a lot of movement, the higher spatial resolution that the high definition video signal can offer cannot be used. This video signal transmitted at great motion will hereinafter be referred to as the low-resolution video signal.

.8800449 PHN 12.440 10

In between these two extremes lies the video signal which the pre-processing circuit 145 supplies to the input 139 of the change-over switch 135. The spatial resolution is twice as high, and the temporal resolution (thus) twice as low, as with a frame of a normal definition video signal. In other words, the spatial and temporal resolutions here are equal to those of an image of a still normal definition video signal. In an embodiment of the invention, depending on the spatial frequencies, it can be chosen whether the horizontal or vertical resolution of the transmitted medium resolution video signal will be twice as high as that of a frame of the normal definition video signal. See also figures 5B1 and 5B2. This video signal transmitted with slight movement will hereinafter be referred to as the mid-resolution video signal.

In an embodiment of the system according to the invention, the motion processing circuit 129 is provided with a motion estimator which determines the direction, size and uniformity of the motion. As mentioned, the spatial resolution of the video signal transmitted by the system decreases with increasing magnitude of the movement. In the case of uniform movement, a display with a higher spatial resolution than corresponding to the magnitude of the movement can nevertheless be achieved by using motion-compensated interpolation. The motion vector required for this must then be determined by the transmitter part and transmitted as auxiliary information in the DATV signal. Here, the motion processing circuit can distinguish, for example, between (virtually) no movement (for example less than 0.5 picture element per picture period), small movement (for example more than 0.5 but less than 1.5 picture elements per picture period), large movement (for example 30 more than 1.5 but less than 6 picture elements per picture period) and very large movement (e.g. more than 6 picture elements per picture period). With (virtually) no movement, the high-resolution roughing circuit 143 is switched on. With small and uniform movement, the high-resolution roughing circuit 143 is turned on, and with small and non-uniform movement, the mid-resolution roughing circuit 145 is turned on. With large and uniform movement, the mid-resolution roughing circuit 145 .8800449 ΡΗΝ 12,440 11 Λ or possibly even the high-resolution roughing circuit 143 is switched on, and with large and non-uniform movement the low-resolution roughing circuit 147 is switched on. At very high motion, regardless of the uniformity of motion, the low-resolution pre-processing circuit 147 is turned on.

In another embodiment of the system according to the invention, the system has a film mode, in which the low-resolution pre-processing circuit 147 is not switched on. This embodiment is based on the insight that the temporal resolution of film images is only equal to 24 phases of movement per second (whereby the light beam is interrupted once during the imaging of a film image to prevent annoying flicker effects), so that it makes little sense to use these film images. to transmit at a temporal resolution of 50 frames per second. Because the temporal resolution of film images is relatively low, the emphasis can therefore be placed on a higher spatial resolution. Thus, in this film mode, depending on the degree of movement, the motion processing circuit 129 selects only between the high resolution preprocessing circuit 143 and the medium resolution preprocessing circuit 145.

20

Figure 1B shows a receiving part suitable for the system according to the invention. It will be clear that the possibilities offered by the circuits included in the transmitting part can be made fruitful if the receiving part is provided with complementary circuits co-operating with the circuits included in the transmitting part. A satellite dish 71 receives the MAC-compatible television signal which is transmitted over channel 170 and is connected to an input 69 of a MAC decoding circuit 63, which has a video signal at a video output 61 and a DATV at a DATV output 65. signal. The MAC decoding circuit 63 performs various operations known per se necessary to receive and decode the MAC-compatible television signal output by the transmitting part of the system in accordance with the selected MAC television transmission standard. The DATV output 65 of the MAC decoding circuit 63 is connected to an input 67 of a bit rate recovery circuit 21 which performs the inverse operation of the operation performed by the bit rate reduction circuit 121 in the transmitter portion. 680 0446, ·, .4 12,440 12 figure 1Α. An output 19 of the bit rate recovery circuit 21 is connected to an input 17 of a DATV decoding circuit 29, which decodes the DATV signal and generates control signals therefrom which are output at an output 31 of the DATV decoding circuit 29. The output 31 of the DATV decoding circuit 29 is with a control input 27 of an intermediate processing circuit 25, with a control input 42 of a high-resolution post-processing circuit 43, with a control input 44 of a medium-resolution post-processing circuit 45, with a control input 46 of a low resolution post-processing circuit 47, and connected to a control input 33 of a change-over switch 35. The intermediate processing circuit 25 performs a number of operations common to video signals suitable for high, medium and low resolution display. The post-processing circuits 43, 45 and 47 perform the inverse of the operations performed by the pre-processing circuits 143, 145 and 147, respectively, in the transmitter part of Figure 1A. The video output 61 of the MAC decoding circuit 63 is connected to an input 23 of the intermediate processing circuit 25, an output 49 of which is connected via the post-processing circuits 43, 45 and 47 to inputs 37, 39 and 41 respectively of the inverter 20, of which an output 51 is connected to a display device 52.

In Figure 2, the motion processing circuit 129 from the transmitter part of Figure 1A is shown in greater detail, taking into account the aforementioned possibility of transmitting a video signal suitable for displaying a higher spatial resolution with uniform motion. The input 127 of the motion processing circuit 129 is connected to a first input 201 of a motion detector 203 and to an input 204 of a first frame memory 205. An output 206 of the first frame memory 205 is 30 to a second input 207 of the motion detector 203, and connected via a second frame memory 209 to a third input 211 of the motion detector 203. The motion detector 203 is of a type that distinguishes per picture element between (virtually) no movement (for instance less than 0.5 picture element per picture period), slight movement (for example more than 0.5 but less than 2 picture elements per picture period) and large motion (for example, more than 2 picture elements per picture period). The motion detector 203 has a first output 213 for outputting a signal indicating whether there is at least slight movement, and a second output 215 for outputting a signal indicating whether there is great motion. The motion detector 203 can be built up from a first and a second motion detector known per se, the first of which detects small movement and the second detects large movement. The first output 213 of the motion detector 203 is connected to a first input 217 of a pixel-to-block motion converter 219, a second input 221 of which is connected to the second output 215 of the motion detector 10 203. The picture element-to-block motion converter 219 converts a block of motion classifications per picture element into a motion classification per block of picture elements, for instance by comparing the number of classified picture elements moved by the first and second motion detectors per block with a first and a second threshold, respectively. . For example, the pixel-to-block motion converter 219 may be composed of separate pixel-to-block motion converters for each of the two input signals. Two outputs 223, 225 of the pixel-to-block motion converter 219 are connected via respective spatial consistency control circuits 227, 229 to respective inputs 231, 233 of a block motion control circuit 235. Spatial consistency control circuits 227 and 229 eliminate spatially isolated outcomes of the pixel-to-block motion converter 219; this is based on the understanding that it does not make sense if, for example, in the middle of an environment of blocks classified as stationary, a block were classified as fast moving. Signals at the outputs 223, 225 of the pixel-to-block motion converter 219 can only take two values, unmoved or motioned. Preferably, the spatial consistency control circuits 227, 229 operate on these signals as follows: 1. If the motion classification of a given block is unmoving and at least two of the motion classifications of the four horizontally or vertically adjacent blocks are motioned, then 35, the motion classification of the particular block must also be moved well.

2. If all eight surrounding blocks of the given block are unmoved .8800449 PHN 12.440 14, then the motion classification of this particular must also be unmoved.

3. If the motion rating of a given block is unmoved and the motion ratings of at least one pair of diagonally adjacent blocks are motioned, then the motion rating of the particular block must also be motioned.

The block motion control circuit 235 decides on the basis of output values of the spatial consistency control circuits 227 and 229 via which roughing circuit (143, 145 or 147 in Figure 1A) the present block should be processed. In the film mode described above, the block motion control circuit 235, as mentioned, selects only between the high resolution preprocessing circuit 143 and the medium resolution preprocessing circuit 145. Preferably, the block motion control circuit 235 operates according to the table below. The numbers in parentheses indicate the refresh time of the image information.

As explained above, high resolution preprocessing circuit 143 emphasizes high spatial resolution; the refresh time of the image information is therefore relatively long with this pre-processing circuit, for example 80 ms. Conversely, the low-resolution preprocessing circuit 147 emphasizes a large number of motion phases per second; the refresh time is therefore relatively short, for example 20 ms. Between these two extremes lies the refresh time associated with the mid-resolution preprocessing circuit 145, which may be, for example, 40 ms. Since the television signal to be output by the transmitter is compatible with the MAC-30 television signal, the frame frequency of the frames to be output is 50 Hz, but this does not necessarily mean that there is new image information every 20 ms. Thus, at a refresh time of 40 ms, it is possible to transmit a first half of each high definition frame to be transmitted into a first compatible frame to be output and a second half to be transmitted into a second compatible frame to be output.

.8800449 PHN 12.440 15

Movement decision Movement greater than 0.5 picture element per block per image period:

| YES | NO

5 ------------------------------------------------- ------------------------- movement greater than | YES {circuit 147 (20 ms) | circuit 147 (20 ms) 2 picture elements per I ---------------------------------------- -------------- image period | NOj circuit 145 (40 ms) | circuit 143 (80 ms) An output 236 of the block motion control circuit 235 is connected to an input 237 of a raster number controller 238. The decision of the block motion control circuit 235 is converted by the frame number controller 238 into a route of time-sequential blocks through the pre-processing circuits 143, 145 and 147. As will become apparent from the description below, for four temporally consecutive blocks are off four consecutive grids allow only the following 5 routes:

Route 1: all four blocks via the low resolution 20 pre-processing circuit 143;

Route 2: all four blocks via the mid-resolution preprocessing circuit 145;

Route 3: the first two blocks via the mid-resolution preprocessing circuit 145, the last two via the low-resolution preprocessing circuit 147;

Route 4: the first two blocks via the low-resolution preprocessing circuit 147, the last two via the mid-resolution preprocessing circuit 145;

Route 5: all four blocks via the low resolution 30 pre-processing circuit 147.

These routes can also be characterized by the refresh time of the image information. Characterized by a refresh time of 20, 40 or 80 ms, the routes are as follows: .8800449 ft PHN 12.440 16

Grid: 1234

Route 1: 80 80 80 80 5 Route 2: 40 40 40 40

Route 3: 40 40 20 20

Route 4: 20 20 40 40

Route 5: 20 20 20 20 10 It will be clear that if the image information of a high definition image is chosen to be "divided" over four compatible frames to be transmitted in order to obtain a display with the highest possible spatial resolution, this choice must also be maintained for four consecutive grid times. There is therefore only one route possible with blocks with a refresh time of 80 ms. Likewise, a choice to "divide" the image information of a high definition frame over two compatible frames to be transmitted must also be maintained for two consecutive frame times, so that blocks with a refresh time of 40 20 ms always occur in pairs, see routes 2, 3 and 4. It follows from the above that in principle a sixth route with change times of successively 20, 40, 40 and 20 is also possible. The inclusion of this route has been deliberately omitted because of the insight that it is of little use to briefly have a few blocks with a higher spatial resolution in a temporally successive series of blocks at a certain place in an image, so that it is preferable it is indicated that a greater number of movement phases per second can be transmitted.

The route decision by the frame number controller 238 according to the invention preferably involves the decisions of the block motion control circuit 235 of an interval of 80 ms, as well as of two previous and two subsequent frames of the interval of 80 ms, according to the following table, in which means that the value does not matter and "/ 20" means that the refresh time is not 20 ms, but 40 ms or 80 ms.

_____________: _ ·· .8800449 * * PHN 12,440 17

Block Motion Control Circuit Decision | New Grid: -10 1 2 3 4 5 6 | Decision Route 5/20/20 80 80 80 80/20/20 | 80-80-80-80 1 80 80 80 80 - 20 l 40-40-40-40 2 80 80 80 80 20 - | 40-40-40-40 2 20 80 80 80 80 - - | 40-40-40-40 2 10 20 - 80 80 80 80 - - | 40-40-40-40 2/20/20/20 40 - - | 40-40-40-40 2/20/20 40/20 - - j 40-40-40-40 2/20 40/20/20 - - | 40-40-40-40 2 15 - - 40/20/20/20 - - [40-40-40-40 2/20/20 20 - - V 40-40-20-20 3/20/20 20 - - - | 40-40-20-20 3 20 - - - 20/20/20 - - | 20-20-40-40 4 - 20 - / 20/20 - - | 20-20-40-40 4 - - - 20 - 20 - - | 20-20-20-20 5 20 20 - - - | 20-20-20-20 5 25 20 - - 20 - - | 20-20-20-20 5 - 20 - 20 - - - | 20-20-20-20 5

The above table is based on the previously mentioned understanding that it makes little sense to briefly have a few blocks with a higher spatial resolution in a given sequence of blocks at a given location in an image for a short time. be able to transmit a greater number of movement phases per second.

An output 239 of the frame number controller 238 is connected to an input 240 of a route consistency controller 241. The routes selected by the grid number controller 238 are viewed, and if necessary adjusted, by the route consistency controller 241 at spatial 8800449 PHN 12.440 18 and temporal consistency, so that illogical decisions are corrected. In the following explanation of the operation of the route consistency controller 241, the sequence is first spatial, then temporal. A reverse order or a composite algorithm is equally possible.

Around a block, the routes of the surrounding blocks are compared and in some cases the following modifications are made. The direction of these modifications is always such that as few annoying artifacts as possible are created.

10 This often means more preference for movement and less for spatial resolution. Modifications 1 through 4 below are performed sequentially in the following order.

1. If all eight surrounding blocks of a given block have an equal route, then the route of this particular block must be made equal.

2. Modification of an isolated 80 block: if the route of a given block is 1 (in four consecutive frames refresh time 80 20 ms), where the routes of the four horizontally and vertically neighboring blocks are all not equal to 1, then the route of the given block will become equal to 2 (in four consecutive frames refresh time 40 ms).

25 3. Modification of an isolated 20 block: 3.1 If the route of a given block is 4 (in two consecutive frames refresh time 20 ms and in the next two consecutive frames refresh time 40 race) and none of the surrounding blocks has this route 4 or route 5 (in four consecutive frames 30 refresh time 20 ms), then the route of the particular block must be equal to 2.

3.2 If the route of a given block is 3 (in two consecutive frames refresh time 40 ms and in the next two consecutive frames refresh time 20 ms) and none of the surrounding blocks 35 has this route 3 or route 5, then the route of the certain block will be equal to 2.

3.3 If the route of a given block is 5, where none of the. 880 044 9 * i PHN 12.440 19 surrounding blocks route 3 or route 4 or if this route has 5, the route of the determined block must become 2.

3.4 If the route of a particular block is 5, where none of the surrounding blocks have route 4 or this route 5 and at least 5 one surrounding block has route 3, then the route of the particular block must become 3.

3.5 If the route of a given block is 5, where none of the surrounding blocks has route 3 or this route 5 and at least one surrounding block has route 4, then the route of the 10 block must become 4.

4. Modification of an isolated 40 block: 4.1 If the route of a given block is 2, with none of the surrounding blocks having this route 2 or route 3 and at least 15 surrounding block having route 4, then the route of the given block becomes equal to 4.

4.2 If the route of a particular block is 2, with none of the surrounding blocks having this route 2 or route 4 and at least one surrounding block having route 3, then the route of the 20 block must become 3.

4.3 If the route of a given block is 2, with none of the surrounding blocks having this route 2 or Route 3 or Route 4 and at least three surrounding blocks having Route 5, then the route of the given block must become 5.

4.4 If the route of a particular block is 2, where none of the surrounding blocks have this route 2 or route 3 or route 4 and at most two surrounding blocks have route 5, the route of the particular block must become 1 .

4.5 If the route of a particular block is 3, with none of the 30 surrounding blocks having route 2 or this route 3, then the route of the particular block must become 5.

4.6 If the route of a particular block is 4, with none of the surrounding blocks having route 2 or this route 4, then the route of the particular block must become 5.

Following is a temporal consistency algorithm that considers three consecutive 80 ms periods of a block.

35 .8800449 PHN 12.440 20 4 1. If the routes of the previous and the following 80 ms periods are equal to 5, then the route of the current period must also be equal to 5.

5 2. Modification of temporally isolated route 1:

If the route of the current period is equal to 1 and the routes of the previous and subsequent 80 ms periods are not equal to 1, then the route of the current period must be equal to 2.

10 3. Modification of Temporally Isolated Route 2:

If the route of the current period is 2, where the route of the previous 80 ms period is 3 or 5 and the route of the next 80 ms period is 4 or 5, then the route of the current period becomes equal to 5.

15 4. Modification of temporally isolated route 3:

If the route of the current period is equal to 3 and the route of the previous 80 ms period is equal to 3, 4 or 5, then the route of the current period must be equal to 5.

5. Modification of Temporally Isolated Route 4:20 If the route of the current period equals 4 and the route of the next 80 ms period equals 3, 4 or 5, the current period route must be equal to 5.

An output 243 of the previously described route-25 consistency controller 241 is connected to the output 131 of the motion processing circuit 129 via a route decoding circuit 245. The output 243 of the route consistency controller 241 is also connected to a first input 247 of a DATV encoding circuit 249. The DATV encoding circuit 249 has a second input 251 for supplying a chrominance routing signal thereto, and an output 253 connected to the data output 117 of the motion processing circuit 129,

In Figures 3A, 3B1 / 3B2 and 3G, the roughing circuits 143, 145 and 147 of Figure 1A are shown in more detail. In the high-resolution pre-processing circuit 143 shown in Figure 3A, a switch 312 is connected to the output 149, 88 0 044 9 PHN 12.440 21 * of the memory 125, which in a first position connects to an input 301 of an image memory 303, in a middle position is not connected to anything and in a third position connects to an input 305 of an image memory 307. A switch 313 connects an input 5 315 of a two-dimensional filter 317 to an output 309 of the image memory 303 or to an output 311 of the image memory 309. An output 319 of the two-dimensional filter 317 is connected to an input 321 of a sampling and line shifting circuit 323, an output 325 of which is connected to the input 137 of the changeover switch 135 of Figure 1A. The drawn switches 312 and 313 can also be omitted if suitable read and write signals are applied to unsigned read and write signal inputs of the picture memories 303 and 307, whereby the same operation can be obtained.

As already mentioned, the high-resolution preprocessing circuit 143 is arranged to output a high-resolution video signal, that is, a video signal suitable for displaying the highest possible spatial resolution. To this end, the first two of each of eight consecutive frames, which together form a complete high-definition image, are written into the image memory 303 via the switch 312. Thereafter, the switch 312 is in the unconnected center position for the next two frames, which are not processed. The fifth and sixth frames are written into the image memory 307, and then the switch 312 is again in the disconnected center position for the next two frames. The switch 313 always connects one of the two image memories 303 or 307 to the two-dimensional spatial image filter 317, the frequency response of which is schematically shown by a solid line in Figure 5A. In Figure 5A, as in Figures 5B1, 5B2 and 5C, vertical vertical frequencies Fv 30 are plotted, expressed in cph (Cycles per Picture Height) and horizontal horizontal frequencies Fh, expressed in cpw (Cycles per Picture Width). By sampling and line shifting circuit 323, the two frames are sampled according to a sampling pattern shifted from frame to be transmitted, then samples of two lines each obtained thereby are pushed between each other to obtain channel 170 of FIG. 1A grids to be delivered which are applied to input 137 of inverter 135. 88 0 044 9 i PHN 12.440 22.

With reference to Figure 4A, the operation of the sampling and line shifting circuit 323 will be explained.

This figure consists of three columns L, M and R. In the left column L5 it is shown how a number of parts of successive camera-derived frames (hereinafter referred to as camera frames) drawn from one another are sampled. The samples are indicated by three-digit numbers, of which the left digit indicates the camera grid from which the sample originates, the middle 10 digit indicates the line from which the sample originates and the right digit indicates the position on the line from which the sample originates. is. This assumes that a high-definition camera frame counts twice as many lines and twice as many picture elements in a line as a frame to be transmitted, that the frame number of camera frames 15 and frames to be transmitted is the same and that both with camera frames and when transmitting grids an image is made up of two interlaced grids. At each grid, an intersection of a landscape and a standing line indicates the position of the first picture element on the first line. In the drawn situation, only the first image of two consecutive images is sampled. However, it is also possible to sample both images, replacing the numbers 113, 131, 153, 171, 224, 242, 264 and 282 in the left column L of figure 4A with 313, 331, 353, 371, 424 , 442, 464 and 482 respectively. With really still images, the result of both options will be the same, with slight movement the second option will give a slightly smoother display with a little more blur than the first option. The middle column M shows how the samples of these successively sampled camera frames are pushed between each other. In a normal definition 30 receiver, the transmitted frames will be displayed as received. In a high definition receiver, on the other hand, four received frames, as indicated in the right column R, are combined to obtain a high resolution signal. This merging can be done in two ways, namely by combining the last 35 four frames received once per frame period and displaying the result obtained, or by combining the last four frames received every four frame periods and the result obtained .880 0449 PHN 12.440 23 over four grid periods. With completely still images there is of course no difference between the results of both methods, but with small movement the first method will lead to a smooth result with a small motion blur, and the second method to a result without motion blur, but with a slightly shaky representation of the movement. Irrespective of which of these joining methods is used, interpolation allows the still missing samples to be obtained. This can be done, for example, by supplementing the grating obtained in the assembly 10 in the right column R with samples of zero value at the missing places, and supplying the supplemented grating to the same two-dimensional low-pass filter as the two-dimensional low-pass filter 317 in the transmitter part of the figure 1A.

Fig. 3B1 shows the mid-resolution preprocessing circuit 145 of Fig. 1A, in which a switch 342 is connected to the output 149 of the memory 125 of Fig. 1A, which in a first position connects to an input 331 of an image memory 333 and in a second position connects to an input 335 of an image memory 337. A switch 343 connects an input 345 of a two-dimensional filter 347 to an output 339 of the image memory 333 or to an output 341 of the image memory 337. An output 349 of the two-dimensional filter 347 is connected to an input 351 of a sampling circuit 353, an output 355 of which is connected to the input 139 of the change-over switch 135 of Figure 1A.

The mid-resolution preprocessing circuit 145, as mentioned, is arranged to output a mid-resolution video signal, that is, a video signal suitable for a display 30 with temporal resolution twice as large as in the previous case and with a vertical resolution twice as small is as in the previous case. To this end, pairs of consecutive camera frames, which together form a high-definition image, are alternately written in the image memory 333 or in the image memory 337 via the switch 342. During the writing of one image memory 333 or 337, the other image memory 337 and 333 are respectively read . The signal filtered by the two-dimensional filter 347, which is band-limited in accordance with 8800449 t PHN 12.440 24 Figure 5B, is then sampled by the sampling circuit 353 according to a sampling pattern shifted from frame to be transmitted and then to the input. 139 of the inverter 135 of Figure 1A 5 is presented.

The operation of the sampling circuit 353 will be explained with the aid of figure 4B1. This figure consists of two columns L and R. The left column L shows how the successive high definition camera frames are sampled. For the first frame to be transmitted, samples from lines 1 + 4n are used from the first camera frame, n being an integer. For the second frame to be transmitted, samples from lines 3 + 4n are used from the first camera frame. The frames to be transmitted are thus obtained from the odd camera frames by means of so-called artificial interlacing. Thus, in this method, the second camera frame of each pair of camera frames is not sampled. A normal definition receiver will display the received frames as indicated in the left column L. A high definition receiver will merge two received frames each time as indicated in the right column R, again choosing between once per frame period or once per image period the last two merge received grids. In the latter case, the result thus obtained will be displayed for two grid periods. Samples still missing can then be obtained by means of interpolation.

When comparing the right column R of figure 4A

and the right column R of Figure 4B1 will notice that the number of pixels on each line is equal, and that the number of lines in the right column of Figure 4A is twice as large as the right column R of Figure 4B1. Thus, the horizontal resolution is the same in both cases, but the vertical resolution is halved in Figure 4B1 compared to Figure 4A. On the other hand, new information is available every 40 ms in Figure 4B1, which was the case in every 4 ms in Figure 4A, so that the temporal resolution in Figure 4B1 is doubled compared to Figure 4A.

In figure 4B2 an alternative is given, with respect to figure 4B1 being lost in horizontal resolution, but gain in vertical resolution, with constant temporal 88 0 0H9 PHN 12,440 resolution. The figure 4B2 consists of three columns L, M and R. The left column I »shows how the high definition camera frames are sampled. In the middle column M it is indicated how the samples obtained from each of two sampled camera frames are combined into frames to be transmitted by means of raster shift operations. Grid shifting operations of this type are described in European patent application EP-A 252,563 (PHN 11,819), and are therefore not further elaborated here. A normal definition receiver will display the transmitted frames as they have been received, 10 and a high definition receiver will combine two received frames as indicated in the right column R of Figure 4B2, whereby missing samples can then be obtained by interpolation.

When comparing the right columns R of Figures 4B1 and 4B2, it will be noticed that the number of samples transferred from each line in Figure 4B1 is twice as large as in Figure 4B2, so that the horizontal resolution in Figure 4B1 is twice that of Figure 4B2; on the other hand, the number of lines transmitted in Figure 4B2 is twice as large as in Figure 4B1, so that the vertical resolution in Figure 4B2 is double that in Figure 4B1.

In an alternative mid-resolution preprocessing circuit 145 ', shown in Figure 3B2, it is measured by means of a measuring circuit 357 whether there is more high horizontal frequencies than high vertical frequencies in a certain part of the image, which is preferably a block. appearance. If so, then the two-dimensional filter 347 and the sampling circuit 353 operating according to Figure 4B1 are turned on, and if not, a two-dimensional filter 347 'and a sampling and raster shifting circuit 353' operating according to Figure 4B2 are turned on. . In Figure 3B2, a common terminal of switch 343 is connected to an input 356 of measuring circuit 357, which controls a switch 358. The input 345 of the two-dimensional filter 347 and an input 345 'of the two-dimensional filter 347' are both directly connected to the common terminal of the switch 343. An output 349 'of the two-dimensional filter 347' is connected to an input 351 'of the sampling and raster shifting circuit 353'. The output 355 of the .8800449 PHN 12.440 26 * sampling circuit 353 is connected to a first switching contact of the switch 358, an output 355 'of the sampling and raster shifting circuit 353' is connected to a second switching contact of the switch 358 and a common connection of the 5 switch 358 controlled by the measuring circuit 357 is connected to the input 139 of the change-over switch 135 of FIG. 1A. The switch 358 thus selects, on the basis of spatial frequencies measured by the measuring circuit 357, whether an output signal of a first branch consisting of the two-dimensional filter 347 and the sampling circuit 353 already described, or an output signal of a second branch consisting of the two-dimensional filter 347 'and the sample and frame shifting circuit 353' is supplied to the input 139 of the changeover switch 135 of Figure 1A. Information about which branch is selected in the transmit portion is transmitted through the DATV auxiliary signal 15 to enable the receive portion to properly decode the received television signal.

The two-dimensional filter 347 ', as shown in Figure 5B2, has twice the cutoff frequency for vertical frequencies and half the cutoff frequency for horizontal frequencies compared to the two-dimensional filter 347.

Figure 3C shows the low-resolution pre-processing circuit 147 of Figure 1A, in which an input 359 of an image memory 361 is connected to the output 149 of the memory 125 of Figure 1A, an output 363 of which is an input 365 of a two-dimensional filter 367 is connected. An output 369 of the two-dimensional filter 367 is connected to an input 371 of a sampling and line shifting circuit 373, an output 375 of which is connected to the input 141 of the changeover switch 135 of Figure 1A.

The low-resolution pre-processing circuit 147 shown in Figure 3C is, as mentioned, arranged to output a low-resolution video signal, i.e. a video signal, of equal spatial and temporal resolution to a normal definition at the input 141 of the inverter 135. signal. The image memory 361 serves to obtain a time delay equal to the time delays of the image memories 303, 307, 333 .8800449 PHN 12,440 27 and 337 in Figures 3A and 3B1. An example of a schematic frequency response of the two-dimensional filter 367 is shown by a solid line in Figure 5C. An appropriate operation of the sampling and line shifting circuit 373 is shown in Figure 4C, which consists of three columns L, M and R. The left column L shows how two consecutive camera frames are sampled, the middle column M shows how the samples thus obtained are slid between each other for transmission. A normal definition receiver will display the received frames as indicated in the middle column M, and a high definition receiver will scatter the samples as indicated in the right column R, then interpolate the missing samples. In this case, in order to obtain a maximum temporal resolution in the high definition receiver, each received frame is displayed separately; a higher spatial resolution to be obtained by merging received frames is therefore deliberately omitted in this case, it being noted that merging frames that have been moved much relative to each other would lead to a nuisance motion blur.

In Fig. 5C, a dashed line and a dotted line 20 show two alternative frequency responses of a two-dimensional spatial low-pass filter, which can be switched on if there are many high horizontal and many high vertical frequencies in a (part of a) image of the high definition signal. appearance. In a similar manner as indicated in figure 3B2, parallel branches can also be switched on in the circuit of figure 3C by a changeover switch controlled by a measuring circuit. In general, a different filter will then not suffice, but a different sampling and shifting circuit will also have to be provided. However, all three variants 30 shown in Figure 5C can be used in combination with the same sampling and shifting circuit. In the circuit of Figure 3a, in principle, parallel branches with alternative filters and sampling and line shifting circuits can be switched on by a changeover switch operated by a measuring circuit. In a practical realization of a pre-processing circuit, the filtering, sampling and shifting operations can be combined into a single operation. Resampling an already sampled signal can be realized if the 8800449 4 PHN 12.440 28 original sampling frequency is a multiple of the new sampling frequency, as is the case here, by simply multiplying the omitted samples by a zero coefficient , so that the filtering and the 5 sampling operations can be easily combined. Parallel branches as described above can also be integrated into a single branch, to which, depending on the spatial frequencies, different sets of (filter) coefficients are presented.

10

In figure 6 a block diagram of an intermediate processing circuit 25 suitable for the receiving part according to figure 1B is shown. Its input 23 is connected to a video signal input 501 of a backshift circuit 503, a control input 505 of which is connected to the control input 27 of the intermediate processing circuit 25. An output 507 of the backslide circuit 503 is connected to a first input 509 of a switch 511 and to an input 513 of a first frame memory 515. An output 517 of this first frame memory 515 is connected to a second input 519 of the switch member 511 and to an input 521 of a second frame memory 523. An output 525 of the second frame memory 523 is connected to a third input 527 of the switch member 511 and to an input 529 of a third frame memory 531. An output 533 of the third frame memory 523 is connected to a fourth input 535 of the switch member 511. A control input 537 of the switch member 511 is connected to the control input 27 of the intermediate processing circuit 25. The switcher 511 supplies four terminals 539, 541, 543 and 545, which together form the quadruple output 49 of Figure 1B, samples from four successively received compatible frames to the post-processing circuits 43, 45 and 47 of Figure 1B.

In Figure 7, a block diagram of a high resolution post-processing circuit 43 suitable for the receiving portion of Figure 1B is shown. Terminals 539, 541, 543, and 545 are connected to four inputs of each of four sample pattern conversion circuits 701, 703, 705, and 707. Each of sample pattern conversion circuits 701, 703, 705, and 707 has .8800449 PHN 12,440 29 an output 709, 711, 713 and 715 respectively which is connected to an input 717, 719, 721 and 723 respectively of filter sections 725, 727, 729 and 731. Each of the filter sections 725, 727, 729 and 731 has a first output 733, 735, 737 and 739, respectively, for outputting partial interpolation results of the non-transmitted samples, as well as a second output 741, 743, 745 and 747, respectively, for outputting copies of the samples which have been transmitted or which have already been transferred by the sampling pattern conversion circuits calculated.

The operation of the sample pattern conversion circuits 701, 703, 705 and 707 and filter sections 725, 727, 729 and 731 is as follows. In the transmitter part of the above-described system, the high-definition frames are sampled according to a number of sampling patterns, which depend on the movement and / or spatial frequencies occurring in the video signal. The resulting samples were then pushed together as necessary to obtain a compatible television signal. If (virtually) none of the motion is selected to transmit the signal processed by the high-resolution pre-processing circuit 143 in the transmitter part, which is suitable for a display with a high spatial resolution, this means that in the embodiment described here of the system is spread a block of pixels from one high-definition image over four compatible frames to be transmitted, as shown in Figure 4A. The blocks located around this present block can be sampled according to the same, but also according to a different sampling pattern. The juxtaposition of blocks that have been sampled according to different sampling patterns has the drawback that these blocks cannot simply be processed by an interpolation filter. Moreover, this drawback does not occur if the amount of movement and spatial frequencies occurring in the video signal is not viewed per block, but per image. This drawback can be solved by prior to the filtering operation having the filter sections 725, 727, 729 and 731 process the incoming frames by the sample pattern conversion circuits 701, 703, 705 and 707, which are the 35 sample patterns of the blocks sampled according to other sample patterns. convert to the sample pattern of the subject block. This sample pattern conversion can be regarded as a kind of interpolation, and it is then also not possible in principle to integrate the sample pattern conversion circuits with the filter sections into one complex interpolator. However, it is easier in the prior art to separate sampling pattern conversion and filtering. The sample pattern conversion requires up to four consecutive frames, that is, if a frame is sampled as shown in Figure 4A, to obtain the "complete" sample pattern of a block to be converted. The complete sampling pattern is understood to mean the set of the four separate sampling patterns of each received frame, as drawn in the right column R of Figure 4A. The complete sampling pattern can be obtained in mind by superimposing the partial sampling patterns from four consecutive frames at the outputs 15 of the sampling pattern conversion circuits 701, 703, 705 and 707, respectively. Starting from the complete sampling pattern of a block to be converted, a block with the sampling pattern of the relevant signal path is generated in the sampling pattern conversion circuits. In the case of Figure 7, the sampling patterns of the frames sampled according to the mid-resolution or low-resolution sampling patterns are converted to the high-resolution sampling pattern.

In the circuit described here it has been chosen to perform the interpolation in parts by four separate filter sections. As mentioned, high resolution blocks are divided into four frames. Each of these frames is now individually processed by one of the filter sections, after which the partial interpolation results obtained hereby are added together to arrive at a complete interpolation result. This method was chosen because of its easy implementation; other more integrated interpolation techniques are of course also possible. For this purpose, each sample pattern conversion circuit 701, 703, 705 and 707 supplies the associated filter sections 725, 727, 729, and 731 with the part of a complete sample pattern located in one frame. To add up the partial interpolation results, the output 733 of the filter section 725 and the

, & 80 0MS

PHN 12.440 31 output 735 of the filter section 727 is connected to a first input 749 and a second input 751 of a first adder 753, respectively, and the output 737 of the filter section 729 and the output 739 of the filter section 731 are connected to a first input 755 and 5 respectively. a second input 757 of a second adder 759 is connected. An output 761 and 763 of the first adder circuit 753 and an output 763 of the second adder circuit 759 are connected to a first input 765 and a second input 767 of a third adder circuit 769, respectively. In principle, it is of course also possible to add the four partial interpolation results in another way; however, the above method, in which two partial results are added together, is the simplest in the current state of the art; however other solutions are also possible.

Similarly, the output 741 of the filter section 725 and the output 743 of the filter section 727 are connected to a first input 771 and a second input 773 of a first switching member 775, respectively, and the outputs 745 and 747 of the filter section 729 and the output 747 of the filter section 731 is connected to a first input 777 and a second input 779 of a second switching member 781, respectively. An output 783 and 785 of the first switch member 775 and an output 785 of the second switch member 781 are connected to a first input 787 and a second input 789 of a third switch member 791, respectively. In principle, it is also possible to combine the copied samples from the four frames in another way; however, the above method, in which two partial results are always added together, is the simplest in the current state of the art; however other solutions are also possible. An output 793 of the third adder circuit 769 is connected to an input 795 of a fourth switch member 797, a second input 799 of which is connected to an output 801 of the third switch member 791. The fourth switch member 797 has a first output 803 and a second output 805 for outputting odd and even signal samples, respectively, to inputs 37 'and 37 *, respectively, of the switcher 35 of FIG. 1B, which together form the dual input 37 35 thereof. The odd and even signal samples are output from these separate outputs, because the number of bits per second of an output signal at each of the outputs is halved to .8800449 a PHN 12,440 32 compared to a situation where a full output would be at only a single output be issued. The solution chosen is the simplest in view of the current state of the art and the high numbers of bits per 5 seconds occurring in high definition television. However, as the technique advances, the other solution with only one output may become preferable.

Figure 7 shows that the control input 42 of the high-resolution post-processing circuit 43 is connected to a control input 807 of the fourth switch member 797. Of course, the control input 42 is also connected to control inputs (not shown) of the other switching members 775, 781 and 791 and of the sample pattern conversion circuits 701, 703, 705 and 707.

In figure 8 a block diagram of a mid-resolution post-processing circuit 45 suitable for the receiving part according to figure 1B is shown. Terminals 539, 541, 543 and 545 are connected to four inputs of a first sample pattern conversion circuit 821 and to four inputs of a second sample pattern conversion circuit 823. The first sample pattern-20 conversion circuit 821 has an output 825 connected to an input 827 of a filter section 829 for calculating a partial interpolation result of odd samples and with an input 831 of a filter section 833 for calculating a partial interpolation result of even samples. The second sample pattern conversion circuit 823 has an output 835 connected to an input 837 of a filter section 839 for calculating a partial interpolation result of odd samples and to an input 841 of a filter section 843 for calculating a partial interpolation result of even monsters. Outputs 845 and 847 of the filter sections 829, 30 and 839, respectively, are connected to inputs 849 and 851 of a first adder 853, which outputs an interpolation result of odd samples to an output 855, which is connected to an input 39 'of the inverter 35 of Figure 1B. is. Outputs 857 and 859 of the filter sections 833 and 843, respectively, are connected to inputs 861 and 863, respectively, of a second adder 865, which outputs an interpolation result of even samples at an output 867, which is fed with an input 39 "of the inverter 35. OM 9 ΡΗΝ 12,440 33 • ^ ΐρ ,, ιί-'ΐρ Figure 1Β is connected. The input 39 'together with the input 39 "forms the dual input 39 of the change-over switch 35 of FIG. 1B.

The control input 44 of the mid-resolution post-processing circuit 45 is connected to an input 822 of the sample pattern conversion circuit 821 and to an input 824 of the sample pattern conversion circuit 823.

In Figure 9, a block diagram of a low-resolution post-processing circuit 47 suitable for the receiving portion of Figure 10 1B is shown. Terminals 539, 541, 543, and 545 are connected to four inputs of a sample pattern conversion circuit 901. The sample pattern conversion circuit 901 has an output 903 connected to an input 905 of a filter section 907 for calculating an interpolation result of odd samples which is delivered to an output 909, which is connected to an input 41 'of the change-over switch 35 of figure 1B. The output 903 of the sample pattern conversion circuit 901 is also connected to an input 911 of a filter section 913 for calculating an interpolation result of even samples output to an output 915, which is connected to an input 41 "of the inverter 35 of FIG. 1B. The inputs 41 'and 41 "of the changeover switch 35 of FIG. 1B together form the dual input 41 thereof.

The control input 46 of the low-resolution post-processing circuit 47 is connected to an input 902 of the sampling pattern conversion circuit 901.

Figure 10 shows a block diagram of a sample pattern conversion circuit suitable for use in a post-processing circuit according to Figures 7 (701, 703, 705 or 707), 8 (821 or 823) or 9 (901). Terminals 539, 541, 543 and 545 are connected to inputs 1001, 1003, 1005 and 1007, respectively, of filter sections 1009, 1011, 1013 and 1015, respectively. Outputs 1017 and 1019 of filter sections 1009 and 1011, respectively, are with inputs 1021 and 1023 of a first adder. 1025, 35 of which an output 1027 is connected to a first input 1029 of a second adder 1031. Outputs 1033 and 1035 of the filter sections 1013 and 1015 are connected to inputs 1037 and 1039, 8800449 PHN 12.440 34 * of a third adder 1041, of which an output 1043 is connected to a second input 1045 of the second adder 1031. An output 1047 from the second adder 1031 outputs the conversion result. a control input 1049 of the sample pattern conversion circuit is connected to a control input 1051 of the filter section 1015, to a control input 1053 of the filter section 1013, to a control input 1055 of the filter section 1011 and to a control input 1057 of the filter section 1009.

In general, not all filter sections 1009 through 1015 are active at the same time. Which of these filter sections are active depends on the input sampling pattern applied to terminals 539 through 545. If this input sampling pattern is the high resolution sampling pattern, all four filter sections 1009 through 1015 may be active. If the input sampling pattern is a mid-resolution sampling pattern, the first two filter sections 1009 and 1011 will be active during the first image of every two images and the last two filter sections 1013 and 1015 will be active during the second image of each two images. If the input sampling pattern is a low-resolution sampling pattern, only one of four filter sections 1009 through 1015 will be active during each frame: filter section 1009 during the first frame of four consecutive frames, filter section 1011 during the second frame. , the filter section 1013 during the third frame, and finally the filter section 1015 during the fourth frame.

Figure 11 shows a block diagram of a motion-compensated interpolation circuit suitable for use in series with the high-resolution post-processing circuit 43 of Figure 7 or with the mid-resolution post-processing circuit 45 of Figure 8. With respect to Figure 1B, these motion-compensated interpolation circuits may be present between the output of the high-resolution post-processing circuit 43 and the mid-resolution post-processing circuit 45 and the input 37 and 39, respectively, of the inverter 35. At input terminals 1101 and 1103, which may be connected to the outputs 803 and 805 of the high-resolution post-processing circuit, respectively. 43 (FIG. 7) or with the outputs 855 and 867 of the mid-resolution post-processing circuit 45 (FIG. 8), the odd and even samples. 8800449 PHN 12,440 35 are presented. The input terminals 1101 and 1103 are connected to inputs 1105 and 1107 of a switchable delay member 1109, and are connected via inputs 1111 and 1113 to inputs 1115 and 1117, respectively, of a switchable delay member 1119. If the motion compensated interpolation circuit is connected in series with the high-resolution post-processing circuit 43, the memories 1111 and 1113 delay two frame times, and if the motion-compensated interpolation circuit is connected in series with the mid-resolution post-processing circuit 45, the memories 1111 and 1113 1113 for a delay of one frame time. An odd sample output 1121 from the switchable delay 1109 is connected to a first input 1123 of an adder 1125, a second input 1127 of which is connected to an odd sample output 1129 from the switchable delay 1119. An output 1131 of the adder 1125 is connected to an input 1133 of a half-circuit 1135, an output 1137 of which is connected to an output terminal 1139 for odd samples of the motion-compensated interpolation circuit. An even sample output 1141 of the switchable delay member 1109 is connected to a first input 1143 of an adder 1145, a second input 1147 of which is connected to an even sample output 1149 of the switchable delay member 1119. An output 1151 of the adder 1145 is connected to an input 1153 of a half-circuit 1155, an output 1157 of which is connected to an output terminal 1159 for even samples of the motion-compensated interpolation circuit. A control input 1161 of the motion-compensated interpolation circuit, which is connected to the output 31 of the DATV decoding circuit 29 of Figure 1B and to which the motion vectors decoded by the DATV decoding circuit 29 are supplied, is provided with a control input 30 1163 of the switchable delay 1109 and connected to a control input 1165 of the switchable delay member 1119.

The operation of the motion compensated interpolation circuit of Figure 11 is as follows. A block of 35 pixels from the current image is applied to the inputs 1105 and 1107 of the switchable delay member 1109. By the switchable delay member 1109, this block is pushed back one quarter, half or three quarters of the motion vector in the direction of the. 880 044 9 ► t PHN 12.440 36 motion vector, which is transmitted by the transmitter in the DATV signal. To this end, the switchable delayers 1109 and 1119 are controlled by the output signal at the output 31 of the DATV decoding circuit 29 of Figure 1B. Inputs 1115 and 1117 of the switchable delay member 1119 are supplied with a block of pixels from the previously transmitted image. By means of this switchable delay member 1119, this block is advanced three-quarter half and one quarter motion vector in the direction of the motion vector, respectively. The blocks are shifted by quarters of 10 motion vectors if a video signal with high possible spatial resolution must still be displayed with large and uniform motion. The blocks are shifted half motion vectors if a video signal with middle spatial resolution is to be displayed with large and uniform motion, or if a video signal with high spatial resolution is to be displayed with small and uniform movement. The adders 1125, 1145 and the semicircuits 1135, 1155 average the shifted blocks from the current image and from the previous transmitted image.

Figures 12A, 12B and 12C show a block diagram of a switchable delay means suitable for the motion compensated interpolation circuit of Figure 11. Figure 12A shows a block diagram of an odd sample delay means 1201 provided with sixteen terminals A1 through A4, B1 to B4, C1 to C4, D1 to D4, for connection to a switch 1203, shown in a block diagram in Figure 12C. Figure 12B shows a block diagram of an even sample 120Γ retarder with sixteen terminals ΑΓ through A4 ', ΒΓ through B4', C1 'through 30 with C4', D1 'through D4' , for connection to the switching member 1203. The switching member 1203 produces a video signal which has undergone a delay corresponding to this motion vector on the basis of a motion vector supplied to a control input 1299 thereof.

In Figure 12A, an input terminal 1207 of the odd sample delayer 1201 is with an input 1209 of a line memory 1211, with the terminal A4 and with an input 1213 of a ~ .8800449 * PHN 12.440 37 pixel memory. 1215 connected. An output 1217 of the pixel memory 1215 is connected to the terminal A3 and to an input 1219 of the pixel memory 1221. An output 1223 of the picture element memory 1221 is connected to the terminal A2 and via a picture element memory 1225 to the terminal A1. An output 1227 of the line memory 1211 is connected to an input 1229 of a line memory 1231, to the terminal B4 and to an input 1233 of a picture element memory 1235. An output 1237 of the pixel memory 1235 is connected to the terminal B3 and to an input 10 1239 of the pixel memory 1241. An output 1243 of the picture element memory 1241 is connected to the terminal B2 and via a picture element memory 1245 to the terminal B1. An output 1247 of the line memory 1231 is connected to an input 1249 of a line memory 1251, to the terminal C4 and to an input 1253 of a picture element memory 1255. An output 1257 of the picture element memory 1255 is connected to the terminal C3 and to an input 1259 of the picture element memory 1261. An output 1263 of the pixel memory 1261 is connected to the terminal C2 and via a pixel memory 1265 to the terminal C1. An output 20 1267 of the line memory 1251 is connected to the terminal D4 and to an input 1273 of a picture element memory 1275. An output 1277 of the pixel memory 1275 is connected to the terminal D3 and to an input 1279 of the pixel memory 1281. An output 1283 of the picture element memory 1281 is connected to the terminal D2 and via a picture element memory 1285 to the terminal D1.

A description of the retarder for even samples 1201 'in Figure 12B can be obtained by providing all of the reference symbols with an accent (') in the above description of the retarder for odd samples 1201 'in Figure 12A.

The switching member 1203 shown in Figure 12C is constructed with a first switch 1287 with the sixteen terminals A1 to D4, with a second switch 1287 'with the sixteen terminals A1' to D4 'and with a third switch 35 1289 a first input 1291 connected to an output 1293 'of the first switch 1287' and a second input 1291 'connected to an output 1293' of the second switch 1287 '.

.8800443 ____. __i y * PHN 12,440 38

The third switch 1289 further includes a first output 1295 connected to an odd sample output terminal 1297 of the switchable delay means and a second output 1295 'connected to an odd sample output terminal 1297' of the switchable delay mechanism. The control input 1299 of the switch member 1203 is connected to a control input 1301 of the second switch 1287 ', to a control input 1303 of the first switch 1287, and to a control input 1305 of the third switch 1289.

With the aid of this switchable delay means, 10 of four lines on a raster basis, eight pixels can be achieved, so that a range of maximum +3 to -3 is achieved on an image basis.

Numerous variants will come to mind when reading the present description; all these variants are included in the scope of the invention.

8800449

Claims (15)

System for transmitting and receiving a television signal over a channel, at least comprising a transmitting part and a receiving part coupled to the channel, which television signal comprises a video signal, the transmitting part being provided with a sampling circuit, of a number of transmitting partial signal paths, coupled to respective signal inputs of a transmitter portion output circuit and of a motion processing circuit comprising a motion detection circuit for measuring the magnitude of motion in the video signal, which is a type 10 sampling circuit adapted to output a sampled frame of the video signal a sample pattern shifted from frame to be output to frame to be output, said motion processing circuit having an output coupled to a control signal input of. the transmit output circuit coupled to the channel, the receive portion comprising a plurality of receive sub signal paths coupled to the channel coupled to respective inputs of a receive sub output circuit, characterized in that the number of transmit signal paths is at least equal to three and the motion processing circuit is arranged to classify the magnitude of the movement into a number of classes, which number of classes is equal to the number of transmit partial signal paths, the transmit partial signal paths each comprising separate sampling circuits of the said type, which sample according to separate sampling patterns, and of a anti-fold-back filter adapted to the sampling pattern of the sampling circuit in the transmit signal path, wherein the transmit output circuit is a change-over switch, wherein in the receive portion the number of receive sub-signal paths is at least three, receiving Input partial signal paths are arranged to merge different numbers of received frames, and the receive partial output circuit is a changeover switch. 2. System as claimed in claim 1, characterized in that the motion detecting circuit is arranged to output a first and a second signal indicating whether the magnitude of the motion is greater than a first and second threshold, respectively, of which motion detecting circuit outputs are coupled with inputs of .8800449 if ί PHN 12.440 40, a block motion control circuit for classifying the magnitude of the motion into three classes based on the first and second signals. System according to claim 1 or 2, characterized in that the motion processing circuit is provided with a spatial consistency control circuit. 4. System according to any one of the preceding claims, characterized in that the motion processing circuit is provided with a raster number controller for determining a route of temporal images or parts of images through the motion-based classification of the magnitude of the motion. transmit signal paths. System according to claim 4, characterized in that the motion processing circuit further comprises a route consistency controller. 6. System according to any one of the preceding claims, characterized in that the motion processing circuit is provided with a motion estimator, which determines a motion vector and the uniformity of the motion. 7. System as claimed in any of the foregoing claims, characterized in that at least one transmission partial signal path is provided with a transmitter partial selection circuit with a number of signal inputs for supplying signals suitable therefor for displaying each with a different distribution of horizontal and vertical resolution, and of a measuring circuit for measuring these horizontal and vertical frequencies occurring in the video signal. 8. System according to any one of the preceding claims, characterized in that the transmitting part is provided with a film mode, wherein the transmitting sub-signal path which outputs a signal suitable for a high temporal resolution display is not coupled to the channel. .8800449 V PHN 12.440 41 9. System as claimed in any of the foregoing claims, characterized in that each receiving sub-signal path comprises a conversion circuit for converting a sampling pattern of a block of picture elements which has been sampled with a sampling pattern which does not correspond to the receiving sub-signal path and is adjacent to a block that is sampled. is with a sampling pattern corresponding to this receiving sub-signal path, to this corresponding sampling pattern. System according to any one of the preceding claims, characterized in that at least one receiving sub-signal path comprises a motion-compensated interpolation circuit. 11. System as claimed in any of the foregoing claims, characterized in that at least one receiving sub-signal path is provided with a receiving sub-selection circuit with a number of signal inputs for supplying signals suitable therefor for a display with a different distribution of horizontal and vertical resolution. Transmitter suitable for the system according to any one of claims 1 to 8. Receiving part suitable for the system according to one of claims 1, 9, 10 or 11. 25 14. Method for transmitting or storing a television signal over a channel or on a storage medium, which television signal comprises a video signal, comprising sampling the video signal according to a sampling pattern shifted from frame to be delivered, and measuring the magnitude of the movement in the video signal for forming a television signal to be delivered to the channel or to be stored on the storage medium on the basis of this magnitude of the movement, from results of a number of possible operations on the video signal, with the characterized in that the number of possible operations on the video signal is at least three and the magnitude of the movement is classified into a number of classes, the number of classes being equal to .8800449 PHN 12.440 42 * to the number of possible operations on the video signal, the various operations on the video signal include one according to separate sample Sampling the video signal as well as, prior to sampling, anti-fold-back filtering of the video signal adapted to the sampling pattern 5, and comprising forming the television signal to be delivered to the channel or to be stored on the storage medium and a selection of a operation on the video signal from the number of possible operations on the video signal. 10 15. Television receiver, comprising means for forming a video signal to be displayed from results of a number of possible operations on a received television signal, which received television signal comprises a received video signal, which means are characterized in that the number of possible operations on the received video signal is at least equal to three and each operation corresponds to a different one each from at least three different sampling patterns, according to which the received video signal may be sampled for transmission, operations 20 comprising merging different numbers of frames from one another. received video signal and wherein forming the video signal to be displayed comprises selecting an operation on the received video signal from the number of possible operations on the received video signal. 8800443