NL8301625A - Data repeater with clock phase synchronisation - locks phase of local clock signal to that of incoming message signal - Google Patents

Abstract

The incoming data signal (1) is fed directly (3) and in delayed form (4) to level sensors (5). The sensors are clocked by a locally generated clock signal (8). The sensor outputs (9,10) are compared by a logic circuit (11). The comparator output (13) is fed to a memory (14) which alters the phase of the clock signal (8) via a switching circuit. The sensors (5) and memory (14) circuits can be D-type flip-flops. The comparator can be an AND-gate, and the switching circuit (16) can be an Exclusive-OR gate.

Description

* *. »·.

VO 4820

Synchronization device with clock signal phase selection.

A- Background of the Invention 1. Field of the Invention

The invention relates to a device for synchronizing the phase of a clock-5 signal derived from a local clock signal with that of a message signal. Devices of this kind aim to solve the problem that can arise with signal transmission, for example in telephone exchanges, between two equipment cabinets, and at higher bit rates even between two picture plates within the same cabinet η.1. that the local clock signal cannot simply be used to clock in the 10 message signals, even if this originates from the same master clock as the message signals were originally generated. Due to transit time differences, phase shifts have been created, so that the phase relationship between the original clock-15 signal implicitly present in the message signal and the local clock signal is no longer known. The two clock signals are therefore homochronous, but not synchronous. This makes synchronization more difficult. When η.1. locally, the edges of the bit transitions in the message signal substantially coincide with the clock edges, then it is not certain that the bit transitions are adopted in the local circuit, resulting in data loss or in an 830 1 625 - 2 - N · * Get undefined state of parts of the local circuit. This synchronization problem occurs the sooner the difference can occur in the duration of the bit transitions (0 * 1) and (1 + 0), causing pulse shortening or broadening.

5 2. Stan £ of the technique

Attempts to solve said problems are known, such as, for example, from Dutch patent application 8101992, which was made available for inspection on November 16, 1982 and relates to a chain device in which an incoming message signal is synchronized with clock pulses which transmit the bit value transitions of the Mark the direction signal. According to this known technique, every message signal edge is detected. On the basis of an edge detection pulse obtained thereby, it is determined with the aid of a counter to what extent the phase of the relevant message signal edge has shifted from a reference value. The relationships between a set of such phase shifts that can be expected, and phase shifts of said clock pulses are given by information content of a memory or a logic circuit; with the relations thus determined, the phase shift of the clock pulse desired for restoring synchronism is then introduced, starting from a detected phase shift. In this known technique it is necessary to make use of a counter or similar circuit arrangement, to which an auxiliary clock signal is supplied, the frequency of which is relatively high compared to that of the aforementioned clock pulses. In addition, a memory or similar chain device is required to record the intended relationships. Apart from the relatively complicated structure, the drawback is that the memory content must always be adapted to the relationship between the frequencies of the auxiliary clock signal and the clock pulses that mark the bit value transitions in the formed message signal.

Another proposal is known from Dutch patent application 8000606, which was made available for inspection on September 1, 1981. In the apparatus described herein, the clock signal is delayed by a delay line comprising a series of taps, each of which provides a clock signal with a different phase.

After a reset of the device, in a coincidence detection circuit, the optimum clock signal phase is determined by selecting that phase shifted 180 ° from the phase providing the first clock signal edge after the occurrence of the first message signal edge. The device is locked at this selected phase.

A drawback of the synchronization system described in the last-mentioned application is that, if the selected clock signal and the message signal become out of phase over time, for example due to temperature changes, a reset of the device is always required before the device can be locked to another optimal clock signal phase. In addition, a reset can only be advantageously performed in a message-free period, because otherwise there is a risk of locking on the wrong clock signal edge.

B. Summary of the invention

The object of the invention is to provide a device which provides a continuous phase monitoring, which does not require an external reset, and which does not require an auxiliary clock signal with a much higher frequency than the original clock signal and no counter elements. The underlying insight is the following. In the situation in which the invention is applied, the local clock signal has the same or substantially the same frequency as the clock signal at which the message signal was originally generated. To avoid said synchronization problems, the message signal is preferably "clocked in" with the clocking edge of the local clock signal in the center of each message signal bit. When it is found that due to phase progression, this clock edge is near one bit edge in the message signal, the other clock edge not used as clock edge is near said center; that is, the inverted signal of the clock used until then for clocking has a particularly suitable phase to be used as a clock signal.

The invention is characterized by a detector circuit which periodically determines with a tempering which has been amplified by the derived clock signal whether the mutual distance between a respective edge of the derived clock signal and an adjacent edge of the message signal has become smaller than a fixed given time distance, as well as, if such a time gap reduction is detected, produces a control signal, which corrects the phase relationship between the derived clock signal and the message signal.

The determination whether the relevant clock signal edge is in the vicinity of the message signal edge can be determined as follows. Within each clock period (T sec), the state of the message signal is examined at the time of the clocking edge and at τ sec before or after (with τ «T). If these two states are different, a message signal edge has occurred within that τ sec. This means that clock edge and message signal edge are so close together that phase shifting of the derived clock signal is desired. Preferably, for this purpose, the detector circuit comprises a sensor circuit which produces a first signal and a second signal under the control of the derived clock signal, which first signal is representative of the state of said message signal at periodic times determined by the derived clock signal, and which second signal is representative of the state of said message signal at periodic times which are each shifted a fixed time distance τ with respect to the first mentioned times, and a logic circuit starting from said first signal and said second signal said control signal may cause indicating that the time distance between a respective edge of the derived clock signal and an adjacent edge of said message signal is less than said time distance τ, and the device is further characterized by a control circuit responsive to said control signal synchronism between restores the derived clock signal and the message signal 8301625.

Said first and second signals can be obtained, for example, in the following ways: (i) delaying the message signal by a time τ and then including both the message signal and the delayed message signal synchronously in the detector circuit with the derived clock signal, (ii) delay the derived clock signal by a time T and then include the message signal in the detector clock as well as in the derived clock signal 10 as in the delayed derived clock signal.

In the exemplary embodiments to be described with reference to the drawing, only method (i) is used.

Said control signal is used to invert the derived clock-15 signal and maintain this inversion until the next control signal effects a new inversion. Preferably, said control circuit therefore comprises a memory element serving to maintain a said control signal until the next control signal is generated, and logic switching means having the control signal and the local clock signal as inputs, and the derived clock signal as output.

It is further preferred that said logic switching means perform an EXOR function.

A device according to the invention contains relatively few logical components, - if fitted as standard on a picture plate, - does not need to take up much space, but nevertheless provides a permanent and reliable monitoring of the synchronization of the message signal for underlying circuits.

For the synchronization of the message signal, the derived clock signal is always used in the direction. Depending on the clock frequency used, either the local clock signal or the derived clock signal can be used for the underlying circuits in the same box or on the same picture plate.

8301625 '* * - 6 - C. Brief description of the drawing

The invention will be elucidated hereinbelow with reference to the drawing. Thereby shows:

Figure 1: a diagram illustrating the basic principle of the invention with delayed message signal;

Figure 2: a diagram of an embodiment to be used at relatively low clock frequencies;

Figure 3: Time sequence diagrams in Figure 2;

Figure 4: a diagram of an embodiment to be used at relatively high clock frequencies; and

Figure 5: Time sequence diagrams in Figure 4.

D. Description of the embodiments

The basic principle schematically shown in Figure 1 works as follows. A message signal 1 enters a detector circuit 2, and 15 is applied to a sensor chain 5 both directly (3) and delayed (4) (with delay time τsec). A local clock signal 6 is applied to a control circuit 7, which is one of the local clock signal derives derived clock signal 8. The derived clock signal 8 serves as a clock signal for a sensor circuit 5 included in the detector circuit 2.

This sensor circuit supplies a first signal 9, which is representative of the message signal 3 clocked in at the derived clock signal 8, and a second signal 10, which is representative of the delayed message signal 4 clocked in at the same clock signal 8, of a logic circuit 11. also part of the detector circuit 2. The sensor circuit is such that the first signal 9 and the second signal 10 only differ if the clocking edge of the derived clock signal 8 falls in the τ period between a bit edge in the message signal 3 and the corresponding bit edge in the delayed message signal 4. The logic circuit 11 detects a possible inequality and then supplies a control signal 13 via a control line to a memory element 14, which is included in the control circuit 7. This memory element 14 supplies a state signal 15 to logic switching means 16, which perform an EXOR function and, on the basis of the value of the state signal 15 (logic '0' or logic M '), the derived clock signal 8 8301625 W Λ - 7 - the local clock signal 6 or the inverted local clock signal. Until an inequality is detected again in detector circuit 2, the message signal is clocked in at the most recently derived clock signal 8 and is passed on to equipment behind it at message signal output 17. Depending on the height of the selected clock frequency, this underlying equipment operates on the local clock signal 6 (via line 6f) or the derived clock signal 8 (via line 8f).

Figure 2 schematically illustrates an embodiment of the basic principle described in Figure I at relatively low clock frequencies. This depends on the logic family used (e.g.

15 MHz for STTL). The sensor circuit 5 herein consists of two D flip-flops 18 and 19 for clocking in the direct message signal 3 and the delayed message signal 4, respectively. The logic circuit 11 is formed by combined AND-NOR gate 20 for detecting an inequality at said clocking in and outputting the control signal 13 via a control line. The combined gate 20 consists of three AND gates with two inputs each, and a NOR gate with the three outputs of the AND gates as inputs. The 20 Q outputs and the Q outputs of the flip-flops 18 and 39 are connected to a first AND gate, and a second AND gate of gate 20, respectively. The memory element 14 is formed by a third D flip-flop 21, which is switched as a two-divider and the control signal 13 is applied to the clock signal input of this D-flip-25 flop 21. The Q output of flip-flop 21 supplies the state signal 15 for the logic switching means 16, which consist of an EXOR gate 22, which last gate from the EXOR of the state signal 15 and the local clock signal 6 supplies the derived clock signal 8. This signal 8 serves as a clock signal for the two flip-flops 18 and 19, and 30 is also applied to both inputs of the third AND gate of the combined gate 20.

Figure 3 provides a time sequence diagram of the various signals in the device of Figure 2. (The number by which each diagram v6Sr 8301625-8 - the ordinate axis is indicated corresponds to the line number in Figure 2).

Suppose that at some point the state signal 15 is (still) zero. The local clock signal 6 then results in a slightly shifted clock signal 8. When the clock edge of this clock signal 8 for the D flip-flops 18 and 19 falls between the edge of the message signal 3 and that of the delayed message signal 4, then a different signal will appear at the outputs Q (and Q) (see timelines 3, 4, 8, 9 and 10 of Figure 3). Apparently the 10 clock edge then lies near the data edge, so that it makes sense to shift the clock edge for half a period.

The top two AND gates of the combined gate 20, together with the NOR gate, form an EXOR function, in that the Q and Q outputs of the flip-flops 18 and 19 are supplied correctly. Via the bottom 15 AND gate, the transmission of this EXOR function can be blocked by making both inputs 1. The derived clock signal 8 is now applied to these inputs, so that any difference between the Q outputs of the flip-flops 18 and 19 is only passed to the flip-flop 21 during the zero being of the derived clock signal 8. suppress short pulses created by travel time differences in flip-flops 18 and 19. If the flip-flops 18 and 19 have indeed clocked in a different signal, the control signal on the control line 13 will go to 1 when the clock signal 8 becomes 0. The flip-flop 21 25 switched as a two-divider then switches over and as a result (see arrow PI in figure 3) the output of the control circuit 7 is inverted. This output provides the derived clock signal 8. Since this signal is used as a clock signal by the flip-flops 18 and 19, the entire detection system starts operating on the clock signal shifted in phase by 180 °. If, for whatever reason, the signals still expire, an adjustment can be made again. For the underlying circuit, the unadjusted clock signal, this is the local clock signal 6 ', can be used. A fourth D-flip-flop 23 (Fig. 2) has been added to ensure in all circumstances that the message signals 8301625 '** ·' ^ - 9 clocked in by the flip-flop 18 at the derived clock signal 8 are synchronous with the local clock. .

The maximum clock frequency at which the circuit according to Figure 2 still functions correctly can be derived from the maximum delay times of the combined AND-NOR gate 20, the flip-flop 21 and the EXOR gate 22. The sum of these times must be smaller. are then half the clock period. For components of the logic family STTL, the intended delay times are in the order of 5.5, 9 and 10.5 nsec, respectively, so that a device according to Figure 2 can synchronize message signals up to about 15 MHz without problems. This upper limit can still be slightly shifted by selecting the components.

At relatively high frequencies (so from about 15 MHz for STTL) it will be necessary to use the derived clock signal 8 'in the underlying circuit (see Figure 1), because the detection of the wrong position of the' old 'clock edge and the necessary conversion to the other' new1 clock edge can no longer be carried out within half a clock period.

Figure 4 schematically illustrates an embodiment of the invention suitable for higher clock frequencies (up to 60 MHz for STTL).

In this embodiment, the sensor circuit 5 (Fig. 1) consists of two D flip-flops 25 and 26, each with its own reset input R. The logic circuit 11 (Fig. 1) is formed by a combined AND-NOR gate 27 (of the same type as gate 20) and an additional D flip-flop 28. Gate 27 is connected to flip-flops 25 and 26 in a similar manner as in the embodiment of Figure 2. The output of gate 27 provides an impure control signal 29 to D input of flip-flop 28. The Q output of flip-flop 28 is connected to the R inputs of flip-flops 25 and 26. The Q-output of flip-flop 28 supplies the control signal 13 to the control circuit 7, whatever signal is applied at both 30 inputs of the third AND gate of the combined AND-NOR gate 27.

Figure 5 shows some time sequence diagrams corresponding to the embodiment according to Figure 4 (here too, the number with which each diagram is indicated in front of the ordinate axis corresponds to the corresponding line number in Fig. 4). As with the embodiment according to Figure 2, the upper two AND gates and the NOR gate of the combined AND-NOR gate 27 through the connection of the Q and Q outputs of the flipflops 25 and 26 form an EXOR function of the Q outputs of the same flipflops. Due to the feedback from the Q output of flip-flop 28 to the third AND gate of gate 27, the transmission of this EXOR function can only take place if the Q output of flip-flop 28 is 0. Flip-flop 28 has been added to the circuit to eliminate short spikes ("spikes") that may be present in the impure control signal 29 due to travel time differences within flip-flops 25 and 26.

If at any given time a different signal is clocked in by the flip-flops 2j and 26, flip-flop 28 on the next rising clock edge will clock in the 1, which then outputs the combined AND-NOR gate 27. As a result of this "set" of flip-flop 28, three actions take place (indicated in Figure 5 by arrows P2, P3 and P4, and P5): - P2: The combined AND-NOR gate 27 is blocked by the output to 0 is pressed.

- P3 and P4: The flipflops 25 and 26 are reset so that no new error state can be transmitted due to the 20 extra clock edges that occur during the inverting of the clock signal. The latter serves to prevent the switching process from being disrupted.

- P5: Flip-flop 21 in the control circuit 7, which is switched as a two-way divider, is converted. The changed Q output of flip-flop 21 causes the derived clock signal 8 to be inverted at the output of the EXOR gate 22 of the control circuit 7.

Due to the blocking of the combined AND-NOR gate 27, flip-flop 28 on the next clock edge will clock 0 and thus be reset.

This causes the flip-flops 25 and 26 to be released again, as well as the combined AND-NOR gate 27. The entire circuit is then at rest again, but clocks in with a clock signal shifted in phase by 180 ° relative to the initial state. The maximum clock frequency at which this circuit still works correctly 8301625 - II - is determined by the delay times of the flip-flops 25 or 26 and the gate 27, which must be smaller than the full clock period T, otherwise 'spikes' will occur again. may interfere with proper operation due to "race" conditions. Clock frequencies up to 60 MHz can thus be achieved with STTL components 5. This maximum limit can also be increased by selecting the components.

It goes without saying that, without departing from the scope of the invention, good operation at higher frequencies can be obtained with the aid of components of even faster logic families.

3301625

Claims (10)

Device for synchronizing the phase of a clock signal derived from a local clock signal with that of a message signal, characterized by a detector circuit (2), which periodically detects with a tempering amplified by the derived clock signal (8) or the * The distance between a respective edge of the derived clock signal (8) and an adjacent edge of the message signal (1) has become smaller than a fixed given time distance, and if such a time reduction has been detected, produces a control signal (13) with which the phase relationship between the derived clock signal (8) and the message signal (1) is corrected. Device according to claim 1, characterized in that a sensor circuit (5) forms part of said detector circuit (2), which, under the control of the derived clock signal (8), a first signal (9) and a second signal (10) which first signal (9) is representative of the state of said message signal (1) at periodic times determined by the derived clock signal (8), and which second signal (10) is representative of the state of said message signal (1) at periodic times each shifted by a fixed time distance τ relative to said times, and a logic circuit (II) starting from said first signal (9) and said second signal (10) said control signal (13) can cause indicating that the time distance between a respective edge of the derived clock signal (8) and an adjacent edge of said message signal (1) is less than said fixed time distance nd τ; the device further characterized by a control circuit (7) which, in response to said control signal (13), restores synchronism between the derived clock signal (8) and said message signal (1). Device according to claim 2, characterized in that said sensor circuit (5) is provided with a first input for receiving the message signal (1,3) and with a second input for receiving an over said time interval τ delayed replica (4) of this message signal, as well as being arranged in response each time to 8301625 m *. - to cause said first and second signals (9,10) to appear simultaneously on a respective edge of the derived clock signal (8). Device according to claim 2, characterized in that said sensor circuit (5) comprises a first input for receiving the message signal (1), a second input for receiving the derived clock signal (8). and from a third input for receiving a replica of this derived clock signal (8) delayed by the said time interval τ, and is arranged to each time in response to two flanks of the derived clock signal said displaced by this time interval τ said first and second signals. (9,10) successively. Device according to any one of claims 2-4, characterized in that said control circuit (7) comprises a memory element (14, 21) serving to maintain a said control signal (13) until the next control signal is generated 13. . Device according to claim 5, characterized in that the control circuit (7) further comprises logic switching means (16) having as their inputs a state signal (15) originating from the memory element (14, 21) and the local clock signal (6), and as output the derived clock signal (8). Device according to claim 6, characterized in that said logical switching means (16) perform an EXOR function. Device according to any one of claims 2 to 7, characterized in that said logic circuit (11) can perform an EXOR function with respect to said first and second signals (9,10). Device according to any one of claims 2 to 8, characterized in that the logic circuit is provided with an additional input for receiving a blocking signal, thereby preventing the formation of said control signal (13), which blocking signal of the control circuit originates. Device according to any one of claims 5-9, characterized in that said logic circuit (11) comprises a second memory element (28) with inputs of an impure control signal (29) and said blocking signal, and one output of which control signal (13) and another output can supply a reset signal for deactivating said sensor circuit (5). 8301625