NL7510904A - Woordgroepsprioriteitsinrichting. - Google Patents

Woordgroepsprioriteitsinrichting.

Info

Publication number
NL7510904A
NL7510904A NL7510904A NL7510904A NL7510904A NL 7510904 A NL7510904 A NL 7510904A NL 7510904 A NL7510904 A NL 7510904A NL 7510904 A NL7510904 A NL 7510904A NL 7510904 A NL7510904 A NL 7510904A
Authority
NL
Netherlands
Prior art keywords
word group
group priority
priority development
development
word
Prior art date
Application number
NL7510904A
Other languages
English (en)
Dutch (nl)
Original Assignee
Philips Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Nv filed Critical Philips Nv
Priority to NL7510904A priority Critical patent/NL7510904A/xx
Priority to DE2640357A priority patent/DE2640357C2/de
Priority to US05/723,154 priority patent/US4059850A/en
Priority to GB38014/76A priority patent/GB1564530A/en
Priority to FR7627708A priority patent/FR2325146A1/fr
Priority to JP51110884A priority patent/JPS5856174B2/ja
Publication of NL7510904A publication Critical patent/NL7510904A/xx

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/123—Replacement control using replacement algorithms with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
    • G06F12/125—Replacement control using replacement algorithms with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list being generated by decoding an array or storage

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Memory System (AREA)
NL7510904A 1975-09-17 1975-09-17 Woordgroepsprioriteitsinrichting. NL7510904A (nl)

Priority Applications (6)

Application Number Priority Date Filing Date Title
NL7510904A NL7510904A (nl) 1975-09-17 1975-09-17 Woordgroepsprioriteitsinrichting.
DE2640357A DE2640357C2 (de) 1975-09-17 1976-09-08 Wortgruppenprioritätsanordnung
US05/723,154 US4059850A (en) 1975-09-17 1976-09-14 Memory system word group priority device with least-recently used criterion
GB38014/76A GB1564530A (en) 1975-09-17 1976-09-14 Information storage systems including a priority device
FR7627708A FR2325146A1 (fr) 1975-09-17 1976-09-15 Dispositif a priorites pour groupes de mots
JP51110884A JPS5856174B2 (ja) 1975-09-17 1976-09-17 ワ−ド群優先順位割当装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL7510904A NL7510904A (nl) 1975-09-17 1975-09-17 Woordgroepsprioriteitsinrichting.

Publications (1)

Publication Number Publication Date
NL7510904A true NL7510904A (nl) 1977-03-21

Family

ID=19824477

Family Applications (1)

Application Number Title Priority Date Filing Date
NL7510904A NL7510904A (nl) 1975-09-17 1975-09-17 Woordgroepsprioriteitsinrichting.

Country Status (6)

Country Link
US (1) US4059850A (xx)
JP (1) JPS5856174B2 (xx)
DE (1) DE2640357C2 (xx)
FR (1) FR2325146A1 (xx)
GB (1) GB1564530A (xx)
NL (1) NL7510904A (xx)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2816838C2 (de) * 1978-04-18 1982-06-09 Siemens AG, 1000 Berlin und 8000 München Verfahren und Prioritätssteuereinheit zum Zuordnen von Prioritäten
US4373179A (en) * 1978-06-26 1983-02-08 Fujitsu Limited Dynamic address translation system
EP0085672B1 (en) * 1981-08-18 1989-02-01 International Business Machines Corporation Thrashing reduction in demand accessing of a data base through an lru paging buffer pool
US4422145A (en) * 1981-10-26 1983-12-20 International Business Machines Corporation Thrashing reduction in demand accessing of a data base through an LRU paging buffer pool
US4523206A (en) * 1982-03-03 1985-06-11 Sperry Corporation Cache/disk system with writeback regulation relative to use of cache memory
US4569017A (en) * 1983-12-22 1986-02-04 Gte Automatic Electric Incorporated Duplex central processing unit synchronization circuit
US4648033A (en) * 1984-09-07 1987-03-03 International Business Machines Corporation Look-aside buffer LRU marker controller
US5355480A (en) * 1988-12-23 1994-10-11 Scientific-Atlanta, Inc. Storage control method and apparatus for an interactive television terminal
CA2014797A1 (en) * 1989-04-20 1990-10-20 Elizabeth A. Smith Storage control method and apparatus for an interactive television terminal
JPH05970U (ja) * 1991-06-19 1993-01-08 周 金木 発電風車
US6078995A (en) * 1996-12-26 2000-06-20 Micro Magic, Inc. Methods and apparatus for true least recently used (LRU) bit encoding for multi-way associative caches
FR2778258A1 (fr) * 1998-04-29 1999-11-05 Texas Instruments France Controleur d'acces de trafic dans une memoire, systeme de calcul comprenant ce controleur d'acces et procede de fonctionnement d'un tel controleur d'acces
US6338120B1 (en) 1999-02-26 2002-01-08 International Business Machines Corporation Apparatus for cache use history encoding and decoding including next lru and next mru and method therefor
US8332598B2 (en) * 2005-06-23 2012-12-11 Intel Corporation Memory micro-tiling request reordering
US7587521B2 (en) * 2005-06-23 2009-09-08 Intel Corporation Mechanism for assembling memory access requests while speculatively returning data
US7765366B2 (en) * 2005-06-23 2010-07-27 Intel Corporation Memory micro-tiling
US7558941B2 (en) * 2005-06-30 2009-07-07 Intel Corporation Automatic detection of micro-tile enabled memory
US8253751B2 (en) 2005-06-30 2012-08-28 Intel Corporation Memory controller interface for micro-tiled memory access
US8878860B2 (en) * 2006-12-28 2014-11-04 Intel Corporation Accessing memory using multi-tiling
US11392499B2 (en) 2020-09-18 2022-07-19 Kioxia Corporation Dynamic buffer caching of storage devices

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE629069A (xx) * 1962-03-05
US3427592A (en) * 1964-11-12 1969-02-11 Ibm Data processing system
US3573750A (en) * 1968-03-29 1971-04-06 Nippon Electric Co High-speed memory system
US3541529A (en) * 1969-09-22 1970-11-17 Ibm Replacement system
US3699533A (en) * 1970-10-29 1972-10-17 Rca Corp Memory system including buffer memories
US3836889A (en) * 1973-03-23 1974-09-17 Digital Equipment Corp Priority interruption circuits for digital computer systems
FR116049A (xx) * 1975-03-20

Also Published As

Publication number Publication date
GB1564530A (en) 1980-04-10
FR2325146A1 (fr) 1977-04-15
JPS5856174B2 (ja) 1983-12-13
DE2640357A1 (de) 1977-04-07
DE2640357C2 (de) 1984-09-27
US4059850A (en) 1977-11-22
JPS5236432A (en) 1977-03-19
FR2325146B1 (xx) 1982-04-23

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Legal Events

Date Code Title Description
BV The patent application has lapsed