NL7215718A - - Google Patents

Info

Publication number
NL7215718A
NL7215718A NL7215718A NL7215718A NL7215718A NL 7215718 A NL7215718 A NL 7215718A NL 7215718 A NL7215718 A NL 7215718A NL 7215718 A NL7215718 A NL 7215718A NL 7215718 A NL7215718 A NL 7215718A
Authority
NL
Netherlands
Application number
NL7215718A
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of NL7215718A publication Critical patent/NL7215718A/xx

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/84—Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/58—Random or pseudo-random number generators
    • G06F7/582—Pseudo-random number generators
    • G06F7/584—Pseudo-random number generators using finite field arithmetic, e.g. using a linear feedback shift register
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/58—Indexing scheme relating to groups G06F7/58 - G06F7/588
    • G06F2207/581—Generating an LFSR sequence, e.g. an m-sequence; sequence may be generated without LFSR, e.g. using Galois Field arithmetic
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/58—Indexing scheme relating to groups G06F7/58 - G06F7/588
    • G06F2207/583—Serial finite field implementation, i.e. serial implementation of finite field arithmetic, generating one new bit or trit per step, e.g. using an LFSR or several independent LFSRs; also includes PRNGs with parallel operation between LFSR and outputs

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
NL7215718A 1971-11-22 1972-11-21 NL7215718A (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US20079671A 1971-11-22 1971-11-22
US00278271A US3818242A (en) 1971-11-22 1972-08-07 High-speed logic circuits

Publications (1)

Publication Number Publication Date
NL7215718A true NL7215718A (fr) 1973-05-24

Family

ID=26896096

Family Applications (1)

Application Number Title Priority Date Filing Date
NL7215718A NL7215718A (fr) 1971-11-22 1972-11-21

Country Status (9)

Country Link
US (1) US3818242A (fr)
JP (1) JPS5242578B2 (fr)
AU (1) AU475185B2 (fr)
BE (1) BE791651A (fr)
CA (1) CA971636A (fr)
FR (1) FR2160931B1 (fr)
GB (1) GB1412978A (fr)
NL (1) NL7215718A (fr)
SE (1) SE380954B (fr)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5814931Y2 (ja) * 1975-12-19 1983-03-25 東芝テック株式会社 デンキソウジキノシユウジンソウチ
JPS5358461U (fr) * 1976-10-20 1978-05-18
JPS53163866U (fr) * 1977-05-30 1978-12-21
JPS53163972U (fr) * 1977-05-31 1978-12-22
JPS53163973U (fr) * 1977-05-31 1978-12-22
JPS53163976U (fr) * 1977-05-31 1978-12-22
JPS53163956U (fr) * 1977-05-31 1978-12-22
JPS53166561U (fr) * 1977-06-02 1978-12-27
JPS541970U (fr) * 1977-06-07 1979-01-08
JPS54131384U (fr) * 1979-01-25 1979-09-12
JPS5673907A (en) * 1979-11-21 1981-06-19 Hitachi Ltd Frequency divider
JPS56164751U (fr) * 1980-05-12 1981-12-07
US4348597A (en) * 1980-05-27 1982-09-07 Weber Harold J Latchup resistant pseudorandom binary sequence generator
US4531022A (en) * 1983-01-13 1985-07-23 International Standard Electric Corporation Device for generating binary digit pseudo-random sequences
US5073909A (en) * 1990-07-19 1991-12-17 Motorola Inc. Method of simulating the state of a linear feedback shift register

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3040192A (en) * 1958-07-30 1962-06-19 Ibm Logic, exclusive-or, and shift register circuits utilizing directly connected cascade transistors in "tree" configuration
NL289174A (fr) * 1962-06-25
US3316503A (en) * 1964-05-18 1967-04-25 North American Aviation Inc Digital phase-modulated generator
CH422061A (de) * 1964-10-07 1966-10-15 Hasler Ag Elektronische Zählkette
US3327226A (en) * 1964-11-16 1967-06-20 Hewlett Packard Co Anticoincidence circuit
US3458825A (en) * 1966-02-17 1969-07-29 Philips Corp Bistable trigger circuit comprising two relatively complementary outputs and two inputs and a clock pulse input
US3598908A (en) * 1968-08-30 1971-08-10 Ampex Digitally controlled lap dissolver
JPS5028144B1 (fr) * 1968-11-01 1975-09-12
US3617903A (en) * 1969-09-29 1971-11-02 Andrew E Trolio Condition responsive high-voltage gate

Also Published As

Publication number Publication date
FR2160931B1 (fr) 1974-01-11
DE2257277B2 (de) 1976-07-15
JPS5242578B2 (fr) 1977-10-25
AU475185B2 (en) 1976-08-12
GB1412978A (en) 1975-11-05
US3818242A (en) 1974-06-18
DE2257277A1 (de) 1973-05-30
CA971636A (en) 1975-07-22
AU4894372A (en) 1974-05-16
FR2160931A1 (fr) 1973-07-06
SE380954B (sv) 1975-11-17
BE791651A (fr) 1973-03-16
JPS4863666A (fr) 1973-09-04

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