NL7015137A - - Google Patents

Info

Publication number
NL7015137A
NL7015137A NL7015137A NL7015137A NL7015137A NL 7015137 A NL7015137 A NL 7015137A NL 7015137 A NL7015137 A NL 7015137A NL 7015137 A NL7015137 A NL 7015137A NL 7015137 A NL7015137 A NL 7015137A
Authority
NL
Netherlands
Application number
NL7015137A
Other versions
NL158325B (nl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of NL7015137A publication Critical patent/NL7015137A/xx
Publication of NL158325B publication Critical patent/NL158325B/xx

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/02—Contacts, special
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/049—Equivalence and options
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/051—Etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/053—Field effect transistors fets
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/978—Semiconductor device manufacturing: process forming tapered edges on substrate or adjacent layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
NL7015137.A 1969-10-31 1970-10-15 Halfgeleiderinrichting, omvattende een halfgeleiderlichaam met een veelvoud van geleidende lagen, met een vooraf bepaald patroon van geleiders. NL158325B (nl)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US87453569A 1969-10-31 1969-10-31

Publications (2)

Publication Number Publication Date
NL7015137A true NL7015137A (fr) 1971-05-04
NL158325B NL158325B (nl) 1978-10-16

Family

ID=25364025

Family Applications (1)

Application Number Title Priority Date Filing Date
NL7015137.A NL158325B (nl) 1969-10-31 1970-10-15 Halfgeleiderinrichting, omvattende een halfgeleiderlichaam met een veelvoud van geleidende lagen, met een vooraf bepaald patroon van geleiders.

Country Status (9)

Country Link
US (1) US3586922A (fr)
JP (2) JPS55907B1 (fr)
BE (1) BE758160A (fr)
CA (1) CA921616A (fr)
CH (1) CH514236A (fr)
DE (1) DE2047799C3 (fr)
FR (1) FR2065609B1 (fr)
GB (1) GB1308359A (fr)
NL (1) NL158325B (fr)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3675319A (en) * 1970-06-29 1972-07-11 Bell Telephone Labor Inc Interconnection of electrical devices
US3774079A (en) * 1971-06-25 1973-11-20 Ibm Monolithically fabricated tranistor circuit with multilayer conductive patterns
US3892606A (en) * 1973-06-28 1975-07-01 Ibm Method for forming silicon conductive layers utilizing differential etching rates
JPS5334484A (en) * 1976-09-10 1978-03-31 Toshiba Corp Forming method for multi layer wiring
NL7701559A (nl) * 1977-02-15 1978-08-17 Philips Nv Het maken van schuine hellingen aan metaal- patronen, alsmede substraat voor een geinte- greerde schakeling voorzien van een dergelijk patroon.
US4178674A (en) * 1978-03-27 1979-12-18 Intel Corporation Process for forming a contact region between layers of polysilicon with an integral polysilicon resistor
JPS57112027A (en) * 1980-12-29 1982-07-12 Fujitsu Ltd Manufacture of semiconductor device
FR2525389A1 (fr) * 1982-04-14 1983-10-21 Commissariat Energie Atomique Procede de positionnement d'une ligne d'interconnexion sur un trou de contact electrique d'un circuit integre
US4703392A (en) * 1982-07-06 1987-10-27 General Electric Company Microstrip line and method for fabrication
US4600663A (en) * 1982-07-06 1986-07-15 General Electric Company Microstrip line
DE3232837A1 (de) * 1982-09-03 1984-03-08 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen einer 2-ebenen-metallisierung fuer halbleiterbauelemente, insbesondere fuer leistungshalbleiterbauelemente wie thyristoren
DE3806287A1 (de) * 1988-02-27 1989-09-07 Asea Brown Boveri Aetzverfahren zur strukturierung einer mehrschicht-metallisierung
US6522762B1 (en) * 1999-09-07 2003-02-18 Microtronic A/S Silicon-based sensor system
KR101557942B1 (ko) * 2014-01-08 2015-10-12 주식회사 루멘스 발광 소자 패키지 및 발광 소자 패키지의 제조 방법

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL251064A (fr) * 1955-11-04
US3382568A (en) * 1965-07-22 1968-05-14 Ibm Method for providing electrical connections to semiconductor devices
US3515607A (en) * 1967-06-21 1970-06-02 Western Electric Co Method of removing polymerised resist material from a substrate
US3510728A (en) * 1967-09-08 1970-05-05 Motorola Inc Isolation of multiple layer metal circuits with low temperature phosphorus silicates

Also Published As

Publication number Publication date
CA921616A (en) 1973-02-20
DE2047799A1 (de) 1971-05-06
BE758160A (fr) 1971-04-01
CH514236A (de) 1971-10-15
JPS55907B1 (fr) 1980-01-10
FR2065609A1 (fr) 1971-07-30
DE2047799B2 (de) 1980-06-19
US3586922A (en) 1971-06-22
NL158325B (nl) 1978-10-16
JPS5543251B1 (fr) 1980-11-05
GB1308359A (en) 1973-02-21
FR2065609B1 (fr) 1976-05-28
DE2047799C3 (de) 1981-12-03

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Legal Events

Date Code Title Description
V1 Lapsed because of non-payment of the annual fee
NL80 Information provided on patent owner name for an already discontinued patent

Owner name: FAIRCHILD