NL7010710A - - Google Patents

Info

Publication number
NL7010710A
NL7010710A NL7010710A NL7010710A NL7010710A NL 7010710 A NL7010710 A NL 7010710A NL 7010710 A NL7010710 A NL 7010710A NL 7010710 A NL7010710 A NL 7010710A NL 7010710 A NL7010710 A NL 7010710A
Authority
NL
Netherlands
Application number
NL7010710A
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of NL7010710A publication Critical patent/NL7010710A/xx

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802Instruction prefetching
    • G06F9/3808Instruction prefetching for instruction reuse, e.g. trace cache, branch target cache
    • G06F9/381Loop buffering
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/325Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for loops, e.g. loop detection or loop counter

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
NL7010710A 1969-07-25 1970-07-20 NL7010710A (cg-RX-API-DMAC7.html)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US84491469A 1969-07-25 1969-07-25

Publications (1)

Publication Number Publication Date
NL7010710A true NL7010710A (cg-RX-API-DMAC7.html) 1971-01-27

Family

ID=25293955

Family Applications (1)

Application Number Title Priority Date Filing Date
NL7010710A NL7010710A (cg-RX-API-DMAC7.html) 1969-07-25 1970-07-20

Country Status (8)

Country Link
US (1) US3593306A (cg-RX-API-DMAC7.html)
JP (1) JPS5133383B1 (cg-RX-API-DMAC7.html)
BE (1) BE753749A (cg-RX-API-DMAC7.html)
DE (1) DE2036729A1 (cg-RX-API-DMAC7.html)
FR (1) FR2055396A5 (cg-RX-API-DMAC7.html)
GB (1) GB1315832A (cg-RX-API-DMAC7.html)
NL (1) NL7010710A (cg-RX-API-DMAC7.html)
SE (1) SE353804B (cg-RX-API-DMAC7.html)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4896260A (en) * 1970-12-28 1990-01-23 Hyatt Gilbert P Data processor having integrated circuit memory refresh
US4825364A (en) * 1970-12-28 1989-04-25 Hyatt Gilbert P Monolithic data processor with memory refresh
US5410621A (en) * 1970-12-28 1995-04-25 Hyatt; Gilbert P. Image processing system having a sampled filter
US3891972A (en) * 1972-06-09 1975-06-24 Hewlett Packard Co Synchronous sequential controller for logic outputs
US4001787A (en) * 1972-07-17 1977-01-04 International Business Machines Corporation Data processor for pattern recognition and the like
US4097920A (en) * 1976-12-13 1978-06-27 Rca Corporation Hardware control for repeating program loops in electronic computers
US4195339A (en) * 1977-08-04 1980-03-25 Ncr Corporation Sequential control system
US4298927A (en) * 1978-10-23 1981-11-03 International Business Machines Corporation Computer instruction prefetch circuit
US4309753A (en) * 1979-01-03 1982-01-05 Honeywell Information System Inc. Apparatus and method for next address generation in a data processing system
US4525673A (en) * 1979-12-26 1985-06-25 Varian Associates, Inc. NMR spectrometer incorporating a re-entrant FIFO
US4481608A (en) * 1979-12-26 1984-11-06 Varian Associates, Inc. Reentrant asynchronous FIFO
US4375676A (en) * 1979-12-26 1983-03-01 Varian Associates, Inc. Feedback FIFO for cyclic data acquisition and instrument control
US4626988A (en) * 1983-03-07 1986-12-02 International Business Machines Corporation Instruction fetch look-aside buffer with loop mode control
FR2557712B1 (fr) * 1983-12-30 1988-12-09 Trt Telecom Radio Electr Processeur pour traiter des donnees en fonction d'instructions provenant d'une memoire-programme
US4764861A (en) * 1984-02-08 1988-08-16 Nec Corporation Instruction fpefetching device with prediction of a branch destination for each branch count instruction
JPS6341932A (ja) * 1985-08-22 1988-02-23 Nec Corp 分岐命令処理装置
US4933837A (en) * 1986-12-01 1990-06-12 Advanced Micro Devices, Inc. Methods and apparatus for optimizing instruction processing in computer systems employing a combination of instruction cache and high speed consecutive transfer memories
JP2690921B2 (ja) * 1987-12-25 1997-12-17 株式会社日立製作所 情報処理装置
US5594908A (en) * 1989-12-27 1997-01-14 Hyatt; Gilbert P. Computer system having a serial keyboard, a serial display, and a dynamic memory with memory refresh
JPH07160585A (ja) * 1993-12-13 1995-06-23 Hitachi Ltd 低電力データ処理装置
JPH07200292A (ja) * 1993-12-28 1995-08-04 Mitsubishi Electric Corp パイプライン式プロセッサ
US6085315A (en) * 1997-09-12 2000-07-04 Siemens Aktiengesellschaft Data processing device with loop pipeline
US6256683B1 (en) * 1998-12-23 2001-07-03 Bops, Inc. Methods and apparatus for providing direct memory access control
US6898693B1 (en) 2000-11-02 2005-05-24 Intel Corporation Hardware loops
US20100122066A1 (en) * 2008-11-12 2010-05-13 Freescale Semiconductor, Inc. Instruction method for facilitating efficient coding and instruction fetch of loop construct
JP6268402B2 (ja) * 2014-07-24 2018-01-31 日本電子株式会社 磁気共鳴測定装置
CN115113110A (zh) * 2022-07-03 2022-09-27 上海创感传感技术有限公司 一种磁传感器装置、测量方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3251041A (en) * 1962-04-17 1966-05-10 Melpar Inc Computer memory system
NL302252A (cg-RX-API-DMAC7.html) * 1963-01-03
US3290656A (en) * 1963-06-28 1966-12-06 Ibm Associative memory for subroutines
US3337851A (en) * 1963-12-09 1967-08-22 Burroughs Corp Memory organization for reducing access time of program repetitions
US3348211A (en) * 1964-12-10 1967-10-17 Bell Telephone Labor Inc Return address system for a data processor
US3466613A (en) * 1967-01-13 1969-09-09 Ibm Instruction buffering system

Also Published As

Publication number Publication date
BE753749A (fr) 1970-12-31
SE353804B (cg-RX-API-DMAC7.html) 1973-02-12
FR2055396A5 (cg-RX-API-DMAC7.html) 1971-05-07
DE2036729A1 (de) 1971-02-04
GB1315832A (en) 1973-05-02
JPS5133383B1 (cg-RX-API-DMAC7.html) 1976-09-18
US3593306A (en) 1971-07-13

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Legal Events

Date Code Title Description
BV The patent application has lapsed