NL6712927A - - Google Patents

Info

Publication number
NL6712927A
NL6712927A NL6712927A NL6712927A NL6712927A NL 6712927 A NL6712927 A NL 6712927A NL 6712927 A NL6712927 A NL 6712927A NL 6712927 A NL6712927 A NL 6712927A NL 6712927 A NL6712927 A NL 6712927A
Authority
NL
Netherlands
Application number
NL6712927A
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of NL6712927A publication Critical patent/NL6712927A/xx

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30189—Instruction operation extension or modification according to execution mode, e.g. mode flag
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/483—Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G06F9/30014—Arithmetic instructions with variable precision
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016—Decoding the operand specifier, e.g. specifier format
    • G06F9/30167—Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/448—Execution paradigms, e.g. implementations of programming paradigms
    • G06F9/4482—Procedural
    • G06F9/4484—Executing subprograms
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/3808—Details concerning the type of numbers or the way they are handled
    • G06F2207/3812—Devices capable of handling different types of numbers
    • G06F2207/3816—Accepting numbers of variable word length

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computing Systems (AREA)
  • Computer Hardware Design (AREA)
  • Nonlinear Science (AREA)
  • Executing Machine-Instructions (AREA)
NL6712927A 1966-09-23 1967-09-21 NL6712927A (xx)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US58160366A 1966-09-23 1966-09-23

Publications (1)

Publication Number Publication Date
NL6712927A true NL6712927A (xx) 1968-03-25

Family

ID=24325831

Family Applications (1)

Application Number Title Priority Date Filing Date
NL6712927A NL6712927A (xx) 1966-09-23 1967-09-21

Country Status (5)

Country Link
US (1) US3434114A (xx)
DE (1) DE1549480A1 (xx)
FR (1) FR1554667A (xx)
NL (1) NL6712927A (xx)
SE (1) SE330276B (xx)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3577130A (en) * 1969-10-03 1971-05-04 Fairchild Camera Instr Co Means for limiting field length of computed data
US3648246A (en) * 1970-04-16 1972-03-07 Ibm Decimal addition employing two sequential passes through a binary adder in one basic machine cycle
US3742198A (en) * 1971-03-19 1973-06-26 Bell Telephone Labor Inc Apparatus for utilizing a three-field word to represent a floating point number
US3725649A (en) * 1971-10-01 1973-04-03 Raytheon Co Floating point number processor for a digital computer
US4305134A (en) * 1979-11-08 1981-12-08 Honeywell Information Systems Inc. Automatic operand length control of the result of a scientific arithmetic operation
US4295203A (en) * 1979-11-09 1981-10-13 Honeywell Information Systems Inc. Automatic rounding of floating point operands
USRE33629E (en) * 1980-02-13 1991-07-02 Intel Corporation Numeric data processor
US4484259A (en) * 1980-02-13 1984-11-20 Intel Corporation Fraction bus for use in a numeric data processor
US4338675A (en) * 1980-02-13 1982-07-06 Intel Corporation Numeric data processor
US4758972A (en) * 1986-06-02 1988-07-19 Raytheon Company Precision rounding in a floating point arithmetic unit
US9146706B2 (en) * 2006-05-05 2015-09-29 Qualcomm Incorporated Controlled-precision iterative arithmetic logic unit
US9710384B2 (en) * 2008-01-04 2017-07-18 Micron Technology, Inc. Microprocessor architecture having alternative memory access paths
US8561037B2 (en) * 2007-08-29 2013-10-15 Convey Computer Compiler for generating an executable comprising instructions for a plurality of different instruction sets
US9015399B2 (en) 2007-08-20 2015-04-21 Convey Computer Multiple data channel memory module architecture
US8095735B2 (en) 2008-08-05 2012-01-10 Convey Computer Memory interleave for heterogeneous computing
US8423745B1 (en) 2009-11-16 2013-04-16 Convey Computer Systems and methods for mapping a neighborhood of data to general registers of a processing element
US10430190B2 (en) 2012-06-07 2019-10-01 Micron Technology, Inc. Systems and methods for selectively controlling multithreaded execution of executable code segments
US10042607B2 (en) 2016-08-22 2018-08-07 Altera Corporation Variable precision floating-point multiplier
US10055195B2 (en) 2016-09-20 2018-08-21 Altera Corporation Variable precision floating-point adder and subtractor
US10204906B2 (en) 2016-12-16 2019-02-12 Intel Corporation Memory with single-event latchup prevention circuitry
US11010131B2 (en) 2017-09-14 2021-05-18 Intel Corporation Floating-point adder circuitry with subnormal support
US10970042B2 (en) 2017-11-20 2021-04-06 Intel Corporation Integrated circuits with machine learning extensions
US11175892B2 (en) 2017-11-20 2021-11-16 Intel Corporation Integrated circuits with machine learning extensions
US10871946B2 (en) 2018-09-27 2020-12-22 Intel Corporation Methods for using a multiplier to support multiple sub-multiplication operations
US10732932B2 (en) 2018-12-21 2020-08-04 Intel Corporation Methods for using a multiplier circuit to support multiple sub-multiplications using bit correction and extension

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3022006A (en) * 1959-01-26 1962-02-20 Burroughs Corp Floating-point computer
NL277572A (xx) * 1961-04-26
US3244864A (en) * 1962-12-10 1966-04-05 Burroughs Corp Subtraction unit for a digital computer
US3290493A (en) * 1965-04-01 1966-12-06 North American Aviation Inc Truncated parallel multiplication

Also Published As

Publication number Publication date
US3434114A (en) 1969-03-18
SE330276B (xx) 1970-11-09
DE1549480A1 (de) 1971-01-21
FR1554667A (xx) 1969-01-24

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