NL6614649A - - Google Patents
Info
- Publication number
- NL6614649A NL6614649A NL6614649A NL6614649A NL6614649A NL 6614649 A NL6614649 A NL 6614649A NL 6614649 A NL6614649 A NL 6614649A NL 6614649 A NL6614649 A NL 6614649A NL 6614649 A NL6614649 A NL 6614649A
- Authority
- NL
- Netherlands
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/14—Digital recording or reproducing using self-clocking codes
- G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
- G11B20/1407—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol
- G11B20/1419—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol to or from biphase level coding, i.e. to or from codes where a one is coded as a transition from a high to a low level during the middle of a bit cell and a zero is encoded as a transition from a low to a high level during the middle of a bit cell or vice versa, e.g. split phase code, Manchester code conversion to or from biphase space or mark coding, i.e. to or from codes where there is a transition at the beginning of every bit cell and a one has no second transition and a zero has a second transition one half of a bit period later or vice versa, e.g. double frequency code, FM code
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Computer Networks & Wireless Communication (AREA)
- Manipulation Of Pulses (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP40068617A JPS507415B1 (xx) | 1965-11-09 | 1965-11-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| NL6614649A true NL6614649A (xx) | 1967-05-10 |
Family
ID=13378882
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| NL6614649A NL6614649A (xx) | 1965-11-09 | 1966-10-18 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US3588718A (xx) |
| JP (1) | JPS507415B1 (xx) |
| DE (1) | DE1462585B2 (xx) |
| FR (1) | FR1498961A (xx) |
| GB (1) | GB1149959A (xx) |
| NL (1) | NL6614649A (xx) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| BE793395A (fr) * | 1971-12-28 | 1973-06-28 | Siemens Ag | Procede de reduction de l'amplitude de dephasage d'un signal a modulation de phase |
| US3851252A (en) * | 1972-12-29 | 1974-11-26 | Ibm | Timing recovery in a digitally implemented data receiver |
| JPS49110257A (xx) * | 1973-02-20 | 1974-10-21 | ||
| JPS5016462A (xx) * | 1973-06-11 | 1975-02-21 | ||
| JPS5074404A (xx) * | 1973-10-30 | 1975-06-19 | ||
| DE2428367C2 (de) * | 1974-06-12 | 1979-06-21 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Schaltungsanordnung zum Begrenzen der Übertragungsgeschwindigkeit von Datensignalen |
| JPS5179321A (ja) * | 1974-12-31 | 1976-07-10 | Fujitsu Ltd | Jikisaiseihoshiki |
| JPS54104230A (en) * | 1978-02-03 | 1979-08-16 | Sony Corp | Processing circuit for vertical synchronizing signal |
| JPS56167041U (xx) * | 1980-05-13 | 1981-12-10 | ||
| DE3533467C2 (de) * | 1985-09-19 | 1999-01-21 | Tandberg Data | Verfahren und Anordnung zum störsicheren Erkennen von in Datensignalen enthaltenen Daten |
-
1965
- 1965-11-09 JP JP40068617A patent/JPS507415B1/ja active Pending
-
1966
- 1966-10-18 NL NL6614649A patent/NL6614649A/xx unknown
- 1966-11-08 DE DE19661462585 patent/DE1462585B2/de active Pending
- 1966-11-09 GB GB50326/66A patent/GB1149959A/en not_active Expired
- 1966-11-09 FR FR83140A patent/FR1498961A/fr not_active Expired
-
1970
- 1970-01-09 US US1620A patent/US3588718A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| US3588718A (en) | 1971-06-28 |
| FR1498961A (fr) | 1967-10-20 |
| JPS507415B1 (xx) | 1975-03-25 |
| GB1149959A (en) | 1969-04-23 |
| DE1462585A1 (de) | 1969-02-20 |
| DE1462585B2 (de) | 1971-01-28 |