NL6507897A - - Google Patents

Info

Publication number
NL6507897A
NL6507897A NL6507897A NL6507897A NL6507897A NL 6507897 A NL6507897 A NL 6507897A NL 6507897 A NL6507897 A NL 6507897A NL 6507897 A NL6507897 A NL 6507897A NL 6507897 A NL6507897 A NL 6507897A
Authority
NL
Netherlands
Application number
NL6507897A
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of NL6507897A publication Critical patent/NL6507897A/xx

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50Adding; Subtracting
    • G06F7/505Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
    • G06F7/575Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Optimization (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Executing Machine-Instructions (AREA)
  • Supports For Pipes And Cables (AREA)
NL6507897A 1964-06-19 1965-06-18 NL6507897A (en:Method)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US376348A US3400259A (en) 1964-06-19 1964-06-19 Multifunction adder including multistage carry chain register with conditioning means

Publications (1)

Publication Number Publication Date
NL6507897A true NL6507897A (en:Method) 1965-12-20

Family

ID=23484665

Family Applications (1)

Application Number Title Priority Date Filing Date
NL6507897A NL6507897A (en:Method) 1964-06-19 1965-06-18

Country Status (10)

Country Link
US (1) US3400259A (en:Method)
JP (1) JPS4913887B1 (en:Method)
AT (1) AT282237B (en:Method)
BE (1) BE665632A (en:Method)
CH (1) CH455342A (en:Method)
DE (1) DE1499192A1 (en:Method)
DK (1) DK129813B (en:Method)
GB (1) GB1114503A (en:Method)
NL (1) NL6507897A (en:Method)
NO (1) NO120907B (en:Method)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3617720A (en) * 1967-09-12 1971-11-02 Bell Telephone Labor Inc Fast fourier transform using hierarchical store
US3711693A (en) * 1971-06-30 1973-01-16 Honeywell Inf Systems Modular bcd and binary arithmetic and logical system
USH1970H1 (en) 1971-07-19 2001-06-05 Texas Instruments Incorporated Variable function programmed system
US3956620A (en) * 1974-11-26 1976-05-11 Texas Instruments Incorporated Adder with carry enable for bit operations in an electric digital calculator

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3028088A (en) * 1956-09-25 1962-04-03 Ibm Multipurpose logical operations
US3199939A (en) * 1962-05-08 1965-08-10 Herman A Stern Phosphor deposition

Also Published As

Publication number Publication date
CH455342A (fr) 1968-06-28
US3400259A (en) 1968-09-03
GB1114503A (en) 1968-05-22
JPS4913887B1 (en:Method) 1974-04-03
DK129813C (en:Method) 1975-06-23
BE665632A (en:Method) 1965-10-18
AT282237B (de) 1970-06-25
DE1499192A1 (de) 1970-01-15
NO120907B (en:Method) 1970-12-21
DK129813B (da) 1974-11-18

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