NL213776A - - Google Patents

Info

Publication number
NL213776A
NL213776A NL213776DA NL213776A NL 213776 A NL213776 A NL 213776A NL 213776D A NL213776D A NL 213776DA NL 213776 A NL213776 A NL 213776A
Authority
NL
Netherlands
Application number
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Publication of NL213776A publication Critical patent/NL213776A/xx

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/5052—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination using carry completion detection, either over all stages or at sample stages only
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
    • G06F7/5016—Half or full adders, i.e. basic adder cells for one denomination forming at least one of the output signals directly from the minterms of the input signals, i.e. with a minimum number of gate levels
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/509—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination for multiple operands, e.g. digital integrators
    • G06F7/5095—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination for multiple operands, e.g. digital integrators word-serial, i.e. with an accumulator-register
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/386—Special constructional features
    • G06F2207/3884—Pipelining

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
  • Image Processing (AREA)
NL213776D 1957-01-16 NL213776A (en:Method)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL213776 1957-01-16

Publications (1)

Publication Number Publication Date
NL213776A true NL213776A (en:Method)

Family

ID=19750828

Family Applications (2)

Application Number Title Priority Date Filing Date
NL213776D NL213776A (en:Method) 1957-01-16
NL98963D NL98963C (en:Method) 1957-01-16

Family Applications After (1)

Application Number Title Priority Date Filing Date
NL98963D NL98963C (en:Method) 1957-01-16

Country Status (6)

Country Link
US (1) US3098153A (en:Method)
CH (1) CH363823A (en:Method)
DE (1) DE1094020B (en:Method)
FR (1) FR1192991A (en:Method)
GB (1) GB876988A (en:Method)
NL (2) NL98963C (en:Method)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3277449A (en) * 1961-12-12 1966-10-04 Shooman William Orthogonal computer
US3299261A (en) * 1963-12-16 1967-01-17 Ibm Multiple-input memory accessing apparatus
FR2627297B1 (fr) * 1988-02-15 1990-07-20 Gallay Philippe Multiplieur de nombres binaires a tres grand nombre de bits
US6088800A (en) * 1998-02-27 2000-07-11 Mosaid Technologies, Incorporated Encryption processor with shared memory interconnect
JP3487783B2 (ja) 1999-03-17 2004-01-19 富士通株式会社 加算回路、それを利用した積分回路、及びそれを利用した同期確立回路
US10831446B2 (en) * 2018-09-28 2020-11-10 Intel Corporation Digital bit-serial multi-multiply-and-accumulate compute in memory

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2585630A (en) * 1949-05-03 1952-02-12 Remington Rand Inc Digit shifting circuit
NL94981C (en:Method) * 1950-05-18
US2879001A (en) * 1956-09-10 1959-03-24 Weinberger Arnold High-speed binary adder having simultaneous carry generation
US2907526A (en) * 1956-11-02 1959-10-06 Ibm Electronic accumulator

Also Published As

Publication number Publication date
NL98963C (en:Method)
GB876988A (en) 1961-09-06
US3098153A (en) 1963-07-16
DE1094020B (de) 1960-12-01
CH363823A (de) 1962-08-15
FR1192991A (fr) 1959-10-29

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