NL2034850A - Substrate-removed GaN-H EMT Chip Combined with Packaging Process and Preparation Method thereof - Google Patents

Substrate-removed GaN-H EMT Chip Combined with Packaging Process and Preparation Method thereof Download PDF

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NL2034850A
NL2034850A NL2034850A NL2034850A NL2034850A NL 2034850 A NL2034850 A NL 2034850A NL 2034850 A NL2034850 A NL 2034850A NL 2034850 A NL2034850 A NL 2034850A NL 2034850 A NL2034850 A NL 2034850A
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layer
gan
substrate
packaging process
chip
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NL2034850A
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Bai Junchun
Cheng Bin
Jia Yong
Wang Fujin
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Jiangsu Chipport Semiconductor Co Ltd
Shanghai Gejing Semiconductor Co Ltd
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Publication of NL2034850A publication Critical patent/NL2034850A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/7806—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices involving the separation of the active layers from a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1066—Gate region of field-effect devices with PN junction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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Abstract

The invention relates a substrate-removed GaN-HEIVIT chip combined with packaging process and preparation method thereof. And the chip comprises a packaging bracket (300). And a die bonding layer (301), a high thermal 5 conductivity voltage-resistant layer (302), a buffer layer (101), a channel layer (102) and a barrier layer (103) are sequentially arranged on the packaging bracket (300). The barrier layer (103) is provided with a p-GaN layer (104), a source electrode (105) and a drain electrode (106), and the p-GaN layer (104) is provided with a gate electrode (107); insulating layers (108) are arranged 10 between the source electrode (105) and the p-GaN layer (104) and the gate (107), and between the drain electrode (106) and the p-GaN layer (104) and the gate electrode (107). The substrate is removed, and a high thermal conductivity voltage-resistant layer is prepared on the back of the epitaxial layer, which can effectively improve the voltage-resistant and heat-dissipating 15 capabilities of the HEIVIT chip; in addition, it is combined with the packaging process, omitting the chip substrate preparation and bonding process, which can effectively reduce the cost, further reduce the thermal resistance and improve the yield. 20

Description

Substrate-removed GaN-HEMT Chip Combined with Packaging Process and Preparation Method thereof
TECHNICAL FIELD
The invention belongs to the technical field of microelectronic devices, and relates to a GaN-HEMT (high electron mobility transistor) chip and a preparation method thereof, in particular to a substrate-removed GaN-HEMT chip combined with packaging process and a preparation method thereof.
BACKGROUND
At present, GaN-HEMT{GaN-based high electron mobility transistor) chip has been gradually applied to consumer electronics power supply, electric vehicles, high-speed rail, power stations, aerospace and other application fields. GaN-HEMT is a high electron mobility transistor device which forms a strong two-dimensional electron gas at the heterojunction based on the inherent characteristics of GaN material. It has the advantages of high power density, high frequency, fast start-up, long service life, high efficiency, energy saving and environmental protection.
At present, the main technical route of GaN-HEMT market is to grow GaN-
HEMT epitaxial layers on silicon, sapphire, SiC and other substrates, and then make into HEMT chips. GaN-HEMT prepared on silicon substrate has serious lattice mismatch, and the quality of epitaxial layer can't compare with sapphire and SiC. And silicon is easy to break down, so it is not suitable for application in high voltage scenes. GaN-HEMT technology on SiC substrate cant be widely used in the field of consumer electronics because of its expensive substrate. The common sapphire substrate GaN-HEMT technology is economical, high withstand voltage, and the quality of GaN epitaxial layer is good. However, due to the low thermal conductivity of sapphire substrate, it can not be used in high power density.
In view of the above technical defects in the current technology, it is necessary to provide a novel GaN-HEMT chip and its preparation method to overcome the above defects.
SUMMARY
In order to overcome the defects of the current technology, the invention provides a substrate-removed GaN-HEMT chip combined with packaging process and a preparation method thereof. The substrate is removed, and a high thermal conductivity voltage-resistant layer is prepared on the back of the epitaxial layer, which can effectively improve the voltage-resistant and heat-dissipating capabilities of the HEMT chip; in addition, it is combined with the packaging process, omitting the chip substrate preparation and bonding process, which can effectively reduce the cost, further reduce the thermal resistance and improve the yield.
In order to achieve the above purposes, the present invention provides the following technical scheme:
A substrate-removed GaN-HEMT chip combined with packaging process comprises a packaging bracket, wherein, a die bonding layer, a high thermal conductivity voltage-resistant layer, a buffer layer, a channel layer and a barrier layer are sequentially arranged on the packaging bracket. The barrier layer is provided with a p-GaN layer, a source electrode and a drain electrode, and the p-GaN layer is provided with a gate electrode; insulating layers are arranged between the source electrode and the p-GaN layer and the gate, and between the drain electrode and the p-GaN layer and the gate electrode.
Preferably, the packaging bracket is a circuit bracket with ceramic, metal or printed circuit board as the base material.
Preferably, the thickness of the packaging bracket is 300 um~1000 um.
Preferably, the thermal conductivity of the high thermal conductivity voltage- resistant layer is more than 170 W/(m kK).
Preferably, the high thermal conductivity voltage-resistant layer is made of
AIN, SiC or adamas, and the thickness is 10 um~50 um.
Preferably, the die bonding layer is made of Ag glue, or AuSn or PbSn eutectic alloy, or sintered Ag or insulating glue, and the thickness is 1 um~100 um.
Preferably, the total thickness of the buffer layer, the channel layer, the barrier layer and the p-GaN layer is 0.1 um~50 um.
Preferably, the source electrode, the drain electrode and the gate electrode are formed by stacking a Ti layer, an Al layer, a Ni layer and/or an Au layer, and the thicknesses are 30 nm~500 nm.
Preferably, the insulating layer is made of SiN, AIN, Al2O3 or SiOz, and its thickness is 30 nm~500 nm.
In addition, the invention also provides a preparation method for the substrate-removed GaN-HEMT chip combined with packaging process, wherein, it comprises the following steps: 1) grow the buffer layer, the channel layer, the barrier layer and a p-type GaN layer on a substrate sequentially; 2) etch chip areas arranged repeatedly on the P-type GaN layer; 3) etch off part of the P-type GaN layer in each chip area to expose the barrier layer; 4) prepare the source electrode and the drain electrode on the exposed barrier layer; 5) prepare the gate electrode on the remaining P-type GaN layer; 6) prepare the insulating layers respectively between the source electrode v{105) and the p-GaN layer and the gate electrode and between the drain electrode and the p-GaN layer and the gate electrode; 7) manufacture bonding wire areas respectively on the source electrode, the drain electrode and the gate electrode; 8) bond the temporary base board to the insulating layer; 9) strip the substrate from the buffer layer; 10) prepare a high thermal conductivity voltage-resistant layer on the bottom surface of the buffer layer; 11) cut to obtain the GaN-HEMT chip base materials; 12) fix the high thermal conductivity voltage-resistant layer of the GaN-HEMT chip base material to the packaging bracket through the die bonding layer; and 13) remove the temporary base board to obtain the substrate-removed
GaN-HEMT chips combined with packaging process.
Compared with the current technology, the substrate-removed GaN-HEMT chip combined with packaging process and the preparation method thereof have one or more of the following beneficial technical effects: 1. The GaN-HEMT chip of the present invention is directly die-bonded to the packaging bracket, which saves the investment in the transfer base board and bonding process of the HEMT chip, and is beneficial to reducing the cost and improving the yield; at the same time, it also reduces the thermal resistance, which is beneficial to chip heat dissipation. 2. According to the GaN-HEMT chip in the present invention, the substrates poor in thermal conductivity or non-resistant in high voltage is removed, and a high thermal conductivity voltage-resistant layer is prepared, which can greatly improve the voltage-resistant capability and power density of the GaN-
HEMT chip, and give consideration to both economic benefits and quality. 3. In the preparation process of the GaN-HEMT chip of the present invention, the common bonding process in the semiconductor industry and the mature substrate removal process in the LED industry are adopted, which can ensure the process stability and obtain products with high yield, high reliability and low cost.
BRIEF DESCRIPTION OF THE FIGURES
Fig. 1 is a schematic structural diagram of the substrate-removed GaN-HEMT chip combined with packaging process of the present invention.
Fig. 2 is a schematic diagram of the structure after the buffer layer, the channel layer, the barrier layer and the P-type GaN layer are sequentially grown on a substrate.
Fig. 3 is a schematic structural diagram after etching part of the P-type GaN layer in each chip area on the basis of Fig. 2.
Fig. 4 is a schematic diagram of the structure after the drain electrode, source electrode and gate electrode are prepared on the basis of Fig. 3.
Fig. 5 is a schematic diagram of the structure after the insulating layer is prepared on the basis of Fig. 4.
Fig. 6 is a schematic diagram of the structure after the temporary base board is bonded on the basis of Fig. 5.
Fig. 7 is a schematic diagram of the structure after the substrate is stripped on the basis of Fig. 6. 5 Fig. 8 is a schematic diagram of the structure after the high thermal conductivity and voltage-resistant layer is prepared on the basis of Fig. 7.
Fig. 9 is a schematic structural diagram of a single GaN-HEMT chip substrate obtained after separation on the basis of Fig. 8.
Fig. 10 is a schematic diagram of the structure after the packaging bracket is fixed through the die bonding layer on the basis of Fig. ©.
DETAILED DESCRIPTION OF THE INVENTION
The present invention will be further described with reference to the attached figures and embodiments, and the contents of the embodiments shall not be taken as limitations on the protection scope of the present invention.
The invention relates to the substrate-removed GaN-HEMT chip combined with packaging process and the preparation method thereof. The substrate is removed by adopting a mature temporary bonding technology in the semiconductor industry, a mature substrate removal technology in the LED industry and a device preparation technology combined with the packaging process, and a high thermal conductivity voltage-resistant layer is prepared on the back surface, which is directly die-bonded to the packaging bracket (reducing thermal resistance), so that the voltage-resistant capability and heat dissipation capability of the GaN-HEMT chip can be significantly improved, and the investment of the base board and bonding process in the chip preparation process can be saved, so as to achieve better economic benefits and technological advantages.
As shown in Flg. 1, the substrate-removed GaN-HEMT chip combined with packaging process in the invention comprises a packaging bracket 300.
The packaging bracket 300 is a circuit bracket with ceramic, metal or printed circuit board (PCB) as the base material.
Preferably, the thickness of the packaging bracket 300 is 300 um~1000 um.
With the packaging bracket 300, the transfer substrate and bonding process investment of the GaN-HEMT chip are saved, which is beneficial to reducing the cost and improving the yield. At the same time, the packaging bracket 300 is made of a material with high thermal conductivity and strong breakdown field, which also reduces the thermal resistance and is beneficial to chip heat dissipation.
A die bonding layer 301, a high thermal conductivity voltage-resistant layer 302, a buffer layer 101, a channel layer 102 and a barrier layer 103 are sequentially arranged on the packaging bracket 300. The barrier layer 103 is provided with a p-GaN layer 104, a source electrode 105 and a drain electrode 106, and the p-GaN layer 104 is provided with a gate electrode 107.
Preferably, the die bonding layer 301 is made of Ag glue, or AuSn or PbSn eutectic alloy, or sintered Ag or insulating glue, and the thickness is 1 um~100 um. Therefore, the packaging bracket 300 can be better die-bonded to the high thermal conductivity and voltage-resistant layer 302 through the die bonding layer 301.
More preferably, the thermal conductivity of the high thermal conductivity voltage-resistant layer 302 is more than 170 W/(m_ k). And the high thermal conductivity voltage-resistant layer 302 is made of AIN, SiC or adamas, and the thickness is 10 um~50 um. Because the high thermal conductivity and voltage-resistant layer 302 is made of AIN, adamas, SiC and other materials with high thermal conductivity and strong breakdown field, the voltage- resistant ability and heat dissipation ability of the GaN-HEMT chip are stronger.
In the present invention, the buffer layer 101, the channel layer 102, the barrier layer 103 and the p-GaN layer 104 together constitute the epitaxial layer of the GaN-HEMT chip.
Similar to the current technology, the buffer layer 101, the channel layer 102, the barrier layer 103 and the p-GaN layer 104 are made of different compositions of GaN materials.
Preferably, the total thickness of the buffer layer 101, the channel layer 102, the barrier layer 103 and the p-GaN layer 104, that is, the thickness of the epitaxial layer is 0.1 um~50 um.
Meanwhile, similar to the current technology, the source electrode 105, the drain electrode 106, and the gate electrode 107 may be formed by stacking multiple layers of metals such as a Ti layer, an Al layer, a Ni layer, and/or an
Au layer, and the thicknesses are 30 nm to 500 nm.
In the invention, insulating layers 108 are arranged between the source electrode 105 and the p-GaN layer 104 and the gate 107, and between the drain electrode 106 and the p-GaN layer 104 and the gate electrode 107.
Preferably, the insulating layer 108 is made of high insulating dielectric materials such as SiN, AIN, Al203 or SiO2, and its thickness is 30 nm~500 nm.
Next, with reference to Figs. 2~10, the preparation method for the substrate- removed GaN-HEMT chip combined with packaging process of the present invention is introduced, which includes the following steps: 1. As shown in Fig. 2, grow the buffer layer 101, the channel layer 102, the barrier layer 103 and a p-type GaN layer 104 on a substrate 100 sequentially, so as to form epitaxial layer. 2. Etch chip areas arranged repeatedly on the P-type GaN layer 104.
Since multiple chips can be generated by one epitaxial layer, etching is performed on the P-type GaN layer 104 to etch chip areas, so as to make the single chip in each chip area. 3. As shown in Fig. 3, etch off part of the P-type GaN layer 104 in each chip area to expose the barrier layer 103.
In Fig. 3, two rows of chip areas are shown, so it can be seen that two parts of the remaining P-type GaN layer 104 are not etched. 4. As shown in Fig. 4, prepare the source electrode 105 and the drain electrode 106 on the exposed barrier layer 103, and prepare the gate electrode 107 on the remaining P-type GaN layer 104.
Of course, in each chip area, the source electrode 105, the drain electrode 106 and the gate electrode 107 should be prepared.
5. As shown in Fig. 5, prepare the insulating layers 108 respectively between the source electrode v105 and the p-GaN layer 104 and the gate electrode 107 and between the drain electrode 106 and the p-GaN layer 104 and the gate electrode 107. 6. Manufacture bonding wire areas respectively on the source electrode 105, the drain electrode 106 and the gate electrode 107, so as to facilitate the production of bonding wires. 7. As shown in Fig. 6, bond the temporary base board 200 to the insulating layer 108.
Preferably, the temporary base board 200 has the same size as the substrate 100. 8. As shown in Fig. 7, strip the substrate 100 from the buffer layer 101. 9. As shown in Fig. 8, prepare a high thermal conductivity voltage-resistant layer 302 on the bottom surface of the buffer layer 101. 10. Cut to obtain the GaN-HEMT chip base materials as shown in Fig. 9. 11. As shown in Fig. 10, fix the high thermal conductivity voltage-resistant layer 302 of the GaN-HEMT chip base material to the packaging bracket 300 through the die bonding layer 301. 12. Remove the temporary base board 200 to obtain the substrate-removed
GaN-HEMT chips combined with packaging process as shown in Fig. 1.
In the following, how to prepare a substrate-removed GaN-HEMT chip combined with packaging process is described in detail with a specific embodiment, so that people in the field can prepare the GaN-HEMT chip according to the description of the present invention. The specific preparation process is as follows: 1. Grow 3 um GaN-HEMT epitaxial layers (including buffer layer 101, channel layer 102, barrier layer 103 and p-GaN layer 104) on sapphire substrate 100 by MOCVD epitaxial technology. 2. Use acetone and isopropanol respectively to do organic cleaning for 5 min to remove organic dirt. 3. Then use SPM solution (mixed solution of sulfuric acid and hydrogen peroxide) for pickling to remove inorganic metal dirt and organic dirt.
4. Flush and spin-dry, use positive photoresist lithography technology to make patterns, and use ICP to etch square ring isolation channels with a side length of 2 mm and a width of 0.05 mm, which cover the whole surface in order to form repeated chip areas, so as to make chips in each chip area.
5. Remove photoresist, rinse and spin dry, and use positive photoresist lithography technology to make source electrode and drain electrode patterns.
6. Etch the P-type GaN corresponding to the source electrode and drain electrode patterns by ICP dry method to expose the barrier layer.
7. Remove the photoresist, use negative photoresist lithography technology to make source electrode and drain electrode patterns, and use metal evaporation process to evaporate Ti/AlI/NI/Au/Ti metal, and strip and remove the glue to obtain the source electrode and drain electrode.
8. Use a rapid annealing furnace to anneal at 850°C and Nz for 30 s so as to form a good ohmic contact between the source electrode and the drain electrode.
9. Spin-coat negative photoresist, use negative photoresist lithography technology to get gate electrode pattern on P-type GaN, and use metal evaporation process to evaporate Ni/Au/Ti metal, and strip the glue to get gate electrode.
10. Use PECVD to grow 200 nm of SiN insulating layer.
11. Spin-coat positive photoresist, use positive photoresist lithography technology, make wire hole patterns with a diameter of 200 um on the source electrode, drain electrode and gate electrode, and etch the SiN insulating layer and the metal Ti on the surface by ICP dry method to form the bonding wire area.
12. Take a silicon wafer with the same shape as the sapphire substrate and the thickness of 300 um as the temporary base board. 13. Spin-coat thermosetting adhesive with a thickness of 5 um at 1000r/min on the surfaces of temporary base board and insulating layer, bake at 300°C for 30 minu, align the thermosetting adhesive surface and put it into temporary bonding equipment, vacuumize, apply 500 kg pressure and 300°C, and bond for 10 min. 14. Use a blade to remove the glue overflowing from the edge, and clean the temporary base board and the back of sapphire with a dust-free cloth dipped in ethanol. 15. Use grinding, rough polishing and CMP processes to remove the rough surface of sapphire by about 30 um, thus forming a mirror polishing effect. 16. According to the measured total thickness and the known thickness of the base board, epitaxial layer and sapphire, calculate the focal distance of laser focusing, and scan the sapphire surface with a laser of 260~300 nm to vaporize a layer of GaN with several tens of nm in contact with sapphire and
GaN, thus stripping and removing the sapphire substrate. 17. Use a solution of hydrochloric acid:water of 1:1 to soak, remove the stripped residual Ga metal, and rinse to dry. 18. Use PVD equipment, sputter reactively 30 um of AIN on the back of the buffer layer, which constitutes a high thermal conductivity and voltage- resistant layer. 19. Use laser to cut and split along the isolation channels in step 4 to obtain a single GaN-HEMT chip base material. 20. Fix the AIN surface of the single GaN-HEMT chip substrate to the packaging bracket with Ag glue and bake it at 200°C in nitrogen for 3 h to fix it to the packaging bracket. 21. Heat to about 300°C to soften the temporary bonding adhesive and remove the temporary base board. 22. Put it into the glue removal solution, heat it at 60°C for 30 min, and remove the residual temporary bonding adhesive, so as to obtain the substrate- removed GaN-HEMT chip combined with packaging process.
The GaN-HEMT chip of the present invention is directly die-bonded to the packaging bracket, which saves the investment in the transfer base board and bonding process of the HEMT chip, and is beneficial to reducing the cost and improving the yield; at the same time, it also reduces the thermal resistance, which is beneficial to chip heat dissipation. In addition, the substrates poor in thermal conductivity or non-resistant in high voltage is removed, and a high thermal conductivity voltage-resistant layer is prepared, which can greatly improve the voltage-resistant capability and power density of the GaN-HEMT chip, and give consideration to both economic benefits and quality. And in the preparation process of the GaN-HEMT chip of the present invention, the common bonding process in the semiconductor industry and the mature substrate removal process in the LED industry are adopted, which can ensure the process stability and obtain products with high yield, high reliability and low cost.
Finally, it should be explained that the above embodiments are only used to illustrate the technical scheme of the present invention, but not to limit the protection scope of the present invention. According to the idea of the present invention, those skilled in the field can modify or replace the technical scheme of the present invention equally without departing from the essence and scope of the technical scheme of the present invention.

Claims (10)

ConclusiesConclusions 1. Een van het substraat verwijderde GaN-HEMT-chip gecombineerd met het verpakkingsproces omvat een verpakkingsbeugel (300), waarin een die- bindingslaag (301), een spanningsbestendige laag met hoge thermische geleidbaarheid (302), een bufferlaag (101) een kanaallaag (102) en een barrièrelaag (103) zijn achtereenvolgens aangebracht op de verpakkingsbeugel (300); de barrièrelaag (103) is voorzien van een p-GaN-laag (104), een bronelektrode (105) en een afvoerelektrode (106), en de p-GaN-laag (104) is voorzien van een poortelektrode (107) ; isolerende lagen (108) zijn aangebracht tussen de source-elektrode (105) en de p-GaN-laag (104) en de gate (107), en tussen de drain-elektrode (106) en de p-GaN-laag (104) en de gate elektrode (107).1. A GaN-HEMT chip removed from the substrate combined with the packaging process includes a packaging bracket (300), in which a die-bonding layer (301), a high thermal conductivity stress-resistant layer (302), a buffer layer (101) and a channel layer (102) and a barrier layer (103) are successively applied to the packaging bracket (300); the barrier layer (103) includes a p-GaN layer (104), a source electrode (105) and a drain electrode (106), and the p-GaN layer (104) includes a gate electrode (107); insulating layers (108) are provided between the source electrode (105) and the p-GaN layer (104) and the gate (107), and between the drain electrode (106) and the p-GaN layer (104 ) and the gate electrode (107). 2. De van substraat verwijderde GaN-HEMT-chip gecombineerd met verpakkingsproces volgens conclusie 1, waarbij de verpakkingsbeugel (300) een circuitbeugel is met keramiek, metaal of printplaat als basismateriaal.The substrate-removed GaN-HEMT chip combined with packaging process according to claim 1, wherein the packaging bracket (300) is a circuit bracket with ceramic, metal or printed circuit board as a base material. 3. De van substraat verwijderde GaN-HEMT-chip gecombineerd met verpakkingsproces volgens conclusie 2, waarbij de dikte van de verpakkingssteun (300) is 300 um~1000 um. The substrate-removed GaN-HEMT chip combined with packaging process according to claim 2, wherein the thickness of the packaging support (300) is 300 µm~1000 µm. 4 De van substraat verwijderde GaN-HEMT-chip gecombineerd met het verpakkingsproces volgens conclusie 3, waarbij de thermische geleidbaarheid van de spanningsbestendige laag (302) met hoge thermische geleidbaarheid meer is dan 170 W/(m.k).The substrate-removed GaN-HEMT chip combined with the packaging process according to claim 3, wherein the thermal conductivity of the high thermal conductivity stress-resistant layer (302) is more than 170 W/(m.k). 5. De van substraat verwijderde GaN-HEMT-chip gecombineerd met het verpakkingsproces volgens conclusie 4, waarbij de spanningsbestendige laag (302) met hoge thermische geleidbaarheid is gemaakt van AIN, SiC of adamas, en de dikte is 10 um-50 um.The substrate-removed GaN-HEMT chip combined with the packaging process according to claim 4, wherein the high thermal conductivity voltage-resistant layer (302) is made of AIN, SiC or adamas, and the thickness is 10 µm-50 µm. 6. De van substraat verwijderde GaN-HEMT-chip gecombineerd met het verpakkingsproces volgens conclusie 5, waarbij de matrijsbindingslaag (301) is gemaakt van Ag-lijm, of AuSn- of PbSn-eutectische legering, of gesinterd Ag of isolerende lijm, en de dikte is 1 um~100 um.The substrate-removed GaN-HEMT chip combined with the packaging process according to claim 5, wherein the die bonding layer (301) is made of Ag adhesive, or AuSn or PbSn eutectic alloy, or sintered Ag or insulating adhesive, and the thickness is 1um~100um. 7. De van substraat verwijderde GaN-HEMT-chip gecombineerd met het verpakkingsproces volgens conclusie 6, waarbij de totale dikte van de bufferlaag (101), de kanaallaag (102), de barrièrelaag (103) en de p-GaN-laag (104) is 0,1 um-The substrate-removed GaN-HEMT chip combined with the packaging process according to claim 6, wherein the total thickness of the buffer layer (101), the channel layer (102), the barrier layer (103) and the p-GaN layer (104) ) is 0.1 um- um.um. 8. De van substraat verwijderde GaN-HEMT-chip gecombineerd met het verpakkingsproces volgens conclusie 7, waarbij de bronelektrode (105), de afvoerelektrode (106) en de poortelektrode (107) worden gevormd door een Ti-laag te stapelen, een Al-laag, een Ni-laag en/of een Au-laag, en de diktes zijn 30 nm-500 nm.The substrate-removed GaN-HEMT chip combined with the packaging process according to claim 7, wherein the source electrode (105), the drain electrode (106) and the gate electrode (107) are formed by stacking a Ti layer, an Al layer, a Ni layer and/or an Au layer, and the thicknesses are 30 nm-500 nm. 9. De van substraat verwijderde GaN-HEMT-chip gecombineerd met het verpakkingsproces volgens conclusie 8, waarbij de isolerende laag (108) gemaakt is van SiN, AIN, A1203 of SiOz, en de dikte 30 nm-500 nmThe substrate-removed GaN-HEMT chip combined with the packaging process according to claim 8, wherein the insulating layer (108) is made of SiN, AIN, Al2 O3 or SiO2, and the thickness is 30nm-500nm 10. Bereidingswerkwijze voor de van substraat verwijderde GaN-HEMT-chip gecombineerd met verpakkingsproces volgens een van de conclusies 1-9, waarbij deze de volgende stappen omvat: 1) achtereenvolgens de bufferlaag (101), de kanaallaag (102), de barrièrelaag (103) en een p-type GaN-laag (104) op een substraat (100) laten groeien; 2) ets chipgebieden herhaaldelijk gerangschikt op de GaN-laag van het P-type (104); 3) ets een deel van de P-type GaN-laag (104) weg in elk chipgebied om de barrièrelaag (103) bloot te leggen; 4) bereid de bronelektrode (105) en de afvoerelektrode (106) voor op de blootgestelde barrièrelaag (103); 5) bereid de poortelektrode (107) voor op de overblijvende GaN-laag van het P-type (104); 6) bereid de isolerende lagen (108) voor respectievelijk tussen de bronelektrode v(105) en de p-GaN-laag (104) en de poortelektrode (107) en tussen de afvoerelektrode (106) en de p-GaN-laag (104 ) en de poortelektrode (107); 7) vervaardiging van verbindingsdraadgebieden respectievelijk op de bronelektrode (105), de afvoerelektrode (108) en de poortelektrode (107); 8) hecht de tijdelijke basisplaat (200) aan de isolatielaag (108); 9) strip het substraat (100) van de bufferlaag (101); 10) maak een spanningsbestendige laag (302) met hoge thermische geleidbaarheid op het onderoppervlak van de bufferlaag (101); 11) gesneden om de GaN-HEMT-chipbasismaterialen te verkrijgen; 12) fixeer de spanningsbestendige laag met hoge thermische geleidbaarheid (302) van het GaN-HEMT-chipbasismateriaal aan de verpakkingsbeugel (300) door de die-bindingslaag (301); 13) verwijder de tijdelijke basiskaart (200) om de van substraat verwijderde GaN-HEMT-chips gecombineerd met verpakkingsproces te verkrijgen.Preparation method for the GaN-HEMT chip removed from substrate combined with packaging process according to any one of claims 1 to 9, comprising the following steps: 1) successively the buffer layer (101), the channel layer (102), the barrier layer ( 103) and growing a p-type GaN layer (104) on a substrate (100); 2) etch chip areas repeatedly arranged on the P-type GaN layer (104); 3) etch away a portion of the P-type GaN layer (104) in each chip area to expose the barrier layer (103); 4) prepare the source electrode (105) and drain electrode (106) for the exposed barrier layer (103); 5) prepare the gate electrode (107) for the remaining P-type GaN layer (104); 6) prepare the insulating layers (108) respectively between the source electrode v(105) and the p-GaN layer (104) and the gate electrode (107) and between the drain electrode (106) and the p-GaN layer (104 ) and the gate electrode (107); 7) fabrication of bond wire regions on the source electrode (105), the drain electrode (108) and the gate electrode (107) respectively; 8) bond the temporary base plate (200) to the insulation layer (108); 9) strip the substrate (100) from the buffer layer (101); 10) create a high thermal conductivity stress-resistant layer (302) on the bottom surface of the buffer layer (101); 11) cut to obtain the GaN-HEMT chip base materials; 12) fix the high thermal conductivity stress-resistant layer (302) of the GaN-HEMT chip base material to the packaging bracket (300) through the die bond layer (301); 13) remove the temporary base card (200) to obtain the substrate-removed GaN-HEMT chips combined with packaging process.
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