NL2026008B1

NL2026008B1 - Electrical power converter

Info

Publication number: NL2026008B1
Application number: NL2026008A
Authority: NL
Inventors: Zhang Daifei; Everts Jordi; Guacci Mattia; Walter Kolar Johann
Original assignee: Eth Zuerich; Prodrive Tech Bv
Priority date: 2020-07-06
Filing date: 2020-07-06
Publication date: 2022-03-11

Abstract

Electrical converter for converting between an AC signal having at least three phases and a DC signal, comprising at least three phase terminals, a first DC terminal and a second DC terminal, a first converter stage operable to convert between an AC current at the at least three phase terminals and a first DC current at the first and second intermediate nodes (p, n), a second converter stage operable to convert between a first DC signal at third and fourth intermediate nodes (q, r) and a second DC signal at the first and second DC terminals, wherein the second converter stage comprises a middle voltage node (m) between the first and second DC terminals, a first filter stage comprising a capacitor network (C…) operably coupled to each of the three phase terminals, wherein the capacitor network comprises a star-point (k), a DC link connecting the first intermediate node (p) to the third intermediate node (q) and the second intermediate node (n) to the fourth intermediate node (r), wherein the DC link comprises a common mode filter, the common mode filter comprising a common mode capacitor (COM ) connecting the middle voltage node (m) to the star-point (k).

Description

Electrical power converter Technical field

[0001] The present invention is related to electrical converters allowing to convert between a three phase AC signal and a DC signal. The electrical converter comprises an AC/DC stage and a DC/DC stage.

Background art

[0002] High power and high efficiency battery chargers, enabling fast charging of electric vehicles (EVs), are of crucial importance for a fast growth of the EV market. Moreover, in case EV batteries serve as distributed energy storage elements to support the grid operation, EV chargers must allow bidirectional power conversion. The AC/DC front-end is a main element of an EV battery charging system, and must cover a wide output voltage range to adapt to different battery voltages.

[0003] Three-phase buck-boost rectifiers are known. The buck-boost topology is simply a buck rectifier with a boost-stage added at the output end of the inductor, as illustrated in Fig. 6.5 in [3]. The two input switches rectify the AC line into a switched voltage, converted next into a DC current by the high-frequency inductor. The output switch then feeds this current into the load.

[0004] In [4], a three-phase buck-boost current source inverter is described, comprising a buck-type DC/DC converter input stage and a boost-type three-phase current DC-link inverter output stage. The current source inverter is implemented with two different modulation schemes, namely conventional pulse-width modulation and two-third pulse-width modulation (2/3-PWM). The 2/3-PWM reduces conduction and switching losses and can be applied in a subset of the buck-mode operation region. In the remainder of the buck-mode operation region, conventional PWM (3/3-PWM) and 2/3-PWM are alternated depending on the instantaneous value of the output voltage.

[0005] References:

[1] C. A. Bendall and W. A. Peterson, An EV On-Board Battery Charger, in Proc. of the IEEE Applied Power Electronics Conference and Exposition (APEC), San Jose, CA, USA, 1996.

[2] US 2012/0286740, S. Loudot, B. Briane, O. Ploix, and A. Villeneuve, Fast Charging Device for an Electric Vehicle.

[3] K. D. T. Ngo, Topology and Analysis in PWM Inversion, Rectification, and Cycloconversion, Ph.D. dissertation, California Institute of Technology, May 1984.

[4] M. Guacci, D. Zhang, M. Tatic, D. Bortis, J. W. Kolar, Y. Kinoshita, H. Ishida, Three- Phase Two-Third-PWM Buck-Boost Current Source Inverter System Employing Dual- Gate Monolithic Bidirectional GaN e-FETs, CPSS Transactions on Power Electronics and Applications, vol. 4, no. 4, pp. 339-354, December 2019.

[5] M. Baumann, J. W. Kolar, A Novel Control Concept for Reliable Operation of a Three-Phase Three-Switch Buck-Type Unity-Power-Factor Rectifier With Integrated Boost Output Stage Under Heavily Unbalanced Mains Condition, /EEE Transactions on industrial Electronics, vol. 52, no. 2, pp. 399-409, April 2005.

[6] Q. Lei, B. Wang, and F. Z. Peng, Unified Space Vector PWM Control for Current Source Inverter, in Proc. of the IEEE Energy Conversion Congress and Exposition (ECCE USA), Raleigh, NC, USA, 2012.

[7] D. Menzi, D. Bortis, J. W. Kolar, Three-Phase Two-Phase-Clamped Boost-Buck Unity Power Factor Rectifier Employing Novel Variable DC Link Voltage Input Current Control, Proceedings of the 2" IEEE International Power Electronics and Application Conference and Exposition (PEAC), Shenzhen, China, November 4-7, 2018.

[8] CH 698490, J. W. Kolar, Vorrichtung zur Regelung der Teilausgangsspannungen eines Dreipunkt-Hochsetzstellers.

Summary of the invention

[0006] There is a need in the art to provide a buck-boost electrical converter of the above described kind, allowing an extended converter output voltage range. There is a need in the art to provide such an electrical converter allowing improved suppression of noise at the DC-side.

[0007] According to a first aspect of the invention, there is therefore provided an electrical converter as set out in the appended claims.

[0008] An electrical converter according to the invention comprises at least three phase terminals, a first DC terminal and a second DC terminal, a first converter stage and a second converter stage, and a DC link connecting the first and second converter stages.

[0009] The first converter stage is operably coupled to the at least three phase terminals and comprises a first intermediate node and a second intermediate node, wherein the converter stage is operable to convert between an AC current at the at least three phase terminals and a first DC current at the first and second intermediate nodes. The first converter stage is advantageously implemented as a buck-type bridge converter, advantageously as a current-source converter, in particular a (bidirectional) current-source rectifier.

[0010] The second converter stage is operably coupled to the first DC terminal and the second DC terminal and comprises a third intermediate node and a fourth intermediate node. The second converter stage is operable to convert between a first DC signal, preferably a current signal, at the third and fourth intermediate nodes and a second DC signal, preferably a voltage signal, at the first and second DC terminals, wherein the second converter stage comprises a middle voltage node between the first and second DC terminals. The second converter stage is advantageously implemented as, or comprises, a boost circuit, in particular comprising a first boost circuit and a second boost circuit stacked between the first DC terminal and the second DC terminal, wherein the middle voltage node is a common node of the first and second boost circuits. Either one, or both the first boost circuit and the second boost circuit can be a multi-level boost circuit comprising at least three voltage nodes.

[0011] The DC link connects the first intermediate node to the third intermediate node, and the second intermediate node to the fourth intermediate node.

The electrical converter further comprises a first filter stage comprising a capacitor network operably coupled to each of the three phase terminals, wherein the capacitor network comprises a star-point. The DC link comprises a common mode filter, the common mode filter comprising a common mode capacitor connecting the middle voltage node to the star-point. Advantageously, the common mode filter comprises a common mode filter choke operably coupled to the first intermediate node and the second intermediate node, the third intermediate node and the fourth intermediate node. Advantageously, the DC link comprises at least one differential mode inductor operably coupled to the first intermediate node and the third intermediate node and/or operably coupled to the second intermediate node and the fourth intermediate node.

[0012] The electrical converter topology according to the present invention combines one or more of the following advantages. First, a three-level second converter stage is employed to extend the converter output voltage range without compromising its performance, but instead reducing the occurring switching losses and/or minimizing the number of magnetic components and the size of the DC- link inductor. Second, a novel integrated common mode (CM) filter is applied to suppress the CM noise at the DC-side.

[0013] Advantageously, the control structure is capable to seamlessly transition between conventional 3/3-PWM and 2/3-PWM [6].

[0014] As an advantage, the electrical converter according to aspects of the invention can be implemented with a control structure as discussed in this document capable to automatically select the optimal operating modes for different output voltage values. Compared to the conventional voltage source approach, the converter system introduced herein offers several advantages, i.e. a reduction of switching losses enabled by a variable DC-link current control strategy (synergetic control) and by a sinusoidally varying switched voltage.

[0015] Accordingly, in one advantageous aspect, this invention disclosure proposes a three-phase current DC-link split-output buck-three-level-boost AC/DC converter, formed by a three-phase buck-type current source rectifier (CSR)-stage and a subsequent boost-type DC/DC-stage. This power converter is advantageously bidirectional and can operate under non-ideal three-phase mains conditions, e.g., in case of harmonics distortion, over- or under-voltage events, voltage dips and phase voltage interruptions. Moreover, both stages are advantageously operated synergetically to provide a wide output voltage range. Electrical converters according to the invention are as well applicable in non-isolated on-board chargers protected by an on-board ground fault circuit interrupter [1]. In this case, the switches of the traction inverter and the stator coils of the motor, already present on-board of the EV, can be used as DC/DC-stage and DC-link inductor, respectively, aiming for a compact and low-cost solution [2].

[0016] Furthermore, this invention can also be applied to other applications areas requiring a three-phase AC/DC PFC rectifier front-end either for providing a widely adjustable DC output/load voltage from a constant three-phase mains or for providing a constant DC output voltage despite a large tolerance of the mains voltage. An example for the latter case would be datacenter power supplies, which (besides wide input voltage range) should feature continuous power supply and sinusoidal input current also in case of a mains phase loss which is possible due to the boost output stage of the proposed system. Moreover, the system could be employed for supplying a non-isolated converter stage supplying a single-side grounded load, as frequently given for envelope tracking power supplies of linear amplifiers, e.g. used for testing purposes.

[0017] Finally, it should be highlighted, that actually two individually controlled DC outputs are generated, which could be different in reference voltage values and power delivery to the individual loads, i.e. the total power taken from the three-phase can be freely distributed to the two outputs. Accordingly, e.g. two isolated DC/DC load converters could be supplied from the two DC outputs, which would allow a design with power semiconductors of lower voltage rating and the utilization of transformers with lower turns ratio in case a low output voltage needs to be generated like for telecom applications.

[0018] According to a second aspect of the invention, there is provided an electric motor drive system as set out in the appended claims.

[0019] According to a third aspect of the invention, there is provided a battery charging system as set out in the appended claims.

5 [0020] According to a fourth aspect of the invention, there is provided a method of converting between an AC signal having at least three phases at three or more phase nodes and a DC signal at a high node and a low node. The method comprises switching by pulse width modulation between the at least three phase nodes and the high node and the low node to obtain a switched voltage signal across the high node and low node. A period of the switched voltage signal comprises a zero voltage level portion obtained by connecting the phase node having a smallest absolute instantaneous voltage value of the at least three phases of the AC signal to both the high node and the low node. The method reduces the common mode noise generated by the PWM switching without increasing switching losses or degrading a differential mode performance. Advantageously, the switched voltage signal comprises a second voltage level portion obtained by connecting the phase node having the highest instantaneous voltage value of the at least three phases of the AC signal to the high node, and connecting the phase node having the lowest instantaneous voltage value of the at least three phases of the AC signal to the low node. Advantageously, the switched voltage signal comprises a third voltage level portion obtained by connecting the phase node having the smallest absolute instantaneous voltage value to the high node, and connecting the phase node having the lowest instantaneous voltage value of the at least three phases of the AC signal to the low node, or vice versa.

[0021] According to a fifth aspect of the invention, there is provided a method of converting between an AC signal having at least three phases at three or more phase nodes and a DC signal at a high node and a low node. The method comprises switching by pulse width modulation between the at least three phase nodes and the high node and the low node to convert between the AC signal and the DC signal. The switching comprises switching between active states in which a connection is made between two of the at least three phases and the high node and the low node and zero states in which the high node and the low node are short circuited, in particular in which both high and low node are both connected to only one of the at least three phases. At least one, preferably all the zero states are obtained by connecting a phase of the at least three phases of the AC signal having a smallest absolute instantaneous voltage value to the high and low nodes.

[0022] The fourth and fifth aspects described above can be provided independently of the first to third aspects, or in combination. In particular, the fourth and fifth aspects can be implemented in the electrical converter according to the first aspect. Brief description of the figures

[0023] Aspects of the invention will now be described in more detail with reference to the appended drawings, wherein same reference numerals illustrate same features and wherein:

[0024] Figure 1 represents a schematic of an exemplary embodiment of an electrical converter according to the invention implemented as a three-level (3-L) three phase (3-®) buck-boost (bB) current DC-link AC/DC converter system. To filter the common mode (CM) noise at the DC output port, the artificial 3-® neutral point k and the DC midpoint m are connected through a CM filter capacitor Com.

[0025] Figure 2 represents Operating regions of the proposed 3-L 3-9 bB current DC-link AC/DC converter system of Fig. 1. Depending on the required output voltage Vou, different operating modes, i.e. Buck-Mode, Transition-Mode, and Boost- Mode (#1 or #2), are applied in order to minimize the switching and conduction losses, and reduce the CM noise emission. Different colour intensity indicate different output power levels.

[0026] Figure 3a-d: Simulated waveforms of the converter of Fig. 1 operating in Buck-Mode with a capacitive return connection. In particular, in Fig. 3a the three-phase mains voltages va, %, and v, in Fig. 3b the three-phase mains currents /a, i», and i, the DC-link currents inc p and ioc pn and the CM current on the return connection icm, in Fig. 3c the output voltage vou and the output capacitor voltages Veou,p and Veoutn, and in Fig. 3d the three-phase mains line-to-line voltages Var, Vibe, and ve, are shown.

[0027] Figure 4: Differential mode (DM) voltages in Buck-Mode operation over one 60°-wide sector of the mains period defined by the three-phase mains currents, i.e. in this sector phase c has the minimum current value. In particular, Von is a switched waveform alternately assuming the values of two line-to-line voltages Va and Vo during the active states, and of OV during the zero state, and vy is equal to Vou. The graphs in the upper part offer a zoomed view of typical voltage waveforms within a switching period.

[0028] Figure 5a-b: CM voltage of the converter of Fig. 1 operating in the Buck-Mode according to an aspect of the invention (Fig. 5a), with the capacitive return connection, and (Fig. 5b) without the return connection (the white dotted line indicates the local average value (within one pulse period} of the switched voltage waveform Vem).

[0029] Figure 6: Common mode (CM) voltages in Buck-mode operation of the converter of Fig. 1 over one 60°-wide sector of the mains period defined by the three-phase mains currents, i.e. in this sector phase c has the minimum current value. specifically, the CM voltage generated by the CSR-stage Vcm‚csr constituted of two active states common mode voltages vey pc = ne and vey gc = Terre and one phase voltage v, or v,,, and low-frequency components of the generated CM voltage Voute. The graphs in the upper part offer a zoomed view of typical voltage waveforms during two switching periods.

[0030] Figure 7: Space vector diagram of a three-phase current DC-link converter highlighting the nine states of the three-phase rectifier. The 60°-wide sector considered in Fig. 3d is shaded.

[0031] Figure 8a-d: Simulated waveforms of the converter of Fig. 1 operating in Boost-Mode with a capacitive return connection. In particular, in Fig. 8a the three-phase mains voltages va, %, and v, in Fig. 8b the three-phase mains currents fa, ip, and /, the DC-link current ipcp and /oc.n and the CM current in the return connection icm, in Fig. 8c the output voltage Vu and the output capacitor voltages Veoutp and Veourn, and in Fig. 8d the three-phase mains line-to-line voltages Van, Vie, and Vea are shown.

[0032] Figure 9: DM voltages in Boost-Mode #1 operation over one 60°- wide sector defined by the three-phase mains currents, i.e. in this sector phase c has the minimum current value. In particular, Vm is a switched waveform alternately assuming the values of two line-to-line voltages Va and vie during the active states, while vy switches between LS and Vut. The graphs in the upper part offer a zoomed view of typical voltage waveforms within a switching period Ts.

[0033] Figure 10a-b: CM voltage vem of the converter of Fig. 1 operating in Boost-Mode #1 (Fig. 10a) with the return connection according to the invention, and (Fig. 10b) without the return connection (the white dot line indicates the local average value of the switched voltage waveform ve).

[0034] Figure 11: CM voltages in Boost mode #1 operation over a 60°- wide sector defined by the three-phase mains currents, i.e. in this sector phase c has the minimum current value. Specifically, CM voltage generated by the CSR-stage vemcsr constituted of the CM voltages of two active states vc = De and vey ge = Terre and low-frequency components of the generated CM voltage vVouis. Furthermore,

the CM voltage generated by the DC/DC-stage vem peoc formed by ++ Vout and OV is demonstrated. The graphs in the upper part offer a zoomed view of typical voltage waveforms during two switching periods.

[0035] Figure 12: DM voltages in Boost-Mode #2 operation over one 60°- wide selected sector defined by the three-phase mains currents, i.e. in this sector phase c has the minimum current value. In particular, Vn is a switched waveform alternately assuming the values of two line-to-line voltages Va and Ye during the active states, while vy switches between eS and Vou, Or fo and OV depending on the local average value of vp. The graphs in the upper part offer a zoomed view of typical voltage waveforms within a switching period Tsu.

[0036] Figure 13a-b: CM voltage of the converter of Fig. 1 operating in Boost-Mode #2 (Fig. 13a) with the return connection according to the invention and (Fig. 13b) without the return connection (the white dotted line indicates the local average value of the switched voltage waveform Vc).

[0037] Figure 14: CM voltages in Boost mode #2 operation over a 60°- wide selected sector defined by the three-phase mains currents, i.e. in this sector phase c has the minimum current value. Specifically, CM voltage generated by the CSR-stage Vcmcsr constituted of the CM voltages of two active states vey pc = wk and vey ge = Jai and low-frequency components of the generated CM voltage Voute.

Furthermore, the CM voltage generated by the DC/DC-stage Vempcoc formed by + Voue and OV is demonstrated. The graphs in the upper part offer a zoomed view of typical voltage waveforms during two switching periods.

[0038] Figure 15a-d: Simulated waveforms of the converter of Fig. 1 operating in Transition-Mode with a capacitive return connection. In particular, in Fig.

15 a the three-phase mains voltages va, %, and v;, in Fig. 15b the three-phase mains currents ia, in, and i, the DC-link current ioc p and ioc and the CM current on the return connection icm, in Fig. 15c the output voltage vu: and the output capacitor voltages Veoutp and Veoutn, and in Fig. 15d the voltage vik across the CM capacitor Cem are shown.

[0039] Figure 16: A synergetic control structure according to an exemplary embodiment includes three main blocks, i.e. the Output Voltage Control, the DCLink Current Reference Generation and the Synergetic DC-Link Current Control, enabling PFC operation with sinusoidal three-phase mains currents /, 4, and 4 in phase with the sinusoidal three-phase mains voltages Vina, Vn», and vine, regulation of the output voltage Vou, control of the DC-link current inc with synergetic operation of the three-phase buck CSR-stage and of the boost DC/DC-stage, and seamless transition between the different operating modes, i.e. Buck- and Boost-mode, and modulation schemes, i.e. 3/3-PWM and 2/3-PWM.

[0040] Figure 17a-b: CM/DM equivalent circuits of the electrical converter of Fig. 1. In particular, the CSR-stage and the DC/DC-stage are replaced by switched voltage sources in Fig. 17a and by equivalent CM/DM voltage sources in Fig. 17b.

[0041] Figure 18 represents another exemplary embodiment of an electrical converter according to the invention, which differs from the converter of Fig. 1 in that the second converter stage (DC/DC stage) is implemented as a flyback capacitor circuit. Description of embodiments

[0042] Referring to Fig. 1, an embodiment of an electrical converter 10 according to aspects of the present invention is implemented as a three-phase (3-9) current DC-link split-output buck-three-level-boost current AC/DC converter system, comprising a 3-® buck-type current source rectifier (CSR)-stage 11 and a subsequent three-level (3-L) boost-type DC/DC-stage 12. The CSR stage 11 comprises six semiconductor switches Tan, Ta, Ton, To, Ten, Te: having bidirectional voltage blocking capability, advantageously arranged in three bridge legs, and operable to switchingly connect the AC voltage nodes a, b, c to the DC nodes p, n. Each of these semiconductor switches can be formed by anti-series connecting two discrete semiconductor switches having unidirectional voltage blocking capability, possibly with external anti-parallel diodes. Alternatively, the semiconductor switches of the CSR stage 11 can be formed as monolithic bidirectional GaN field effect transistors, in particular enhanced-mode field effect transistors (e-FET).

[0043] The DC/DC stage 12 advantageously comprises an upper boost circuit 121 and a lower boost circuit 122 stacked between the DC terminals P and N. The upper and lower boost circuits 121, 122 comprise a common voltage node m. Each of the upper and lower boost circuits can be implemented with semiconductor switches Tocp and Toc‚np for the upper boost circuit 121 and semiconductor switches Toc,m and Toc ma for the lower boost circuit 122. Other implementations are possible. By way of example, either one or both the upper and lower boost circuits can be implemented as a flyback capacitor circuit 123, 124 as shown in Fig. 18.

[0044] A DC-link 13 connects the CSR stage 11 and the DC/DC stage 12. In particular, the DC-link 13 connects the DC-nodes p, n of the CSR stage 11 to the input nodes q, r of the DC/DC stage 12. The DC-link 13 is implemented with a novel common mode (CM) filtering concept, comprising a capacitive return connection 14 between the input capacitors Cin and the output capacitors Coutp and Coutn, possibly in combination with a CM DC-link inductor Loc.cm. This common mode filtering concept allows to significantly reduce the high-frequency components of CM noise.

[0045] An input filter 15 is advantageously arranged between the AC terminals A, B, C and the AC voltage nodes a, b, c. The input filter can comprise a network of input capacitors Ci, which are advantageously star-point-connected to star- point k. Furthermore, the splitoutput structure advantageously enables an asymmetrical loading capability at the DC output-port. Figs. 17a and b represent equivalent electrical circuits of the converter of Fig. 1. The DC-link 13 advantageously comprises a common mode inductor Loc cm and/or a differential mode inductor Loc pom which are operably coupled to nodes p and q and/or n and r.

[0046] Different possible operating modes employed in the different output voltage regions characteristic of this converter (see Fig. 2) are analyzed in the following with the support of simulation results.

[0047] The converter operating modes as described herein advantageously implement two different pulse-width modulation schemes for operating the switches Tan, Tan, Ton, Tos, Ten, Te: of the CSR stage 11, namely conventional pulse-width modulation (3/3-PWM)} and two-third pulse-width modulation (2/3-PWM). The electrical converter 10 comprises a control unit configured to automatically select which of the two PWM schemes to use for operating the CSR stage 11 based on a desired or requested output voltage, as will be described in more detail below.

[0048] Referring to Fig. 7, six symmetric TT/3-wide sectors of the AC input period are represented with six active states [bc], [ac], [ab], [cb], [ca] and [ba] and three freewheeling or zero states [aa], [bb] and [cc]. The letters ‘a’, ‘b’ and ‘C’ in the above refer to the voltage nodes a, b, c of Fig. 1. E.g., the state [bc] refers to a state in which node b is connected to node p by closing switch Tpn and in which node c is connected to node n by closing switch Tei. Hence, in the active states, the AC input 9 is connected between the DC-link nodes p, n, whereas in the zero states, the nodes p and n are short circuited. Consequently, depending on the selected state, the DC-link input voltage vp varies between OV (zero states) and the six input voltages tVa,, +V and Vac.

[0049] In 3/3-PWM, the six semiconductor switches Tan, Tas, Ton, Ten, Ten, Tc, of the CSR stage 11 are operated in order to switch between the two respective active states and the zero state. In the example of the shaded sector of Fig. 2, the switches of the CSR stage 11 are operated to switch between states [bc], [ac] and the zero state. Conventionally, the zero state [cc] is used for this sector. However, in one aspect of the invention, as will be described below in relation to buck-mode operation, the zero state used in this sector is [bb] from z to 5 and [aa] from z to > instead of [cc] over the whole sector. This allows to further reduce the common mode noise generated by the CSR stage.

[0050] In 2/3-PWM, a pulse-width modulation scheme is employed that is free of zero states in all sectors, i.e. all zero space vectors are eliminated and only the active states are applied. For the shaded sector of Fig. 2, this results in that only active states [bc] and [ac] are applied, without applying the zero state, e.g. [cc]. Consequently, Ten is permanently off and only Tan and Tr are alternately switched. In this case, Te, is permanently on and Ta; and Ty; are permanently off. The 2/3-PWM scheme allows to improve efficiency by eliminating switching losses resulting from transitioning to/from the zero state and possibly conduction losses in the DC-link due to reduced RMS value of the DC-link current. Further details regarding 2/3-PWM scheme can be found in reference [6], section III.B and IV and in [4].

(i) Buck-Mode Operation (Vo <> Pin)

[0051] In buck-mode operation, the most significant waveforms of the CSR-stage and of the DC/DC-stage are reported in Fig. 3a-d. In this mode, only the CSR-stage operates to step down the three-phase mains voltages to a DC output voltage lower than Don (where ¥;,, refers to the peak amplitude of the AC input voltage). The two switches Toe np and Toc nn of the DC/DC-stage are permanently on to avoid any switching losses, as shown in Fig. 4, where vy = Vou.

[0052] The differential mode (DM) output voltage of the CSR-stage Vn is a switched waveform alternately assuming the values of two line-to-line voltages during the active states, and of OV during the zero state, as shown in Fig. 4.

[0053] In Fig. 5a-b, Voucsr coincides with the CM voltage vem generated by the converter without the return connection 14, i.e. with an open circuit between m and k, due to permanently clamping of the DC/DC stage. With a capacitive return connection, i.e. a CM capacitor Ccm connected between m and k, Cc, together with the CM DC-link inductor Loe, forms a CM filter. Accordingly, the low-frequency (LF), i.e. 150Hz, component of ven appears across Cen (See Fig. 5a), while the high-frequency (HF) component, i.e. at the switching frequency, appears across Loc, and Loca.

[0054] In buck-mode operation, a 3/3-PWM scheme is advantageously applied. To reduce the CM noise generated by the CSR-stage 11 without increasing switching losses or degrading the DM performance, e.g. the DC-link current ripple, the zero state is advantageously implemented by connecting the AC input voltage node a,

b, c having the smallest absolute instantaneous voltage value to the nodes p, n of the DC-link 13. In Fig. 6, the sector where phase c has the minimum current value is considered as an example (this sector is shaded in Fig. 7). The zero state used in this sector is [bb] from = to = and [aa] from Z to Z, instead of [cc] as in the PWM schemes described in literature (see Fig. 7).

[0055] The aforementioned PWM modulation scheme advantageously allows to have a continuous LF component of ven at the boundary between different sectors, in turn allowing implementation of the capacitive return connection 14. Thus, advantageously, in each sector, the LF component of vem should, for example, start from OV and end at OV. Otherwise, a current ringing will occur on the return path and also in the DC-link.

(ii) Boost-Mode Operation (Vu: > V3Vn)

[0056] To achieve the boost functionality, both CSR-stage 11 and DC/DC- stage 11 are operated simultaneously. The CSR-stage 11 always operates at the maximum modulation index (equal to one) to minimize the DC-link current inc and the conduction losses of the whole converter 10. In boost-mode operation, a 2/3-PWM scheme is advantageously applied to the switches of the CSR stage 11. The DC-link current ipc is controlled to a pulsed shape as shown in Fig. 8b. Depending on the local average value (averaged within one pulse period) of vu, the input voltage of the DC/DC-stage var is a switched waveform alternately assuming the values of tand Vout (Boost-Mode #1, see Fig. 9), or OV and la (Boost-Mode #2, see Fig. 12).

[0057] Furthermore, the converter CM voltage vem (for Boost-Mode #1 see Fig. 10b, and for Boost-Mode #2 see Fig. 13b) is generated by both the CSR-stage 11 and the DC/DC-stage 12, due to the operation of both stages in Boost-Mode.

[0058] Last but not least, the upper and lower output capacitors Coup and Coutn are alternatively utilized when fo is required at the input 12 of the DC/DC-stage to balance the output mid-point m. As a result, the main frequency component of vempepc is at half of the switching frequency, while the one of Vcucsr is at the three times of the mains frequency.

(ii.1) Boost-Mode #1 (3V;,, > Vor > V3Vi,))

[0059] A three-level (3-L) DC/DC-stage 12 is advantageously considered allowing to extend the output voltage range and reduce the switching losses in the DC/DC-stage (as compared to a two-level arrangement). Due to a comparably low output voltage in the Boost-Mode #1, the input voltage of the DC/DC-stage vy is a switched waveform alternately assuming the values of To and Vou (Boost-Mode #1, see Fig. 9).

[0060] The CM voltage generated by the CSR-stage vemcsr is a switched waveform alternately assuming the values of two CM voltages during the active states, as shown in Fig. 11. Advantageously, the LF component of vemcsk is identical to the LF component of vem, which also satisfies the aforementioned requirement for the proposed CM filtering method. The DC/DC-stage only produces HF CM components, i.e. OV if vgr= OV Or Vou, if Toc np and Toc. are on, and — fot if Toc.m and Tocp are on.

[0061] Considering the impact on CM and DM voltage-time area, the same carrier is advantageously used to generate the PWM signals of the CSR-stage 11 and of the DC/DC-stage 12, and the switching states featuring the larger values of two switched voltage waveforms vu, and Vg are centered in one switching period to ensure minimum CM and DM voltage-time area over the DC-link CM and DM inductors Loc‚p and Lopes, as shown in Fig. 9. (ii.2) Boost-Mode #2 (Vr: > 3V;,)

[0062] Due to the increased Vut, the input voltage of the DC/DC-stage Var is a switched waveform alternately assuming the values of OV and ie (Boost-Mode #2, see Fig. 12). When Vo > 3 in, Vou is large enough to balance the DM voltage-time area of the CSR-stage by only using OV and Low so Boost-Mode #2 is applied.

[0063] The CM voltage generated by the CSR-stage Voucsr is a switched waveform alternately assuming the values of two CM voltages of the active states, as shown in Fig. 14. Advantageously, the LF component of vemcsr is identical to the LF component of Vcm, which also allows to satisfy the aforementioned requirement for the selected CM filtering method. The DC/DC-stage only produces HF components, i.e. OV if Vy= OV or Vou, fo if Toc np and Tocwn are on, and — 7 if Toc. and Toc‚p are on. (iii) Transition-Mode Operation É Vin < Vour < VBV a)

[0064] In Transition-Mode, 3/3-PWM and 2/3-PWM are alternately applied based on the local average value of vpn, Tyn. If Ty, > Vout, 3/3-PWM is used, and if Don < Voue, 2/3-PWM is used, as shown in Fig. 15.

[0065] The DM and CM voltage analysis follows the behaviour described for 2/3-PWM and 3/3-PWM independently. Control unit with synergetic control structure

[0066] Fig. 16 shows a block diagram of control unit 20 implementing a synergetic control structure according to an aspect of the present invention. The control unit 20 advantageously comprises three main functional blocks 21, 22 and 23. Control unit 20 can be configured to receive as input a reference output voltage. Outputs of the control unit 20 are gate signals to the switches of the CSR stage 11, representative of a selected PWM scheme and gate signals to the switches of the DC/DC stage 12, which are particularly representative of a duty cycle which the control unit 20 has determined for these switches (in boost mode operation). On the other hand, in buck-mode operation, control unit 20 is configured to maintain DC/DC stage 12 inoperative as described above.

[0067] The first block 21 is formed by an Output Voltage Controller, and is configured to define the input power reference FP, e.g. through a Pl-controller, considering the error between the actual and the reference output voltage, Vou and Ve: respectively. Hence, by measuring the peak value of the three-phase mains voltages Vi, meas (constant over one mains period even for unbalanced mains conditions), the converter’s input conductance reference G*is calculated as: * P* Time and fed into the following block 22 responsible for the DC-Link Current Reference Generation.

[0068] In order to achieve PFC operation, the three-phase mains current references ig, ij, and i; are set proportional to the corresponding three-phase mains voltages vna, Vp, p, and vn, and are limited to /nax to ensure the safe operation of the selected power semiconductors and to avoid the saturation of the DC-link inductor Loc. The instantaneous values of these currents advantageously provide the sector information for the space vector pulse width modulator 24 of the CSR-stage 11, while the upper envelope of their absolute values ij, , 5, obtained by ipc,2s = max{lighliph liel}, (2) is the varying DC-link current reference for 2/3-PWM operation. Differently, multiplying G* with the calculated peak value of the three-phase mains voltages P; (different from Vin.meas Only in case of unbalanced mains conditions), defined by:

Pine = 2 +v}+v), (3) provides the peak value of the three-phase mains current references I). Vine is constant and equal to Vi, eqs only for symmetric mains conditions. If the mains is unbalanced, V;, . shows a time-dependent behaviour within one switching period. The varying Vine ensures a sinusoidal shape of I. 5; during one-phase operation.

[0069] The DC-link current reference for 3/3-PWM operation I; 5/3, can be determined by the reference output power P* and measured phase voltages Va, Vp, Vr. This ensures the operation under unbalanced mains condition. Dividing I}, by the current conversion ratio of the AC/DC-stage m,.,,, and of the DC/DC-stage mpc;pc: the DC-link current reference for 3/3-PWM operation Ip: 5,3, is calculated. Myc pc and mpc pe are derived from the reference output voltage Vu: to operate with the minimum DC-link current ipc. It will be convenient to note that the current conversion ratio of the AC/DC-stage can alternatively be stated as m,; pc = 2 and of the DC/DC-stage as Mpc/Dc = on Therefore, as an advantage and as shown in Fig.

16, the present method advantageously allows to determine Incas without requiring to measure the output current /ou.

[0070] Moreover, the DC-link current reference ij. takes the maximum value between inc, 3, and Ipc 33, ipc = max{ije 2/3 Incas): (4) providing the input for the third block 23, controlling the DC-link current, and referred to as the Synergetic DC-Link Current Control. In particular, in one embodiment, automatic selection of the operating mode can be based on the value of i}, and hence based on comparison between írc,2/3 and Ipc,3/3-

[0071] If ipc‚2/3 is larger than ku, the converter 10 operates in Boost- mode, with 2/3-PWM operation of the CSR stage 11. If smaller, the DC/DC-stage 12 does not operate, the switches Toc.np and Toc nn are permanently on, and the CSR-stage 11 operates with 3/3-PWM in Buck-mode, resulting in identical currents flowing through the DC-link inductor and at the DC output.

[0072] Advantageously, the method for determining í5c shown in (4), ensures a seamless transition from 3/3-PWM to 2/3-PWM and vice versa. It furthermore advantageously ensures minimum conduction losses in Transition-mode.

[0073] In the Synergetic DC-Link Current Control block 23, ip. is first compared with ip. == (icp + ipcn); their difference, e.g. by means of the DC-link current Pl-controller, provides the voltage v; to be generated across Loc by switching the CSR-stage 11 and possibly the DC/DC-stage 12. The sum of v; and the output voltage reference V,,; results in the virtual DC-link voltage reference Vp. Feeding Vj into two voltage limiters, the virtual DC-link voltage references for 3/3-PWM vp 5 3 and for 2/3-PWM v‚c,2;3 are calculated. This is the core of the synergetic operation; in fact, when the three-phase mains voltages are large enough to generate the necessary Vic without operating the DC/DC-stage, i.e. Vu: < Vax, this stage is permanently clamped to eliminate its switching losses, while the CSR-stage provides the required voltage gain (Buck-mode), but must operate with 3/3-PWM. In this case, vj; 3/3 = Vpc = Vpn, i.e. the reference output voltage of the CSR-stage, and vj 5,3 = Vour. Differently, when Vo is large enough to balance the volt-second area applied to Loc by the CSR-stage with Macoc = 1, ie. Vie > = Vina: the CSR-stage operates with 2/3-PWM and the DC/DC-stage is actively switched with PWM (Boost-mode). Specifically, vp 3,5 = Vmax: and Vpc,2/3 = vg, i.e. the reference input voltage of the DC/DC-stage. Finally, when Vinax < Vour © = Vaz the current controller democratically switches between 2/3-PWM and 3/3-PWM, depending on the instantaneous v; (Transition-mode).

[0074] Accordingly, the current control block 23 advantageously regulates the DC-link current inc always by means of only one stage, i.e. when operating with 3/3- PWM, the CSR-stage 11 is controlled by modifying vp 5/3 and v‚c,2/3 is not influenced thanks to the voltage limiter; when operating with 2/3-PWM, instead, the DC/DC-stage 11 is controlled by modifying vj 5,5 and vj 5,3 is clamped to Vinax.

[0075] To ultimately operate the two stages, v‚c3/;3 and vy ,,; are fed to the modulators 24, 25. For the CSR-stage, the reference DC-link current ipc‚cse utilized in the modulator 24 is determined based on vy 3,3 and on Mocioc. ine ese and ipc are identical in steady state. Specifically, in 3/3-PWM operation, Vo: coincides with vg, = Vpc‚3/3 and mye pe=1 because Toc‚np and Toc‚m are permanently on. Differently, in 2/3- PWM operation, mp, must be considered due to the operation of the DC/DC stage. Given Vou __ _, Mp pc: Vmax the CSR-stage operates with the maximum modulation index, and ip: is regulated by the DC/DC-stage only. The switching signals for the CSR-stage 11 can be calculated from iy, iy, iz, and ip csi @s described in reference [4] and appropriately distributed to the twelve gate terminals.

[0076] An example is given in the following considering the sector where phase c has the minimum current value (see Fig. 7). The zero state used in this sector is [bb] from z to : and [aa] from z to = instead of [cc] as in the PWM schemes described in the prior art. The duty cycles of the two active states and of the zero state are calculated as: 8ac) = ZE Sipe = Land 810) = 1 — Sac) — Ove) where ó;xy] indicates the duty cycle of the state [xy].

[0077] Finally, the duty-cycle reference of the DC/DC-stage 12 is calculated by: gr = Poeass _ Van Vout Vout and then compared with a three-level triangular carrier to generate complementary switching signals.

Claims

CONCLUSIONS

An electrical converter (10) for converting between an alternating current signal having at least three phases and a direct current signal, comprising: at least three phase connections (A, B, C), a first direct current connection (P) and a second direct current connection (N) , a first converter stage (11) operably coupled to the at least three phase connections and comprising a first intermediate node (p) and a second intermediate node (n), the first converter stage (11) operable to convert between a alternating current at the at least three phase connections and a first direct current (inc p, inc.) at the first and second intermediate nodes (p, n), a second converter stage (12) operably coupled to the first direct current connection (P) and the second DC terminal (N) and comprising a third intermediate node (q) and a fourth intermediate node {r), the second converter stage operative to convert between and a first DC signal at the third and fourth intermediate nodes (q, r) and a second DC signal at the first and second DC terminals, the second converter stage comprising a center voltage node (m) between the first and second DC terminals, a first filter stage (15 ) comprising a capacitor network (Cin) operably coupled to each of the three phase connections, the capacitor network comprising a star point (k), a DC link (13) connecting the first intermediate node (p) to the third intermediate node (q) and the second intermediate node {n) to the fourth intermediate node (r), the DC connection comprising a common mode filter, the common mode filter comprising a common mode capacitor (Ccm) connecting the intermediate voltage node (m) to the star point (k).

The electrical converter of claim 1, wherein the common mode filter comprises a common mode filter choke (Loccm) operably coupled to the first intermediate node (p) and the second intermediate node (n), the third intermediate node (q) and the fourth intermediate node (r).

An electrical converter according to claim 1 or 2, wherein the direct current connection comprises at least one differential mode inductor (Loc om) operably coupled to the first intermediate node (p} and the third intermediate node (q) and/or operably coupled to the second intermediate node {n) and the fourth intermediate node (r).

The electrical converter of claims 2 and 3, wherein the common mode filter choke (Lpocew) and the differential mode inductor (Loco) comprise a common core or individual cores.

An electrical converter according to any one of the preceding claims, wherein the first DC signal is the first DC current (ioc p, inca).

An electrical converter according to any preceding claim, wherein the second DC signal is a DC voltage (Vox) across the first and second DC terminals.

An electrical converter according to any preceding claim, wherein the first filter stage (15) comprises inductors (Ln) coupled between the three phase terminals (A, B, C) and the capacitor network (Cin).

An electrical converter according to any preceding claim, wherein the second converter stage (12) comprises a capacitor filter (Coup, Coun) comprising a plurality of serially connected capacitors across the first and second DC terminals, the center voltage node (m} being a center junction of the capacitor filter.

An electrical converter according to any preceding claim, wherein the second converter stage (12) comprises a boost circuit (121, 122, 123, 124).

The electrical converter according to claim 9, wherein the second converter stage comprises a plurality of serially connected first switches (Toc‚vp, Toc‚m) connected between the third intermediate node (q) and the fourth intermediate node (r), wherein a center point of the serially connected first switches is connected to the center voltage node (m).

An electrical converter according to claim 9 or 10, wherein the boost circuit comprises a first boost circuit (121, 123) and a second boost circuit (122, 124) stacked between the first DC terminal (P) and the second DC terminal (N), wherein the middle voltage node (m) is a common node of the first and second booster circuits.

An electrical converter according to claim 11, wherein the first boost circuit and/or the second boost circuit is a multi-level boost circuit.

An electrical converter according to any one of the preceding claims, comprising a third DC terminal connected to the center voltage node (m).

An electrical converter according to any preceding claim, comprising a control unit (20), wherein the first converter stage (11) and the second converter stage (12) comprise active switching devices operatively coupled to the control unit, the control unit being implemented with a multitude of operation modes for controlling the electrical converter.

The electrical converter of claim 14, wherein a first mode of operation of the plurality of modes of operation corresponds to a buck mode of operation, wherein the second converter stage is configured to operate to continuously connect the third and fourth intermediate nodes (q, r) to the first and second DC terminals, respectively, and wherein the control unit (20) is configured to actively operate the active switching devices (Tan, Tan, Ton, Tos, Ten Tej) of the first inverter stage (11).

The electrical converter of claim 15, wherein the control unit, in the first mode of operation, is configured to operate the active switching devices of the first converter stage (11) according to a pulse width modulation scheme that switches between active states in which two phases of the at least three phases are connected to the first and second intermediate nodes {p, n} and null states wherein the first and second intermediate nodes (p, nj} are shorted, the controller being configured to implement the null states by connecting a phase of the at least three phases of the AC signal having a smallest absolute instantaneous voltage value with the first and second intermediate nodes (p, n).

An electrical converter according to any one of claims 14 to 16, wherein a second mode of operation of the plurality of modes of operation corresponds to a boost mode of operation, wherein the control unit (20) is configured to actively operate the active switching devices (Tan, Tas, Ton, Tos, Teh, Tek T0Chp, TDC, Tpc‚nn, Tpew) of both the first inverter stage (11) and the second inverter stage (12).

The electrical converter of claim 17, wherein the control unit (20), in the second mode of operation, is configured to operate the active switching devices of the first converter stage (11) according to a pulse width modulation scheme free of zero states wherein the first and second intermediate nodes are shorted by the active switches of the first inverter stage.

An electrical converter according to any one of claims 14 to 18, wherein the control unit (20) is operable to operate the electrical converter in rectification mode, the control unit, in rectification mode, is operable to determine a first current reference (Ïoc23) for a current in the DC link and a second current reference (I'ncas) for the current in the DC link, the control unit operable to automatically select between the plurality of modes of operation based on comparison of the first current reference and the second current reference.

The electrical converter of claim 19, wherein the first current reference is determined based on a reference output power and reference input phase currents.

The electrical converter of claim 19 or 20, wherein the second current reference is determined based on a reference output power and measured phase voltages.

An electrical converter according to any one of claims 14 to 21, wherein the control unit (20) is configured to operate the active switching devices by pulse width modulation.

An electrical converter according to any one of claims 14 to 22, wherein the control unit (20) is configured to operate the first converter stage (11) and the second converter stage (12) to obtain a voltage across the common mode capacitor ( Ccm) which is one of: a substantially constant zero voltage signal, a substantially triangular waveform and a substantially sinusoidal waveform, preferably comprising one or more harmonic frequencies of a fundamental frequency of the AC signal, preferably comprising a third harmonic frequency of the fundamental frequency.

An electrical converter according to any one of claims 14 to 23, wherein the control unit (20) is operable to inject a common mode voltage signal into the third and fourth intermediate nodes (q, r) to drive a voltage across the common mode capacitor (Cem).

An electrical converter according to claim 24, comprising measuring means for measuring a voltage signal at the middle voltage node (m) and at nodes (a, b, c) of the at least three phases, the control unit being operative to determine the common mode voltage signal injected into the third and fourth intermediate nodes (q, r) based on the measured voltage signals.

An electrical converter according to claim 24 or 25, wherein the control unit is operable to add an offset to duty cycles of pulse width modulation signals controlling the operation of active switches (Toc vp, Toc‚m) of the second converter stage, whereby the common mode voltage signal injected into the third and fourth intermediate nodes (q, r) is obtained.

An electric motor drive system comprising the electric converter according to any preceding claim.

The electric motor drive system of claim 27, further comprising an electric motor comprising stator coils, the stator coils connected to act as a common mode filter choke and/or as a differential mode inductor of the DC connection of the electrical converter.

An electric motor drive system according to claim 27 or 28, comprising a traction converter operable to drive the electric motor, the traction converter configured to act as the second converter stage in operating the electric converter.

A battery charging system, in particular for charging batteries of electric vehicles, wherein the battery charging system comprises a power supply, the power supply comprising the electrical converter according to any one of claims 1 to 26.

A method of converting between an AC signal having at least three phases at at least three phase nodes (a, b, } and a DC signal at a high node (p) and a low node (n), comprising providing the electrical converter according to any one of claims 1 to 26, and switching by pulse width modulation between the at least three phase nodes (a, b, c) and the high node (p) and the low node (n) to obtain a switched voltage signal across the high node and low node to obtain a switched voltage signal across the high node and low node, wherein a period of the switched voltage signal includes a zero voltage level portion obtained by connecting the phase node which has a smallest absolute instantaneous voltage value of the tens has at least three phases of the AC signal with both the high node (p) and the low node (n).

The method of claim 31, wherein the switched voltage signal comprises a second voltage level portion obtained by connecting the phase node having the highest instantaneous voltage value of the at least three phases of the AC signal to the high node (p), and connecting of the phase node having the lowest instantaneous voltage value of the at least three phases of the AC signal to the low node (n).

The method of claim 31 or 32, wherein the switched voltage signal comprises a third voltage level portion obtained by connecting the phase node having the smallest absolute instantaneous voltage value to the high node, and connecting the phase node having the lowest instantaneous voltage value of has at least three phases of the AC signal with the low node, or vice versa.