NL2002038C - Method and system for coding and decoding signals. - Google Patents

Method and system for coding and decoding signals. Download PDF

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Publication number
NL2002038C
NL2002038C NL2002038A NL2002038A NL2002038C NL 2002038 C NL2002038 C NL 2002038C NL 2002038 A NL2002038 A NL 2002038A NL 2002038 A NL2002038 A NL 2002038A NL 2002038 C NL2002038 C NL 2002038C
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signal difference
difference values
values
signal
group
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NL2002038A
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Dutch (nl)
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Jochem Welvaadt
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Qdes Works B V
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Priority to NL2002038A priority Critical patent/NL2002038C/en
Priority to PCT/NL2009/000191 priority patent/WO2010039029A1/en
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Publication of NL2002038C publication Critical patent/NL2002038C/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Description

P29511N LOO/ΜΕ
METHOD AND SYSTEM FOR CODING AND DECODING SIGNALS FIELD OF THE INVENTION
5 The invention relates to the field of coding and decoding signals, and more specifically to coding and decoding audio signals. In the method and system according to the invention, a digital input signal is coded, transmitted, received, and decoded to obtain a digital output signal representing the digital input signal. The digital input signal may be obtained from A/D conversion of an analog audio input signal. An analog output signal may be obtained from 10 D/A conversion of the digital output signal. The invention also relates to a coding method and system, and to a decoding method and system.
BACKGROUND OF THE INVENTION
15 In the transmission of audio signals, often a conversion to the digital domain is made, and a data compression is applied to enable a fast transmission using low bandwidth.
In known frequency domain compression methods, such as those defined by the MPEG, large buffers are required to avoid distortion which would otherwise be caused by the window effect for an applied FFT (Fast Fourier Transformation) conversion. The large buffers 20 result in delays for the transmission, e.g. delays in the order of 100 ms are not uncommon. If such methods were to be used in live music transmission, their performance would be unacceptable. Moreover, a processor load for performing FFT operation is high since such operation requires complex mathematical functions.
In known PCM (Pulse Code Modulation) systems, transmission errors resulting in loss 25 of data lead to discontinuities in the output signal.
SUMMARY OF THE INVENTION
It would be desirable to provide a method and system for transmission of digital 30 signals having a low transmission delay. It would also be desirable to provide a method and system for transmission of digital signals in which an original analog signal remains substantially undistorted when data loss occurs.
To better address one or more of these concerns, in a first aspect of the invention a method for processing a digital input signal containing a sequence of input signal sample 35 values is provided. The method comprises: determining signal difference values between -2- pairs of subsequent input signal sample values; determining a divider for a group of subsequent signal difference values; coding the subsequent signal difference values by dividing each signal difference value of the group of subsequent signal difference values by the divider to obtain a group of coded signal difference values; transmitting and receiving the 5 group of coded signal difference values, and the divider; decoding the coded signal difference values by multiplying each coded signal difference value of the group of coded signal difference values by the corresponding divider to obtain a group of decoded signal difference values; and determining a digital output signal containing subsequent output sample values from the decoded signal difference values by adding a decoded signal difference value to a 10 sum of previous decoded signal difference values.
According to the present invention, a high data compression takes place, and at the same time small buffers (arranged for buffering values during their processing, such as buffering a group of signal difference values) can be used. A small buffering capacity leads to a low transmission delay.
15 According to the present invention, signal difference values are coded, transmitted, received and decoded in subsequent groups. A group of signal difference values is stored in a buffer before all signal difference values are coded, and the group is associated with the corresponding divider. After transmission, a group of coded signal difference values is stored in a buffer before the signal difference values are decoded using the corresponding divider.
20 Should the transmission of coded signal difference values from a buffer and/or the corresponding divider become corrupt due to loss of data, no discontinuity in the digital or analog output signal will occur, due to the differential coding. Thus, an audio signal processed according to the present invention will hardly be distorted when a loss of data during transmission occurs.
25 Transmission may be through a wired or a wireless coupling, link or connection.
The present invention can be applied e.g. in the fields of wireless mobile phone earpieces, wireless personal audio earpieces, wireless microphones, wireless connections for musical instruments, telecommunication equipment, and VOIP (Voice Over IP) systems.
In an embodiment, the present invention provides a system for processing a digital input 30 signal containing a sequence of input signal sample values. The system comprises: a first processor for determining signal difference values between pairs of subsequent input signal sample values, for determining a divider of a group of subsequent signal difference values, and for coding the subsequent signal difference values by dividing each signal difference value of the group of subsequent signal difference values by the divider to obtain a group of 35 coded signal difference values; a transmitter for transmitting the group of coded signal difference values, and the divider; a receiver for receiving the group of coded signal difference values, and the divider; a second processor for decoding the received coded signal -3- difference values by multiplying each coded signal difference value of the group of coded signal difference values by the corresponding divider to obtain a group of decoded signal difference values; and for determining a digital output signal containing subsequent output sample values from the decoded signal difference values by adding a decoded signal 5 difference value to a sum of previous decoded signal difference values.
The above and other aspects of the invention will be more readily appreciated as the same becomes better understood by reference to the following detailed description and considered in connection with the accompanying drawings in which like reference symbols designate like parts.
10
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 depicts a system for processing an analog input signal, containing a system for processing a digital input signal derived from the analog input signal.
15
DETAILED DESCRIPTION OF EMBODIMENTS
Figure 1 depicts a signal processing system comprising an analog-to-digital converter ADC, a first processor 2, a second processor 4, and a digital-to-analog converter DAC.
20 In operation, an analog input signal AS is input to the ADC, which converts the analog input signal AS into a digital input signal (a sequence of sample values) DS and outputs the digital input signal. The digital input signal DS is input to the first processor 2 which performs a coding operation on the digital signal, and outputs a coded digital signal CDS. Next, the coded digital signal CDS is transmitted in an appropriate way by a transmitter TX, which may 25 be part of the first processor 2, or may be an additional unit.
The coded digital signal CDS is received by a receiver RX, which may be part of a second processor 4, or may be an additional unit. The coded digital signal CDS is input to the second processor 4, which performs a decoding operation on the coded digital signal, and outputs a decoded digital output signal “DS” which is highly similar to the digital input signal 30 DS. The digital output signal “DS” is input to the DAC, which converts it into an analog output signal “AS” which is highly similar to the analog input signal AS.
Thus, a transmission of the analog signal has taken place.
Next, the operation of the digital processing system of Fig. 1 in accordance with the invention will be described in more detail, in different embodiments.
35 The analog input signal AS is supplied to the ADC which converts the analog input signal into a digital input signal at a predetermined sampling rate (e.g. 44.1 kHz, 48 kHz or 96 kHz) and with a predetermined precision (e.g. 8 bit, 12 bit, 16 bit or 24 bit). In the following, a -4- precision of 24 bit will be assumed as an example, but other precisions are possible within the scope of the present invention.
Table I below, first and second columns, illustrates sample numbers and corresponding sample values, respectively, for a plurality of subsequent samples.
5
Table I
Sample no. Sample Signal Divider Coded signal Decoded value difference difference signal value value difference value Ï 15.653.827 - 11.275 Ö 2 17.085.739 1.431.912 11.275 Ï27 1.431.925 3 18.357.826 1.272.097 11.275 ÏÏ3 1.274.075 4 19.613.283 1.255.447 11.275 ÏÏÏ 1.251.525 5 20.364.106 750.823 11.275 67 755.425 6 20.628.369 264.263 3847 69 265.443 7 20.526.853 -101.516 3847 ^26 -100.022 8 20.948.326 421.473 3847 1ÏÖ 423.170 9 21.436.927 488.601 3847 127 488.569 10 21.893.682 456.755 3847 119 457.793 11 21.705.326 -188.356 15.300 -12 -183.600 12 “ “ “ “ “
In a first embodiment, the first processor 2 processes the sample values to produce 10 signal differential values between pairs of subsequent input signal samples as shown in the third column of Table I. As an example, the signal differential value between sample no. 10 (21.893.682) and sample no. 9 (21.436.927) is 456.755.
For a group of five samples indicated by a bold line, i.e.. sample nos. 6, 7, 8, 9 and 10, the first processor 2 determines a divider in the following way. First, the largest signal 15 difference value among the sample nos. 6-10 is determined. It appears that sample no. 9 has the largest signal difference value of 488.601 (indicated by a bold line in the third column of Table I). In addition, a digital precision, expressed as a number of bits, is selected. In the example, an 8 bit precision is selected. From the selected precision, a factor is determined, which is the largest (or at most the largest) number to be expressed in said number of bits in 20 a specific notation. In this exemplary case the number of bits is 8 bits. In the example, the factor is selected to be the largest 8 bit number in two’s complement notation, i.e. 127. Now, -5- the divider is found by dividing the largest signal difference value by the factor: 488.601/127 = 3847. Next, all signal difference values of the group of signal difference values are divided by the same divider, which results in the numbers in the fifth column in Table I (coded signal difference values), which are all expressible in an 8 bit digital number. The coded signal 5 difference values are rounded to the nearest integer.
The coded signal difference values and the divider are transmitted from the transmitter TX to the receiver RX, in a manner known per se, such as by PCM (Pulse Code Modulation) or PWM (Pulse Width Modulation).
In the second processor 4, the coded signal differences are multiplied by the 10 corresponding divider to obtain decoded signal difference values, as illustrated in the sixth column of Table I. Due to rounding errors (rounding the coded signal difference values to the nearest integer), the decoded signal difference values (sixth column in Table I) which can be obtained from the coded signal difference values (fifth column in Table I) by multiplication thereof by the divider (fourth column in Table I), deviate slightly from the (original) signal 15 difference values (third column in Table I).
Each decoded signal difference value is added to a sum of previously decoded signal difference values to obtain a digital output signal containing subsequent output sample values “DS” to be fed to the DAC.
In the first processor 2, a divider may be modified in the first processor 2 before 20 sending it from the transmitter TX to the receiver RX. Then, in the second processor 4, the modified divider is inversely modified before using it to obtain decoded signal difference values. Table II illustrates such a modification of the divider by taking the square root of the divider, while again using a factor in line with an 8 bit precision.
25 Table II
Sample no. Sample Signal Square root Coded signal Decoded value difference of divider/ difference signal value Divider value difference value Ï 15.653.827 - 107/11.449 Ö 2 17.085.739 1.431.912 107/11.449 Ï25 1.431.125 3 18.357.826 1.272.097 107/11.449 TÏÏ 1.270.839 4 19.613.283 1.255.447 107/11.449 TTÖ 1.259.390 5 20.364.106 750.823 107/11.449 66 755.634 6 20.628.369 264.263 63/3.969 67 265.923 7 20.526.853 -101.516 63 / 3.969 :26 -103.194 -6- 8 20.948.326 421.473 63 / 3.969 Π06 420.714 9 21.436.927 488.601 63/3.969 123 488.187 10 21.893.682 456.755 63/3.969 115 456.435 11 21.705.326 -188.356 124/15.376 -12 -184.512 Ï2 “ “ “ “ ~
For a group of five samples indicated by a bold line in Table II, i.e.. sample nos. 6, 7, 8, 9 and 10, the first processor 2 now determines a divider in the following way. First, the largest signal difference value among the sample nos. 6-10 is determined. It appears that 5 sample no. 9 has the largest signal difference value of 488.601 (indicated by a bold line in the third column of Table II). In addition, a digital precision, expressed as a number of bits, is selected. In the example of Table II, an 8 bit precision is selected. From the selected precision, a factor is determined, which is the largest (or at most the largest) number to be expressed in said number of bits, in this case in 8 bits. In this example, the factor is selected 10 to be a large 8 bit number, i.e. 125. Now, the divider is found by dividing the largest signal difference value by the factor: 488.601/125 = 3969. Next, from the divider, a modified divider is derived by taking the square root of the divider: sqrt(3969) = 63. Next, all signal difference values of the group of signal difference values are divided by the same divider, which results in the numbers in the fifth column in Table I (coded signal difference values), which are all 15 expressible in an 8 bit digital number. The coded signal difference values are rounded to the nearest integer.
The coded signal difference values and the modified divider are transmitted from the transmitter TX to the receiver RX, in a manner known per se.
In the second processor 4, the divider is regenerated from the modified divider by 20 squaring the modified divider. The coded signal differences are multiplied by the corresponding divider to obtain decoded signal difference values, as illustrated in the sixth column of Table II. Due to rounding errors (e.g. rounding the coded signal difference values to the nearest integer), the decoded signal difference values (sixth column in Table II) which can be obtained from the coded signal difference values (fifth column in Table II) by multiplication 25 thereof by the divider (fourth column in Table II, right-hand side), deviate slightly from the (original) signal difference values (third column in Table II).
Table III illustrates such an further alternative modification of the divider by performing a 2log(divider) function, while again using a factor in line with an 8 bit precision.
30 Table III
Sample no. Sample Signal 2log(divider)/ Coded signal Decoded -7- value difference divider difference signal value value difference value Ï 15.653.827 - 14/16.384 Ö 2 17.085.739 1.431.912 14/16.384 87 1.425.408 3 18.357.826 1.272.097 14/16.384 78 1.277.952 4 19.613.283 1.255.447 14/16.384 77 1.261.568 5 20.364.106 750.823 14/16.384 46 753.664 6 20.628.369 264.263 12/4.096 65 266.240 7 20.526.853 -101.516 12/4.096 ^25 -102.400 8 20.948.326 421.473 12/4.096 ÏÖ3 421.888 9 21.436.927 488.601 12/4.096 119 487.424 10 21.893.682 456.755 12/4.096 112 458.752 11 21.705.326 -188.356 14/16.384 -11 -180.224 12 “ “ ~ I ~
For a group of five samples indicated by a bold line in Table III, i.e.. sample nos. 6, 7, 8, 9 and 10, the first processor 2 now determines a divider in the following way. First, the largest signal difference value among the sample nos. 6-10 is determined. It appears that 5 sample no. 9 has the largest signal difference value of 488.601 (indicated by a bold line in the third column of Table II). In addition, a digital precision, expressed as a number of bits, is selected. In the example of Table II, an 8 bit precision is selected. From the selected precision, a factor is determined, which is the largest (or at most the largest) number to be expressed in said number of bits, in this case in 8 bits. In this example, the factor is selected 10 to be a large 8 bit number, i.e. 119. Now, the divider is found by dividing the largest signal difference value by the factor: 488.601/119 = 4096. Next, from the divider, a modified divider is derived by performing a 2log(divider) function: 2log (4096) = 12. Next, all signal difference values of the group of signal difference values are divided by the same divider, which results in the numbers in the fifth column in Table I (coded signal difference values), which are all 15 expressible in an 8 bit digital number. The coded signal difference values are rounded to the nearest integer.
The coded signal difference values and the modified divider are transmitted from the transmitter TX to the receiver RX, in a manner known per se.
In the second processor 4, the divider is regenerated from the modified divider by 20 performing a 2<modlfieddlvlder) function. The coded signal differences are multiplied by the corresponding divider to obtain decoded signal difference values, as illustrated in the sixth column of Table III. Due to rounding errors (e.g. rounding the coded signal difference values -8- to the nearest integer), the decoded signal difference values (sixth column in Table III) which can be obtained from the coded signal difference values (fifth column in Table III) by multiplication thereof by the divider (fourth column in Table III, right-hand side), deviate slightly from the (original) signal difference values (third column in Table III).
5 Instead of modifying the divider by performing a function operation on the divider, also a first look-up table can be used in the first processor, the look-up table linking values of the divider to values of a modified divider. A similar look-up table can be used in the second processor to obtain values of the divider from values of the modified divider.
In the embodiments of the invention illustrated above, a stream of 24 bit samples 10 forming a digital input signal for the first processor 2, may be regenerated in the second processor as a stream of 24 bit samples. Further, as illustrated, a group of five samples of 24 bit (fifteen bytes in total) is compressed into seven bytes, i.e. one divider (or modified divider) of two bytes, and five coded coded signal difference values of one byte each. Accordingly, the compression rate 15/7 may be better than 50%.
15 For a delay in the system, the sample time multiplied by the group size may be taken.
As an example, for a 40 kHz sampling rate, the delay in the different embodiments is 25 ps multiplied by 5 for the first processor and for the second processor, so 25-5-2 = 250 ps, being extremely low.
In the system according to the invention, offset drift may occur due to rounding errors 20 or data loss in the transmission path. These drifts can cause overflow in the digital output signal resulting in noise in the analog output signal. In an embodiment, this is compensated by a digital highpass filter in the second processor 4 preventing offset drift, and boundary checking preventing said overflow.
As required, detailed embodiments of the present invention are disclosed herein; 25 however, it is to be understood that the disclosed embodiments are merely exemplary of the invention, which can be embodied in various forms. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a basis for the claims and as a representative basis for teaching one skilled in the art to variously employ the present invention in virtually any appropriately detailed structure. Further, the 30 terms and phrases used herein are not intended to be limiting, but rather, to provide an understandable description of the invention.
The terms "a" or "an", as used herein, are defined as one or more than one. The term plurality, as used herein, is defined as two or more than two. The term another, as used herein, is defined as at least a second or more. The terms including and/or having, as used 35 herein, are defined as comprising (i.e., open language, not excluding other elements or steps). Any reference signs in the claims should not be construed as limiting the scope of the claims or the invention.
-9-
The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.
The term coupled, as used herein, is defined as connected, although not necessarily directly, and not necessarily mechanically.
5 A single processor or other unit may be replaced by several interacting processing units performing different functions to fulfil the functions of several items recited in the claims. The invention may be defined by the following clauses 1-13:
CLAUSES
10 1. Method for processing a digital input signal containing a sequence of input signal sample values, the method comprising: determining signal difference values between pairs of subsequent input signal sample values; 15 determining a divider for a group of subsequent signal difference values; coding the subsequent signal difference values by dividing each signal difference value of the group of subsequent signal difference values by the divider to obtain a group of coded signal difference values; transmitting and receiving the group of coded signal difference values, and the divider; 20 decoding the coded signal difference values by multiplying each coded signal difference value of the group of coded signal difference values by the corresponding divider to obtain a group of decoded signal difference values; and determining a digital output signal containing subsequent output sample values from the decoded signal difference values by adding a decoded signal difference value to a sum of 25 previous decoded signal difference values. 1 2
Method for coding a digital input signal containing a sequence of input signal sample values, the coding method comprising: determining signal difference values between pairs of subsequent input signal sample 30 values; determining a divider for a group of subsequent signal difference values; coding the subsequent signal difference values by dividing each signal difference value of the group of subsequent signal difference values by the divider to obtain a group of coded signal difference values.
35 2
Method for decoding a digital input signal containing a sequence of input signal sample values, and coded by the method of clause 2, the decoding method comprising: -10- decoding the coded signal difference values by multiplying each coded signal difference value of the group of coded signal difference values by the corresponding divider to obtain a group of decoded signal difference values; and determining a digital output signal containing subsequent output sample values from the 5 decoded signal difference values by adding a decoded signal difference value to a sum of previous decoded signal difference values.
4. Method according to clause 1 or 2, wherein the step of determining a divider of a group of subsequent signal difference values comprises: 10 selecting a digital precision expressed as a number of bits; determining a factor being at most equal to the largest number to be expressed in said number of bits; determining the largest signal difference value of the group of subsequent signal difference values; 15 dividing said largest signal difference value by said factor to obtain said divider.
5. Method according to any of clauses 1 -4, further comprising: performing an operation on the divider, before transmission thereof, to obtain a modified divider; 20 performing an inverse operation on the modified divider, after transmission thereof, to obtain the divider.
6. Method according to clause 5, wherein the operation comprises taking the square root of the divider, and wherein the inverse operation comprises squaring the modified divider.
25 7. Method according to clause 5, wherein the operation comprises performing a 1log(x) operation on the divider, and wherein the inverse operation comprises performing a 2X operation on the modified divider.
30 8. Method according to any of clauses 5-7, wherein the operation comprises: selecting a modified divider in a first look-up table linking dividers to modified dividers, and wherein the inverse operation comprises: selecting a divider in a second look-up table linking modified dividers to dividers.
35 9. Method according to any of clauses 1 -3, wherein the digital input signal is obtained by converting an analog input signal into the digital input signal at a predetermined sample rate.
-11 - 10. Method according to clause 1 or 3, wherein an analog output signal is obtained by converting the digital output signal into the analog output signal.
11. System for processing a digital input signal containing a sequence of input signal 5 sample values, the system comprising: a first processor for determining signal difference values between pairs of subsequent input signal sample values, for determining a divider of a group of subsequent signal difference values, and for coding the subsequent signal difference values by dividing each signal difference value of the group of subsequent signal difference values by the divider to 10 obtain a group of coded signal difference values; a transmitter for transmitting the group of coded signal difference values, and the divider; a receiver for receiving the group of coded signal difference values, and the divider; a second processor for decoding the received coded signal difference values by 15 multiplying each coded signal difference value of the group of coded signal difference values by the corresponding divider to obtain a group of decoded signal difference values; and for determining a digital output signal containing subsequent output sample values from the decoded signal difference values by adding a decoded signal difference value to a sum of previous decoded signal difference values.
20 12. System for coding a digital input signal containing a sequence of input signal sample values, the coding system comprising: a first processor for determining signal difference values between pairs of subsequent input signal sample values, for determining a divider of a group of subsequent signal 25 difference values, and for coding the subsequent signal difference values by dividing each signal difference value of the group of subsequent signal difference values by the divider to obtain a group of coded signal difference values.
13. System for decoding a digital input signal containing a sequence of input signal sample 30 values, and coded by the system of clause 12, the decoding system comprising: a second processor for decoding the coded signal difference values by multiplying each coded signal difference value of the group of coded signal difference values by the corresponding divider to obtain a group of decoded signal difference values, and for determining a digital output signal containing subsequent output sample values from the 35 decoded signal difference values by adding a decoded signal difference value to a sum of previous decoded signal difference values.

Claims (13)

1. Werkwijze voor het verwerken van een digitaal ingangssignaal dat een opeenvolging 5 van ingangssignaalbemonsteringswaarden bevat, waarbij de werkwijze omvat: bepalen van signaalverschilwaarden tussen paren opeenvolgende ingangssignaalbemonsteringswaarden; bepalen van een deeltal van een groep opeenvolgende signaalverschilwaarden; coderen van de opeenvolgende signaalverschilwaarden door het delen van elke 10 signaalverschilwaarde van de groep opeenvolgende signaalverschilwaarden door het deeltal voor het verkrijgen van een groep gecodeerde signaalverschilwaarden; zenden en ontvangen van de groep gecodeerde signaalverschilwaarden, en het deeltal; decoderen van de gecodeerde signaalverschilwaarden door het vermenigvuldigen van 15 elke gecodeerde signaalverschilwaarde van de groep gecodeerde signaalverschilwaarden met het bijbehorende deeltal voor het verkrijgen van een groep gedecodeerde signaalverschilwaarden; en bepalen van een digitaal uitgangssignaal dat opeenvolgende uitgangsbemonsteringswaarden van de gedecodeerde signaalverschilwaarden bevat door het 20 optellen van een gedecodeerde signaalverschilwaarde bij een som van voorheen gedecodeerde signaalverschilwaarden.A method for processing a digital input signal comprising a sequence of input signal sampling values, the method comprising: determining signal difference values between pairs of successive input signal sampling values; determining a share of a group of consecutive signal difference values; coding the successive signal difference values by dividing each signal difference value of the group of successive signal difference values by the division number to obtain a group of coded signal difference values; sending and receiving the group of coded signal difference values, and the division number; decoding the coded signal difference values by multiplying each coded signal difference value of the group of coded signal difference values with the corresponding divisor to obtain a group of decoded signal difference values; and determining a digital output signal that contains successive output sampling values of the decoded signal difference values by adding a decoded signal difference value to a sum of previously decoded signal difference values. 2. Werkwijze voor het coderen van een digitaal ingangssignaal dat een opeenvolging van ingangssignaalbemonsteringswaarden bevat, waarbij de codeerwerkwijze omvat: 25 bepalen van signaalverschilwaarden tussen paren opeenvolgende ingangssignaalbemonsteringswaarden; bepalen van een deeltal van een groep opeenvolgende signaalverschilwaarden; coderen van de opeenvolgende signaalverschilwaarden door het delen van elke signaalverschilwaarde van de groep opeenvolgende signaalverschilwaarden door het deeltal 30 voor het verkrijgen van een groep gecodeerde signaalverschilwaarden.2. A method for coding a digital input signal containing a sequence of input signal sampling values, the coding method comprising: determining signal difference values between pairs of successive input signal sampling values; determining a share of a group of consecutive signal difference values; coding the successive signal difference values by dividing each signal difference value of the group of successive signal difference values by the division number 30 to obtain a group of coded signal difference values. 3. Werkwijze voor het decoderen van een digitaal ingangssignaal dat een opeenvolging van ingangssignaalbemonsteringswaarden bevat, en dat is gecodeerd door de werkwijze van conclusie 2, waarbij de decodeerwerkwijze omvat: 35 decoderen van de gecodeerde signaalverschilwaarden door het vermenigvuldigen van elke gecodeerde signaalverschilwaarde van de groep gecodeerde signaalverschilwaarden -13- met het bijbehorende deeltal voor het verkrijgen van een groep gedecodeerde signaalverschilwaarden; en bepalen van een digitaal uitgangssignaal dat opeenvolgende uitgangsbemonsteringswaarden van de gedecodeerde signaalverschilwaarden bevat door het 5 optellen van een gedecodeerde signaalverschilwaarde bij een som van voorheen gedecodeerde signaalverschilwaarden.3. A method for decoding a digital input signal that contains a sequence of input signal sampling values, and which is coded by the method of claim 2, wherein the decoding method comprises: decoding the coded signal difference values by multiplying each coded signal difference value of the coded group of values signal difference values -13- with the associated divisor for obtaining a group of decoded signal difference values; and determining a digital output signal that contains successive output sampling values of the decoded signal difference values by adding a decoded signal difference value to a sum of previously decoded signal difference values. 4. Werkwijze volgens conclusie 1 of 2, waarbij de stap van het bepalen van een deeltal van een groep opeenvolgende signaalverschilwaarden omvat: 10 selecteren van een digitale nauwkeurigheid uitgedrukt als een aantal bits; bepalen van een factor die het grootste in genoemd aantal bits uit te drukken getal is; bepalen van de grootste signaalverschilwaarde van de groep van opeenvolgende signaalverschilwaarden; delen van genoemde grootste signaalverschilwaarde door genoemde factor voor het 15 verkrijgen van genoemd deeltal.4. Method according to claim 1 or 2, wherein the step of determining a share of a group of consecutive signal difference values comprises: selecting a digital accuracy expressed as a number of bits; determining a factor that is the largest number to be expressed in said number of bits; determining the largest signal difference value of the group of consecutive signal difference values; dividing said largest signal difference value by said factor for obtaining said partial number. 5. Werkwijze volgens een van de conclusies 1 -4, verder omvattende: uitvoeren van een bewerking op het deeltal, voorafgaand aan verzending daarvan, voor het verkrijgen van een gewijzigd deeltal; 20 uitvoeren van een inverse bewerking op het gewijzigde deeltal, na zenden daarvan, voor het verkrijgen van het deeltal.The method of any one of claims 1 to 4, further comprising: performing an operation on the share prior to sending it to obtain a modified share number; 20 performing an inverse operation on the changed share, after sending, to obtain the share. 6. Werkwijze volgens conclusie 5, waarbij de bewerking het worteltrekken van het deeltal omvat, en waarbij de inverse bewerking het kwadrateren van het gewijzigde deeltal omvat. 25The method of claim 5, wherein the operation comprises rooting the dividend, and wherein the inverse operation comprises squaring the modified dividend. 25 7. Werkwijze volgens conclusie 5, waarbij de bewerking een 2log (x) bewerking op het deeltal omvat, en waarbij de inverse bewerking het uitvoeren van een 2X bewerking op het gewijzigde deeltal omvat.The method of claim 5, wherein the operation comprises a 2log (x) operation on the dividend, and wherein the inverse operation comprises performing a 2X operation on the modified dividend. 8. Werkwijze volgens een van de conclusies 5-7, waarbij de bewerking omvat: het selecteren van een gewijzigd deeltal in een eerste opzoektabel die deeltallen verbindt met gewijzigde deeltallen, en waarbij de inverse bewerking omvat: selecteren van een deeltal in een tweede opzoektabel die gewijzigde deeltallen 35 verbindt met deeltallen. -14-A method according to any of claims 5-7, wherein the operation comprises: selecting a modified share number in a first look-up table connecting share numbers to changed share numbers, and wherein the inverse operation comprises: selecting a share number in a second look-up table which changed partial numbers 35 connect with partial numbers. -14- 9. Werkwijze volgens een van de conclusies 1 -3, waarbij het digitale ingangssignaal wordt verkregen door het converteren van een analoog ingangssignaal naar het digitale ingangssignaal met een vooraf bepaalde bemonsteringssnelheid.The method of any one of claims 1 to 3, wherein the digital input signal is obtained by converting an analog input signal to the digital input signal with a predetermined sampling rate. 10. Werkwijze volgens conclusie 1 of 3, waarbij een analoog uitgangssignaal word verkregen door converteren van het digitale uitgangssignaal naar het analoge uitgangssignaal.The method of claim 1 or 3, wherein an analog output signal is obtained by converting the digital output signal to the analog output signal. 11. Systeem voor het verwerken van een digitaal ingangssignaal dat een opeenvolging 10 van ingangssignaalbemonsteringswaarden bevat, waarbij het systeem omvat: een eerste verwerkingseenheid voor het bepalen van signaalverschilwaarden tussen paren opeenvolgende ingangssignaalbemonsteringswaarden, voor het bepalen van een deeltal van een groep opeenvolgende signaalverschilwaarden, en voor het coderen van de opeenvolgende signaalverschilwaarden door het delen van elke signaalverschilwaarde van 15 de groep opeenvolgende signaalverschilwaarden door het deeltal voor het verkrijgen van een groep gecodeerde signaalverschilwaarden; een zender voor het zenden van de groep gecodeerde signaalverschilwaarden, en het deeltal; een ontvanger voor het ontvangen van de groep gecodeerde signaalverschilwaarden, 20 en het deeltal; een tweede verwerkingseenheid voor het decoderen van de gecodeerde signaalverschilwaarden door het vermenigvuldigen van elke gecodeerde signaalverschilwaarde van de groep gecodeerde signaalverschilwaarden met het bijbehorende deeltal voor het verkrijgen van een groep gedecodeerde 25 signaalverschilwaarden, en voor het bepalen van een digitaal uitgangssignaal dat opeenvolgende uitgangsbemonsteringswaarden van de gedecodeerde signaalverschilwaarden bevat door het optellen van een gedecodeerde signaalverschilwaarde bij een som van voorheen gedecodeerde signaalverschilwaarden.A system for processing a digital input signal comprising a sequence of input signal sampling values, the system comprising: a first processing unit for determining signal difference values between pairs of successive input signal sampling values, for determining a partial of a group of consecutive signal difference values, and for coding the successive signal difference values by dividing each signal difference value of the group of successive signal difference values by the division number to obtain a group of coded signal difference values; a transmitter for transmitting the group of coded signal difference values, and the division number; a receiver for receiving the group of coded signal difference values, 20 and the division number; a second processing unit for decoding the coded signal difference values by multiplying each coded signal difference value of the group of coded signal difference values with the associated divisor for obtaining a group of decoded signal difference values, and for determining a digital output signal having successive output sampling values of the decoded signal difference values contained by adding a decoded signal difference value to a sum of previously decoded signal difference values. 12. Systeem voor het coderen van een digitaal ingangssignaal dat een opeenvolging van ingangssignaalbemonsteringswaarden bevat, waarbij het codeersysteem omvat: een eerste verwerkingseenheid voor het bepalen van signaalverschilwaarden tussen paren opeenvolgende ingangssignaalbemonsteringswaarden, voor het bepalen van een deeltal van een groep opeenvolgende signaalverschilwaarden, en voor het coderen van de 35 opeenvolgende signaalverschilwaarden door het delen van elke signaalverschilwaarde van de groep opeenvolgende signaalverschilwaarden door het deeltal voor het verkrijgen van een groep gecodeerde signaalverschilwaarden. -15-A system for coding a digital input signal comprising a sequence of input signal sampling values, the coding system comprising: a first processing unit for determining signal difference values between pairs of successive input signal sampling values, for determining a partial of a group of consecutive signal difference values, and for coding the consecutive signal difference values by dividing each signal difference value from the group of consecutive signal difference values by the division number to obtain a group of coded signal difference values. -15- 13. Systeem voor het decoderen van een digitaal ingangssignaal dat een opeenvolging van ingangssignaalbemonsteringswaarden bevat, en dat is gecodeerd door het systeem van conclusie 12, waarbij het decodeersysteem omvat: 5 een tweede verwerkingseenheid voor het decoderen van de gecodeerde signaalverschilwaarden door het vermenigvuldigen van elke gecodeerde signaalverschilwaarde van de groep gecodeerde signaalverschilwaarden met het bijbehorende deeltal voor het verkrijgen van een groep gedecodeerde signaalverschilwaarden, en voor het bepalen van een digitaal uitgangssignaal dat 10 opeenvolgende uitgangsbemonsteringswaarden van de gedecodeerde signaalverschilwaarden bevat door het optellen van een gedecodeerde signaalverschilwaarde bij een som van voorheen gedecodeerde signaalverschilwaarden.13. A system for decoding a digital input signal that contains a sequence of input signal sampling values, and which is coded by the system of claim 12, wherein the decoding system comprises: a second processing unit for decoding the coded signal difference values by multiplying each coded signal difference value signal difference value of the group of coded signal difference values with the associated partial for obtaining a group of decoded signal difference values, and for determining a digital output signal containing 10 consecutive output sampling values of the decoded signal difference values by adding a decoded signal difference value to a sum of previously decoded signal difference values .
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