NL1043676B1 - Above supply pll-charge pump - Google Patents

Abstract

2 SUMMARY The tuning range of voltage controlled oscillators (VCOs) is determined by 10 varactors as available in deep-submicron processes. It is shown that the voltage on varactors needs to be higher than the supply voltage in order to obtain the maximum VCO tuning range. When the VCO is applied in a phase-locked loop (PLL), the supply voltage of the charge-pump then limits the maximum tuning range. By using a intelligent charge-pump in combination with switchable PLL 15 loop-filter, the maximum tuning range can be recovered without the need for an extra supply voltage. 1043676

Description

ABOVE SUPPLY PLL-CHARGE PUMP

STATE OF THE ART For communications systems like GSM, Bluetooth, WLAN, ele, and radar systems at 24, 80 or 80 GHz, one of the essential specifications is the generation of various signals with the correct frequency (fi. as Local Oscillator (LOY), which needs to be as clean as possible (Le. a minimum amount of phase-noiss). The larger the tuning range, the more signals can be received. In the case of frequency-modulated-continuous-wave (FMCW) radar, the tuning range directly defines the resolution res that can be obtained {resolution is here defined as being able to distinguish between two objects in the range profile): res = {2 bw) where © denotes the speed of light {37108 mis) and bw denotes the maximum tuning rage of the VCO. For a tuning rage of 1 GHz, the resolution amounts to

0.15 m, while a tuning range of 5 GHz resulls in a resolution of C03 mor om. | is clear that a large tuning range is advantageous. A voltags-controlled oscillator is usually applied in a phase-locked loop, as shown in Figure 1. The VOO signal is used directly (VCO output) or after a frequency multiplier (MVC) in the application. The VCO signal is frequency-divided down with a factor N, and used as input lo a phase-frequency delecior, A phase- frequency detector (PFD) compares the VCO-frequency-divided signal with a signal at a reference frequency (usually a crystal oscillator). The difference in phasefirequency makes the charge-pump act to add or sublract a charge from the PlLl-loopfilter, and thus correct the VCO frequency. In a proper working PLL the VCO frequency is a multiple of the reference frequency: NCO = Nfreference where N is the division factor, This division factor can also be {delia-sigma) modulated to obtain fractional division numbers.

Figure 2 shows the tuning curve of a VCO using a standard varactor in a deep- submicron CMOS process. The tuning curve shows an S-shaped behaviour, The 40 tuning voltage is along the x-axis, while the VOO frequency is along the y-axis. For voltages below 0.0 V, the frequency hardly changes any longer. Above 1.8 V, the frequency also changes minimally. The optimum tuning voltage tuning is then between, say, O and 1.8 V, leading to a frequency variation between 53.5 and 64.8 GHz, or a 11.3 GHz tuning ranges. The maximum allowed voltage on the deep- 45 submicron transistors is around 1.3 V for 10 years reliable functioning of these transistors. if these transistors would be used above 1.3 V, breakdown can occur and functionality of the circuit can no longer be guaranteed.

Another important design aspect is that must circuits can be designed to function down to 1.0 V, which is important again for lowering power dissipation. But this 50 would seriously compromise the VCO tuning range. if the varactor is used between 0.0 and 1.0 V {no margin in the circuit if the minkmium power supply voltage is 1.0 V), the maximum VCO frequency variation is only 53.5 to 82.5 GHz or 9 GHz tuning range. This is 26% lower than the maximum tuning range of 11.3 GHz for the 0 to 1.8 V tuning voltage. Being able to 55 use the maximum tuning range makes the difference In performance in mass. produced integrated circuits. it is therefore advantageous fo be able to generate varactorNVC O tuning voltages above the power supply voltage (assuming the 1V minimum supply voltage). Using only part of the tuning range of the varactor resulis in a smaller tuning 60 range, and/or lower Q of the resonator (thus a worse VCO phase-noise), or a higher sensitivity of the VCO to ripple on supply and/or ripple on the tuning voltage.

The standard solution to this problem would be to use a separate, external, power 65 supply voltage {fi 2 V) to supply the chargs-pump with. This supply needs te be very clean without any ripple from any switched-made power supply, and has to be stable and be able to cope with the {fast) pulses generated by the phase- frequency detector, and the amount of current that the charge-pump would have to supply to the loop-filer, This would mean a separate supply domain, and extra 70 design effort and investment in the application, Reference [1] shows another possible solution whereby the pulses of the phase- frequency detector and charge-pump ars used in a voltages multiplier (sce Figure 4 in 11} to amplify the output voltage of the charge-pump before it is supplied 10 75 the PLL loop-filter. The multiplication factor is given by multiplication factor = n*(Vin-Vdiode) where nis the number of stages in the multiplier, Vin is the input voltage of the multiplier, and Vdiode is the vollage drop over the diodes used in the multiplier. Vdiode is in the order of 0.5 ta 0.7 V pending the type of diode and the current 850 flowing through the diode. This multiplication factor is a non-linear function of the input voltage, especially for low input voltages. This sxtra nondlinearity will hamper the design of an optimum PLL, Also the multiplication factor has to be high as Vin- Vode is only 0.3-0.5 V.

85 His the goal of this patent application to find a solution to this problem and present a circuit that increases the oscillator tuning range and makes it possible the implement sverything on-silicon.

FIGURES Figure 1 shows an example of a standard PLL.

Figure 2 shows the tuning curve of a voltage controlled oscillator in a desp- submicron CMOS process. Figure 3 shows the combination of the standard charge-pump and the standard joop-ifter,

95 Figure 4 shows the combination of the new charge-pump and the new loop-filter. Figure 5 shows the timing of the various phases. Figure 6 shows an alternative loop-filter. Figure 7 shows an alternative implementation using switches around C2.

100 DETAILED DESCRIPTION The problem is that the tuning voltage of the varactor has to become higher than the power supply voltage. And this should be accomplished without using an external supply, be fully integrated on-silicon and with little or no ripple.

105 The varactor is a mos-like device with the gate-connection as tune input. The low- frequency input impedance of the varactor is very high, larger than 10 Mohm or even higher. Leakage current at the varactor input are measured in the nA range. Therefore, very low demands are requested from the PLL-loopfilter in terms of supplying current to the varactor.

110 The phase-frequency detector in a PLL generates a small pulse that is proportional to the phaseffrequency difference between the PLL-reference signal and the VC O-divided signal. When the PLL is in lock, the pulses become very narrow. The charge-pump uses these pulses to charge/discharge the capacitors in 115 the PLL loopfilter, usually with peak currents in the order of mA's.

By smartly charging/discharging the capacitors in the loop-filter and using switches to redistribute the charge, a voltage doubler can be implemented in the joop-filter. So the charge-pump remains as is with a 1 V supply. The loop-filter 120 becomes more complex, and incorporates switches compared to the traditional solution,

Figure 4 shows an example of the new loop-Hiter which incorporates a voltage multiplier. When the charge-pump is off, the charge is redistributed to double the 125 voltage on the loop filter. A sample-and-hold is used fo minimise the ripple during transitions. Part of the loop-filter is then further used to reduce the ripple due to the charging and discharging of the capacitors in the loop filter, The performance is explained with reference to Figure 4 and the timing of the 130 various phases as shown in Figure 5. The loop-filter consists of the series connection R1-C1, with C2 parallel to R1-C1, followed by a filter section R3-C3. The names are consistent with the standard loop-filter as shown in Figure 3. Capacitor C1 is split in two parts Cla and C1b, each with value C1/2. In phase 1, the switches denoted with ph1 ars closed, and the combination of R1-C1-C2-R3 135 looks the same as in Figure 3. During this phase 1, the capacitors Cia, C1b and C2 are charged/discharged by the PLL charge-pump. Capacitor Cla and C1b will be charged to a voltage Vesichp*Tpulse/l1, where ichp is the charge-pump current and Tpulse is the duration of the pulse (assuming C1 >> C2).

In phase 2 the switches denoted with ph2 are closed and the switched denoted 140 with phi are open. Capacitor Cth remains connected to ground, while capacitor Cla is switched between C1b and R1. The voltage over the combined Cia and C1b capacitors is now 2*Ve, thus effectively doubled. As C2 is usually much smaller than C1, a small charge from Cla and C1b will be redistributed to C2.

145 if the redistribution of charge to C2 is not acceptable, the same procedure used to C1 can also be used to C2. Split CZ in 2 separate parts C2a and C2b, during phase 1 charge C2a and C2b in parallel, and during phase 2 connect C2a and C2b in series, just as done with Cla and C1b.

150 During phase 3 the switch denoted ph3 will be closed so that the voltage over R1- C1-C2 can be transferred to C3 and to the varactor. Capacitor C3 effectively functions as a sample-and-hold for the varactor voltage. By opening the switch denoted with ph3, any jump in voltage due to the 2x multiplication in C1, are non- visible to the varactor, thus minimizing disturbances and ripple. The combination 155 R3-C3 also acts as filter for any ripple. An extra capacitance may be added just after the switch ph3 to act as better sample&hold capacitor, Due to the switching of the capacitances, the effective capacitance in the loop- filter changes. it can be shown that the effective capacitance Cleffective due to 160 the switching is given by: Cteffective= phieffective™2*Cirphleffective* C112 where phieffective is the part of the period that ph is active, ph2effective is the part of the period that ph2 is active and C1 is the nominal capacitance. Assume that phfeffective is 5% (the PLL is in lock or close to being in lock), ph2effective is 165 94% (1% left to realise non-overlapping clocks for phi and ph2), and C1 is 100 DF, then C7 _effeclive can be calculated to be: Cleffective=0.05"2%100+0.94*100/2=10+47=57 pF.

Due to the change in effective capacitances, the phase-locked-loop loop- 170 behaviour changes: the loop-bandwidth and loop-stability have changed. Assuming very-short pulses from the phase-frequency detector, the effective capacitance approaches C1/2 for in-lock conditions and 2°C1 for out-of-lock conditions; a factor 4 variation. By switching resistor R1 any change in stability can be compensated for. A similar situation occurs when both C1 and C2 are 175 switched.

The phases in Figure 5 have on-purpose been chosen to be non-overlapping to prevent any disturbances in the desired behavior. In some cases the phase phd maybe the same as ph2 without (any) loss of overall performance. Similarly ph2 180 maybe the same as the inverse of ph1, without (any loss) loss of overall performance. In general, all signal (ph1, ph2 and ph3) maybe combined and derived and/or similar to 1 signal.

The signal ph is directly derived from the phase-frequency detector and the 185 charge-pump; f£ ís more or less the sams as the on-time of the current sources in the charge-pump. Signals ph2 and ph3 can easily be derived from ph by simple logic circuits.

In some cases the charge-pump cannot generate voltages close to zero due to the 180 transistors entering the triode region. Dus to the doubling, the varactor voltage is 2 mes this triode voltage, and essentially some tuning range is lost. As this is at the paint in the curve where the tuning sensitivity is small, this loss is minor. Alternatively, if the tuning voltage is measured, the doubling function can be switched off in such stuations.

195 The shown sstample doubles the voltage in the loop-filter. Using somewhat more complicated cirouitry gives the possibility to triple or quadruple {or even more) the voltags.

200 Sometimes the PLL loop-filter is split in several segments for easier integration, see Reference [2]. A first part is the integration, while in the second part the proportional part with a zero and pole is realised. Two chargs-pumps are required, one for each loop-filter part. For the experienced designer, there should be no difficulty transferring the principle described in this patent application to a split 205 loop-filter. The disadvantage in the structure described in Reference [2] is that an operational amplifier is needed to sum the integral and proportional parts. Figure 8 shows an alternative loop-filter implementation, which also uses two chargs- pumps {chp_a and chp _b), which together drive the loop-filter. The advantage of this loop-filter above the loop-filler in Reference [2] is that a separate voltage 219 combiner is no longer needed. For the experienced designer, there should be no difficulty in designing a voltage multiplication version of this loop-filter,

Evan in the case that the full varactor control range is not needed because the tuning range requirement is not that large, the applied technique can be used for 215 switching on/off capacitances in parallel to the oscillator resonator circuit.

Due to the use of higher voltage the switch series resistance will be reduced and the Q willbe improved, Figure 7 shows an alternative implementaion where C2 is used for voltages 220 doubling.

During phase 1 (switches denoted phi are closed while other switches are open), capacitor C2a and C2b are charged in parallel.

During phase 2 {switches denoted ph1 are open and those denoted with ph? are closed), capacitors CzZa and C2b are placed in series, thus doubling the voltage.

As in Figure 4, C3 acts as sample and hold capactor.

The version shown in Figure 7 225 has the advantage that C2 is less important in the PLL dynamic behaviour, and variations in capacitance value (first C2a and C2n are in parallel, later they are in series) is easier absorbed in the overall loop behaviour, in Figure 4 the capacitor C1 and C2 (if charge redistribution is not acceptable) are 230 used for the voltage doubling.

In Figure 7 C2 Is used for the voltage doubling.

His also possible to use capacitor C3 for the voltage doubling: split capacitor C3 into 2 capacitors C3a and C3b and charge both capacitors during phi.

During ph2 Cla and C3b are placed In series and thus generate the double voltage.

For optimum performance, another sampladhold switch phd (with sample&hold capacitor C4) 235 should then be placed after R3-C3. Also the case where both C1 and CZ are split both into 2 capacitors (so 4 in total) and each is, in a first period, charged, while in a second part of the period, the capacitors are placed in series.

So several versions can be created: use only C1, 240 use only C2, or the combination of both.

in some applications/processes the tuning curve of the varactor and oscillator can be shifted to include negative voligges.

The principle disclosed here can also be applied for that application by subtracting the voltage on the capacitor instead of 245 the addition used above, The switches in 0.a.

Figure 4 can be implementad by only pmos devices, by only nmos devices, or by a combination of both.

Some of these switches will have to handle 2 V, so thick oxide devices may have to be used.

Also the gate drive-level 250 will have to be 2 V io have the proper switching function.

The backgates of the switching devices also require 2 V to prevent the scurce-backgate and drain- backgats going forward, This extra 2 V only requires a minimal amount of current {only leakage and switching current), and may be generated using a standard on- silicon normal Dickon multiplier or a cross-coupled switched-capacitor voltage 255 doubler, see Ti.

Reference [3] The phase-locked-loop is mainly implemented with analog circuits and transfer functions.

Soms or all parts of the phase-locked loop may be Implemented in the digital domain using boolean logic circuits, see 11. Reference [4]. The principle 260 =xplaned above may also be used in these so-called digital phase-locked loops.

Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, Fom a study of the drawings and figures, the disclosure, and the appended claims.

In the claims, the 265 word" comprising” does not exclude other elements or steps, and the indefinite article "a ” or "an" does not exclude a plurality.

The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measured cannot be used to advantage.

Any reference signs in the claims should not be construed as limiting the scope. 278

REFERENCES {1] Phase-lock circuit, US 8590459. {21 J. Craninckx et al, “A Fully Integrated CMOS DCS-1800 Frequency Synthesizer”, Journal of Solid-State Circuits, Vol 33, no 12, December 1988. 275 [3] hitps:/en.wikipedia org/wiki/Voltage_ multiplier

[4] R.Staszewski et al, ‘All-Digital TX Frequency Synthesizer and Discrete-Time Receiver for Bluetooth Radio in 130-nm CMOS’ IEEE Journal of Solid-State Circuits, Vol.38, No 12, December 2004.

Claims (1)

1. 280 CONCLUSIES

   1. Een fass-vergrendelde lus waarbij in het lusfiller een spanningsverveel- voudiging wordt gerealiseerd.

   2. Als een van ds voorgaande conclusies waarbij de spanningsverveeslvou- diging plaatsvind door sen of meerdere condensator{en) in oen eerste fase 285 (paralisi) op ie laden en daama mbt schakelaars in gen weeds fase de condensatoren in serie te schakelen.

   3. Als esn van de voorgaande conclusies waarbij de Tase-vergrendelde lus bestaat uil een gestuurde oscillator, en/of een delerketen, enfof sen fase- frekwentie vergelijker, en/of een ladingspomp, en/of een lusfilter en/of een 290 frekwentievermenigvuldiger.

   4. Als een van de voorgaande conclusies waarbij als een van de onderdelen sen houd-cirouit is, waarbij de klok een derde fase heeft, zodat de rimpeling in het uitgangssignaal wordt geminimaliseerd.

   5. Als een van de voorgaande conclusies waarbij de verschillende fases van het 295 klok-signaal gerelateerd zijn aan het klok-signaal van de signalen afkomstig uit de fase-frequentie detector en ladingspomp.

   8. Als een van de voorgaande claims waarbij alternative lusfilters worden gebruikt zoals een lusfilter dat is gespitst in een integratie-deel en een proportioneel deel.

   309 7. Als een van de voorgaande conclusies waarbij de weerstanden in het lus-filter ook worden geschakeld zodanig dat maximale stabilitelt wordt gerealiseerd.

   8. Als ean van de voorgaands conclusies waarbij een extra (hoge) spanning wordt gerealiseerd die gebruik! wordt om de back-gates van de schakelaars {pmos devices) van voldoende hoge spanning te voorzien.

   305 9. Als een van de voorgaande claims, waarbij de fase-frequentie detector op sen hogere harmonische (als sub-sampler) werkt.

   10. Als een van de voorgaande conclusies waarbij de signalen phi, phz en ph3 zijn gecombineerd in 1 signaal.

   11. Als een van de voorgaands claims waarbij de fase-vergrendelde lus een 310 digitale fase-vergrendelde Ius is, waarbij een of meerdere onderdelen zoals de fase-frequenctie detector, time-to-digital converter, ladingspomp, en het lusfilter in het digitale domain zijn gerealiseerd.

   12. Als sen van de voorgaande conclusies waarbij een negatieve spanning wordt gegenereerd voor de varactor-oscilator combinatie om het optimale 315 afstemmingsbereik te realiseren.

   13. Als een van de voorgaande claims waarbij de oscillator een ringoscillator is. 14 Als een van de voorgaande conclusies waarbij het circuit in CMOS, BICMOS, GaN, GaAs en/of SO! technologie is geïmplementeerd. 320