NL1010154C2 - Ion implantation method for semiconductor manufacture e.g. DRAM - by determining surface layer thickness through which implantation can be carried out, providing it and implanting ions into substrate - Google Patents

Abstract

The method for implanting ions into a substrate (132) involves determining a desired uniform surface layer (128) thickness through which implantation can be carried out in order to minimise defect formation. A surface layer is provided with the desired surface layer thickness. Ions are implanting into the substrate through the surface layer. The substrate is provided with a concave shaped surface region (130). The surface layer is provided with a concave shaped surface portion. Ions are implanted into the substrate through the concave shaped surface portion and the concave shaped surface region. The substrate includes silicon and the substrate surface is implanted through is a (100) crystallographic plane. A conducting material is provided as the surface layer.

Description

METHOD FOR PREVENTING THE FORMATION OF ΙΟΝΕΝΙΜΡΕΑΝΤΑΉΕ-INDUCED EDGES

The present invention relates to a method of preventing defect formation in a substrate subjected to ion implantation followed by annealing, comprising the steps of providing a substrate having a surface, removing material from the surface to form a first region, implanting ions into the substrate through the first region and annealing the substrate.

This patent application is a division of the Dutch patent application NL-A-1005932.

A method as mentioned above is known from US patent US-A-4,891,327. This patent describes a method for manufacturing a memory cell in a dynamic random access memory (Dynamic Random

Access Memory, DRAM). A trench is formed in a substrate with a width-height ratio of at least substantially one. Ions are implanted in the substrate in the right side wall of the trench and the bottom side of the trench.

There is a continuous tendency to increase the storage density of 20 integrated circuit memories to provide higher levels of data storage on a single chip. Higher density memories provide storage that is generally more compact and more often cheaper on a per-bit basis than an equivalent amount of storage provided on multiple chips. It has generally been possible to provide these higher storage levels at equivalent or improving performance levels compared to previous lower density chips. Historically, the density of integrated circuit devices has been partially increased by decreasing the size of structures such as wiring leads and transistor gates, and decreasing the separation between the structures that make up the integrated circuit device. Reducing the size of circuit structures is commonly referred to as limiting the "design rules" used for the fabrication of the integrated circuit device.

In dynamic random access memories (DRAMs), information is typically stored by selectively charging or discharging each capacitor from an array of capacitors formed on the surface of a semiconductor substrate. Typically, a single bit of binary information is stored on each capacitor by connecting a discharged capacitor state to a logic zero and connecting a charged capacitor state to a logic one. The surface area of the electrodes of the memory capacitors determines the amount of charge that can be stored on each of the capacitors for a given operating voltage, for the electrode separation that can be reliably fabricated, and for the dielectric constant of the capacitor dielectric typically used between the electrodes of the charge storage capacitor. Read and write operations are performed in memory by selectively coupling the charge storage capacitor with a bit line for transferring charge to or from the charge storage capacitor. The selective coupling of the charge storage capacitor to the bit line is typically accomplished using a transfer field effect transistor (FET). The bit line contact 15 is typically made to one of the source / drain electrodes of the transfer FET and the charge storage capacitor is typically formed in contact with the other of the source / drain electrodes of the transfer FET. Word line signals are applied to the gate of the FET to connect one electrode of the charge storage capacitor to the bit line contact via the transfer FET, thereby facilitating transfer of charge between the charge storage capacitor and the bit line.

Figure 1 shows in schematic cross-section two memory cells of a DRAM in an intermediate manufacturing stage. The illustrated DRAM cells are formed on a P-type substrate 10 and include thick field oxide regions 12 to provide isolation from other adjacent memory cells. A gate oxide layer 14 is formed by thermal oxidation on a portion of the active device region between the field oxidation regions, and polysilicon gate electrodes 16 are formed on the gate oxide layer 14. The two gate electrodes 16 illustrated in Figure 1 are part of two independent transfer FETs for the two illustrated memory cells. Polysilicon gate electrodes 16 are formed by applying an undoped polysilicon layer over the substrate, typically using low pressure chemical vapor deposition (LPCVD), and then implanting impurities into the polysilicon and 1010154 3 activating the impurities to make the polysilicon layer conductive. The gate electrodes are then patterned using conventional photolithography techniques. A layer of silicon oxide 18 is provided over the polysilicon gate electrodes 16 to secure the gate electrodes in subsequent processing steps and, often, to serve as an etching stopper for subsequent etching steps. Side oxide spacer structures 20 are also provided adjacent the gate electrodes during the source / drain implantation process (described below). At the same time that the gate electrodes 16 are formed, wiring leads 22 connecting different gate electrodes 10 are formed on field oxide regions 12. Since the wiring leads are generally formed in the same process used to form the gate electrodes 16, the wiring leads have a similar structure consisting of polysilicon leads 22 covered by oxide layers 24 with side oxide spacer structures 26 formed adjacent to the wiring leads 22.

Doped source / drain regions 28, 30, 32 are formed on both sides of the polysilicon gate electrodes 16 to define the channel regions of the transfer FETs. The source / drain region 30 common to the transfer FETs will serve as the bit line contact for the two illustrated memory cells. Lightly doped drain (LDD) structures are often used in small design line memory transistors of the type mainly used in modern memory and logic devices. LDD source / drain regions 28, 30 and 32 are typically formed in a two-step process, starting with a relatively low level dopant implantation which is self-aligned with the polysilicon gate electrodes 16. Spacer Oxide regions 20 are then formed on both sides of the gate electrodes 16 by first applying a layer of CVD oxide over the device and then anisotropically etching back the oxide layer to the substrate over the source / drain regions 28, 30 and 32 to uncover. Resetting the CVD oxide layer generates the spacer oxide regions 20 on both sides of the polysilicon gate electrodes 16 and on both sides of the polysilicon wiring leads 22. After the spacer oxide regions 20 are provided on both sides of the polysilicon gate Electrodes 16, a second, heavier ion implantation is made in the source / drain regions 28, 30 and 32, self-aligned with the spacer oxide regions 20 to complete the source / drain regions.

After the formation of the transfer FETs of the DRAM cells, processing continues to form the charge storage capacitors and the bit line contacts by first applying an insulating silicon oxide layer 34 over the structure of Figure 1 using chemical vapor deposition ( CVD). The resulting structure is shown in Figure 2. Apertures 36 are then formed by conventional photolithography through the silicon oxide layer 34 to expose the source / drain regions 28,32 of the substrate. Referring now to Figure 3, an undoped polysilicon 38 layer is then applied by low pressure chemical vapor deposition (LPCVD) over the surface of the device and within the openings 36 in contact with source / drain regions 28, 32. The polysilicon layer 38 will form part of the bottom electrode of the charge storage capacitor for the DRAM memory cells. The layer is doped by ion implantation and annealing, and then the bottom electrodes 38 are defined by photolithography. A dielectric capacitor layer 40, such as a two-layer structure of silicon nitride and silicon oxide, is provided over the surfaces of the lower electrodes 38. Upper capacitor electrodes 42 are formed by applying, doping and patterning a layer of polysilicon, creating the structure shown in Figure 4 is illustrated.

Processing continues to cover a layer of intermediate dielectric material, such as a doped glass applied by atmospheric pressure CVD of a TEOS source gas, over the structure of Figure 4. A bit line contact 46 is opened by the dielectric layer 44 by conventional photolithography to expose the common source / drain contact 30. The bit line contact 50 is then formed, typically by providing an additional bit line contact ion implantation and then providing one or more layers of metal sputter or CVD applied over the surface of the layer 44 and within the opening 46 as illustrated in Figure 5. The bit line is then patterned and further processing is performed to complete the device.

Reducing the design rules used to form the device illustrated in Figure 5 places increased demands on many of the structures illustrated in Figure 5, along with the processing techniques that are * Λι. · Η, ί Γ | i 5 used to form the structures. The formation of source / drain regions becomes more critical because of the relatively shallower and narrower source / drain regions contained in reduced dimension memory cells. There is a greater need for the control of implantation energies and the degree of diffusion of source / drain-5 regions to achieve small device sizes. There is also a need to maintain highly conductive source / drain regions to maintain the high performance of these structures. One aspect of maintaining high conductivity levels is to prevent the formation of defective structures in the source / drain regions.

Various types of crystal lattice defect structures can be formed in the processes of implanting dopant ions into semiconductor substrates and annealing the substrates to activate the implanted dopants. The ion implantation doses used to form many semiconductor switching components can make the crystalline silicon semiconductor substrate 15 into which the dopant ions have been implanted amorphous. The substrate must then be annealed to activate implantation and often to recrystallize the amorphous zone. Recrystallization of implanted silicon substrates takes place by solid-phase epitaxial (SPE) growth (SPE = solid-phase epitaxial). SPE growth is a process in which the substrate is heated to a temperature below the melting point of the substrate material. Crystal growth occurs by solid-state transport and continues across the boundary between the crystalline (implanted or non-implanted) portion of the substrate and the amorphous implanted region of the substrate. The recrystallization takes place incrementally, the direction of recrystallization of each incremented amorphous region being determined by the orientation of the crystalline region on which the recrystallization takes place. Therefore, the orientation of the crystalline substrate at the interface of the crystalline region and the amorphous region will determine the directions of SPE growth.

Due to the shape of the boundary of the amorphous region, the SPE growth can continue over several crystalline planes. Various studies have indicated that SPE growth that occurs over different crystalline planes can lead to the formation of defects in the crystal. For example, the joining together of growth faces corresponding to two different crystal planes can lead to the formation of extensive defect structures in recrystallized silicon substrates.

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Other residual defects can be introduced into the crystal lattice, both by implantation and by other processes. For example, the presence of gate layers and sidewall spacer layers on the substrate can introduce compressive stresses to the underlying material, particularly during subsequent thermal processing steps. The presence of such voltages can generate defects such as grating errors and can increase grating errors.

Certain types of defects known as projected range defects (PRDs) and end-of-range defects (ERDs) can be formed in implanted and annealed areas of the substrate. PRDs and ERDs are secondary defects (lattice or lead defects), where PRDs are near the region of maximum implanted ion concentration and ERDs are near the amorphous crystalline interface after implantation. These defects are believed to result from vertical SPE growth of amorphous silicon, that is, growth perpendicular to the silicon surface, and the defects may include lattice error loops buried within the implanted area. The location and density of PRDs and ERDs are related to the energy and dose of the implantation ions. Another type of defect that involves recrystallization of a silicon made amorphous by ion implantation is the mask edge defect (MED). MEDs are believed to be lattice errors resulting from bringing recrystallization fronts of vertical and lateral SPE growth together. During the annealing and recrystallization process, the lattice errors formed from the meeting SPE growth fronts tend to agglomerate when additional epitaxial layers are formed, the defects growing in a structure that has been reported to be similar to a grain boundary. This enlarged defect structure can affect electron transport if it is placed along a main direction of current flow. Such defect structures can be formed near the lateral edges of the implantation zone at or near the substrate surface, often at the location where a recrystallization substrate surface is adjacent to another structure on the surface of the substrate, and can lead to junction leakage problems.

The object of the present invention is to prevent defects which are formed after recrystallization of silicon semiconductor substrates amorphousized by, for example, ion implantation.

This object is achieved by a method of the type defined at the beginning of the row <<j ^ 7, wherein the first region is formed at least substantially concave.

This method has the advantage that the fouling during recrystallization takes place in a controlled manner so that no defects occur.

Certain preferred embodiments of the invention include a method of controlling the shape of a recrystallization interface so that SPE (solid phase epitaxial) growth takes place mainly along a series of preferred directions.

After the surface layer is placed on the substrate, the implantation is performed. Glow then activates the implantation and recrystallizes any amorphous region.

Embodiments of the invention are described with reference to the accompanying drawings which, for illustrative purposes, are schematic and not drawn to scale.

Figures 1-5 show cross sections of a conventional prior art DRAM at various stages of manufacture.

Figure 6 shows a cross section of an ion implantation zone for a bit line contact.

Figure 7 shows a cross section of contact edge defects formed during recrystallization and annealing of the implantation zone of Figure 6.

Figure 8 shows a cross section of an implantation profile in a substrate having a generally flat surface.

Figure 9 shows a cross section of a substrate with a surface layer through which implantation is performed.

Figure 10 shows several dimensions related to implantation through a surface layer and into a substrate.

Figure 11 shows a cross section of a substrate with a curved surface part according to embodiments of the present invention.

Figure 12 shows a cross section of a substrate with a curved surface and a curved surface layer according to embodiments of the present invention.

Figure 13 shows a cross section of a substrate with a generally flat surface and a curved surface layer according to embodiments of the present invention.

Figure 14 shows a cross section of a DRAM at an intermediate processing stage according to embodiments of the present invention.

Figure 15 shows a cross section of a DRAM including a bit line contact formed according to embodiments of the present invention.

Figure 16 shows a cross section of a DRAM in an intermediate processing stage with a curved surface for implantation therethrough according to embodiments of the present invention.

A typical bit line contact region 30 as seen in Figure 5 can be subjected to three ion implantation steps and between one and three annealing steps in a typical manufacturing process. At least one annealing step is usually required to electrically activate the dopants and to remedy at least part of the lattice damage caused by the ion implantation steps. Typical implantation dosages for high density, shallow junction devices can make part or all of the contact area amorphous. Annealing is carried out in such cases to recrystallize the amorphous zone. Recrystallization is believed to proceed through solid phase epitaxial growth (SPE), in which a solid phase transformation takes place transforming the amorphous zone into a crystalline structure by atomic transport and rearrangement between the amorphous and crystalline regions. The recrystallization can proceed in directions generally perpendicular to the boundary of the amorphous region. Therefore, the orientation of each incremental recrystallized region depends on the orientation of the crystalline region from which the recrystallization proceeds. As a result, the orientation of the crystalline substrate at the interface between the crystalline part of the substrate and the amorphous part determines the crystalline directions along which the recrystallization proceeds.

The recrystallization of amorphous silicon regions can effect the formation of a variety of defects. Projected range defects (PRDs) and end-of-range defects (ERDs) are secondary defects (typically lattice error loops) that are formed within the implanted region of the substrate during SPE recrystallization of amorphous silicon. PRDs are found near the region of maximum implanted ion concentration and ERDs are found; near the amorphous crystalline interface after implantation. These defects are believed to be the result of vertical SPE growth of amorphous silicon. The location and density of PRDs and ERDs relate to the energy and dose of the implantation ions. Another type of defect related to recrystallization of a silicon made amorphous by ion transplantation is the mask edge defect (MED). MEDs are typically located near the corners of the recrystallized zone below or near mask edges. The formation of MEDs during recrystallization of the amorphous zone depends on the direction of crystallographic growth. SPE growth rates are different along different crystallographic directions, and MEDs are believed to result from the joining of the recrystallization fronts of both vertical and lateral SPE growth.

Figures 6 and 7 illustrate the formation of mask edge defects in an implanted and annealed bit line contact region, where ion implantation is performed on the substrate 110 having an implant region defined, for example, using photolithographic (illustrated) or direct beam writing techniques. The implantation is typically performed perpendicular to the substrate 110 surface in the 112 direction, thereby forming the implantation and amorphous zone 114. As shown in Figure 6, the shape of the implantation zone approaches a Gaussian distribution, with a maximum implantation concentration being applied to the widest part of zone 114. After implantation, an annealing step is performed to recrystallize the amorphous zone 114. During the annealing 20, the recrystallization occurs by solid phase epitaxial (SEP) regrowth along the boundary between the crystalline portion of the substrate and the amorphous region of the substrate. The recrystallization takes place in layers, the direction of recrystallization of each layer being determined by the orientation of the crystalline region on which the recrystallization takes place. Therefore, the directions of crystal growth depend on the orientation of the crystalline region at the interface.

As seen in Figure 7, recrystallization can take place in multiple directions, including vertically in the [001] direction and laterally along the [110] direction. Recrystallization generally begins at the interface between the amorphous zone and crystalline regions in the substrate, and takes place at different rates in 30 different regions. As the crystal faces growing in different directions intersect, defects can be generated and held at the intersection between the crystal growth faces, as illustrated by arrows 113 and 115 in Figure 7. As crystal growth progresses through the amorphous zone, the 1 010154 and are retained along the faces where the crystal growth faces intersect during recrystallization, resulting in enlarged defect structures 116 in the substrate, which typically extend near the edge of the surface structures H1.

By controlling the depth and shape of the amorphous zone within the substrate, defect formation such as defects 116 shown in Figure 7 can be reduced. Appropriate design of the implantation and recrystallization process provides a process that favors specific directions of growth in the recrystallization process. In certain embodiments, it is desirable for the growth directions to be dominated by and / or limited to directions including the [100], [111], [211], [311] and [511] directions. For example, the angle between the [100] direction and other directions can be easily calculated or measured. The angle between the [100] and [111] directions is approximately 54.7 degrees for a cubic crystal. Edge defects have been found to be prevented when the angle between growth directions is about 54.7 degrees or less for a substrate oriented in the [100] direction. The angle between the [100] direction and the [211], [311] and [511] directions are all less than 54.7 degrees, with the angle between the [100] and [211] directions being approximately 35.3 degrees , the angle between the [100] and [311] directions is approximately 25.2 degrees, and the angle between the [100] and [511] directions is approximately 15.8 degrees. A variety of processes have been developed by the present inventor to ensure that recrystallization will proceed along crystallographic directions forming angles less than or equal to about 54.7 degrees with the [100] direction.

In certain embodiments, a surface layer of a material that may be polysilicon or an insulating agent such as a silicon oxide is placed on the surface of the substrate so that the implantation zone is partly within the surface layer and partly within the substrate. The layer may preferably be of at least substantially uniform thickness. By controlling the thickness of the surface layer, the shape of the recrystallization zone in the substrate can be controlled. An aspect of the invention provides a method of determining a minimum thickness for the surface layer to ensure that crystal growing faces will intersect at an angle of the user's choice that is less than the maximum angle between growing surfaces, corresponding to avoiding the formation of extensive defect structures. The method is described below with reference to the geometry illustrated in Figure 8. The ion implantation profile 120 in a direction 124 perpendicular to the generally flat substrate surface 122 can be described by a Gaussian distribution, as seen in Figure 8. The implantation profile 120 extends in the substrate along the direction 124 and laterally extends to a maximum width at an intermediate depth within the implanted substrate. The location of the peak concentration of implanted ions extends along a line 126-126 ', which is generally at or near the maximum width portion of the profile 120. The two-dimensional profile can be characterized by a projected range Rp, a projected standard deviation 10 along the X direction ARp, and a projected standard deviation along the Y direction ΔΥ. These distances are characteristic of the ion implantation process and are influenced by the specific ion, the substrate, the energy of the implanted ions and the range of variations in the energy of the ions. The amorphous zone profile is believed to have the same general shape as the implantation concentration profile, the size of the amorphous zone being determined by a threshold energy.

In order to control the amorphous zone such that, after recrystallization, growth occurs in directions that prevent the formation of edge defects, the implantation can be performed by an at least uniformly thick surface layer 128 as shown in Figure 9, with part of the implanted distribution 130 is located in the surface layer 128, and part of the implantation distribution 130 is in the substrate 132. The surface layer can be formed from a wide variety of materials, such as, for example, polysilicon, other conductors such as heat-resistant metals or silicides, silicon oxide and various glass compositions. When the invention is applied to the bit line contact area, it is particularly preferred that the surface layer is a conductor such as polysilicon, a heat resistant metal such as a titanium, tungsten, tantalum or a silicide of a heat resistant metal. In this way, the surface layer does not need to be removed prior to forming the remainder of the bit line contact. The present inventor has observed that for certain embodiments, edge defect formation 30 is minimized when the intersection point between growth directions is 54.7 degrees or less. To determine a desired surface thickness layer t, it is assumed that the spatial distribution of the implantation profile is approximated by an elliptical contour. The right triangle formed by the radius of the ellipse at Θ = 54.7

λ T. ·. ::? f, A

At 12 degrees, the bottom of the surface layer 128 and the edge of the implantation divider 130 can be used to determine the minimum thickness t for the surface layer 128 applied to the substrate 132. As shown in Figure 10, the radius d of the ellipse at Θ = 54.7 degrees is determined by the following equation: 5 d = [(AYsinO) 2 + (ARpcosO) 2] 0'5 (1) where ΔΥ the projected standard deviation is along the y direction and ARp is the projected standard deviation along the x direction. Furthermore: 10 t - Rp = dcosO (2) where Rp is the projected range of implantation depth, and solve for thickness t: 15 t = dcosO + Rp (3)

Substitution of the radius d from the equation above: t = Rp + cos9 [[(AYsinO) 2 + (ARpcosO) 2] 0’5] (4) 20

When Θ = 54.7 degrees: t = Rp + 0.578 [[(AY) 2 (0.666) + (ARp) 2 (0.334)] 0’5] (5) 25

The values for Rp, ΔΥ and ARp depend on the energy used for implantation. Published results for certain elements are set forth in Table 1. The minimum surface layer thickness t for a number of ion species with various ion implantation energies are calculated and have the values shown in Table 1.

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Table 1 energy (KeV) 20 40 60 80

Rp (A) 15Ö 262 368 473

Axle ARp 56 96 133 169 ΔΥ 41 - 69 96 121 t 177 308 431 553

Rp 658 1277 Ï847 2380 B ARp 270 423 526 605 ΔΥ 290 483 638 761 t 822 1545 2195 2792

Rp 253 488 729 974 P ARp 114 201 288 367 ΔΥ 94 175 249 323 t 311 594 881 1170

Rp 3Ö 22Ö 299 375

Sb ARp 39 68 92 115 ΔΥ 30 49 66 82 t 149 252 343 430 5

Table 1. Published values for RP, ΔΥ and ARp in Angström and the calculated values for surface layer thickness t in Angström for As, B, P and Sb ions implanted in a silicon substrate at 20.40, 60 and 80 KeV.

10

It will be understood that, while the thickness t indicated in Table 1 is a minimum value for avoiding the formation of extensive defect structures, t will often also be an optimal thickness. As a result of normal processing variations, there will often be a variation in surface layer thickness. In most cases, the surface layer thickness t15 will have a variation of about 10% or less. For a given implantation energy, as the surface layer thickness t increases, the total implantation dose in the substrate becomes smaller and has less effect on the conductivity of the contact area. It is therefore typically desirable to keep the surface layer thickness at a small value if possible, although this is a less sensitive factor in the overall performance of the device.

As shown in Table 1, for an implantation of As ions using, for example, an energy of 20 keV, the thickness of the surface layer 128 of Figure 10 should be at least about 177 Angstroms. Using a surface layer of at least 177 angstroms in thickness, the formation of mask edge defects will be reduced because the angle between the [100] direction and 10 crystalline growth directions will be 54.7 degrees or less. The shape of the resulting amorphous region will control the growth directions so that the formation of defects including MEDs from interactions between vertical and lateral SPE growth will be minimized. Other embodiments of the present invention can provide different values for 0 depending on, for example, the substrate orientation and / or crystal structure.

Embodiments of the present invention can utilize a variety of substrate surface and surface layer morphologies. For example, a substrate may initially be formed with a drop in its surface. Alternatively, a substrate that has a generally flat surface can be subjected to processing steps to remove material to form a depression. For example, as shown in Figure 11, a substrate 130 may have a depression 136 to create an implantation zone 134 having an interface with a shape similar to that of the depression 136. The implantation zone 134 shown in Figure 11 shown leads to certain advantages due to the geometry of the front growth during recrystallization. The angle between the amorphous implantation zone 134 and the crystalline region of the substrate 130 can be modified by controlling the curvature of the depression 136. By controlling the curvature, one can minimize the interactions between vertical and lateral SPE growth during recrystallization. Certain embodiments of the invention have a depression extending below the original planar surface of the substrate, the depression defined by inwardly inclined sidewall regions 137 and a flatter or planar central region 139, as shown in Figure 11.

i

The depression 136 in the substrate 130 may, for example, be formed by 1 -1. ^

I! - J _ "-T

15 performing an isotropic etching step after a bit line contact opening is formed to the existing source / drain region of the transfer FET. In certain preferred embodiments, the depression may be concavely formed over at least a portion of its length, and may be fully curved along its length, or may be curved at both ends with a generally flat region in the center. Depending on the etching agent used or the etching agents used, the substantially concave shaped surface may have a more flattened or more curved appearance. The depression formed can undercut the side walls of the insulating layer extending above the bit line contact. In certain embodiments, a goal 10 is to avoid steep surface angles. After the etching step is completed, implantation is performed to form the resulting implantation zone 134. The implantation zone 134 will have an interface with the rest of the substrate that is similar in geometry to the curved surface 136, which will result in minimal defect-pin-pin interactions between lateral and vertical solid-phase epitaxial growth regions. As a result, defect formation will be reduced.

To further control the shape and / or depth of an implantation zone, a surface layer 146 may be placed on top of an at least substantially concave shaped surface 142 of a substrate 140 prior to implantation, as shown in Figure 12. Alternatively, a device similar to the device shown in Figure 12 may have a generally flat substrate surface 152 that has a generally concave shaped surface layer 156 disposed thereon, as shown in Figure 13. Such a curved surface layer 156 can be formed, for example, by applying a generally flat surface layer over the substrate and then etching a portion of the surface layer using an isotropic etchant. Subsequent implantation will lead to an implantation zone 154 in the substrate 150, the interface between the amorphous implantation zone 154 and the crystalline substrate 150 being curved in a similar manner to the curvature of the surface layer 156.

An example of a DRAM device fabricated in accordance with embodiments of the present invention is shown in Figure 14. The illustrated DRAM cells are formed on a P-type substrate 50 and include field oxide regions 52 for isolation of adjacent memory cells. Polysilicon gate electrodes 56 are formed on the gate oxide layer 14. Lightly doped source / drain 1010154 16 regions 68, 70 and 72 are formed on both sides of the polysilicon gate electrodes 56 to define the channel regions of the transfer FETs. The source / drain region 70 common to the transfer FETs will serve as the bit line contact for the two illustrated transfer FETs. Doped source / drain regions 68, 70 and 72 can be formed in a two-step process, first a relatively low level dopant implantation which is self-aligned with the polysilicon gate electrodes 56. Sidewall spacer oxide regions 64 are then formed adjacent to the gate electrodes by applying a layer of CVD oxide over the device and then anisotropically etching the oxide layer to expose the substrate over the source / drain regions 68, 70 and 72 to lay. Then, a second, heavier ion implantation is made in the source / drain regions 68, 70 and 72, self-aligned with the spacer oxide regions 64. Wiring lines 60 connecting different gate electrodes are formed on field oxide regions 52 at the same time as the gate electrodes 56 are formed. Similarly, sidewall oxide spacer structures 66 are formed along wiring leads 60 at the same time that sidewall oxide spacer structures 64 are formed.

After the FETs are formed, storage capacitors and bit line contacts are formed. According to embodiments of the present invention, a bit line contact may be opened through the device to expose the source / drain region 70 through the opening 80 using a technique such as photolithography and anisotropic etching to the source / drain surface. Then, a surface layer 82 is applied to the surface of the source / drain region 70 through which an implantation step is performed to further increase the conductivity of the bit line contact. The thickness of the surface layer will be related to the extent to which the directions of growth are desired to be limited and can be determined using the above equations 1.1-1.5. One or more annealing steps are then performed to activate the implanted ions and to recrystallize the amorphous zone. The surface layer 82 is preferably removed prior to the formation of the bit line contact 84 in the opening 80 when an insulating agent is used as the surface layer 82. In other embodiments in which a conductive material is used to form the layer 82, it may be preferable deserve to leave the material in place to reduce the number of 1 0101 54 17 processing steps. The bit line contact 84 (see Figure 15) may consist of one or more layers of metal sputtered or CVD disposed within the opening 80 and over a portion of the device.

In another embodiment, a DRAM structure similar to the structure shown in Figure 14 can be formed with a surface 86 that has a curved morphology through which implantation takes place to control the shape of the implantation zone. Such a structure can be formed by first masking and using an anisotropic etchant to etch part of the opening 80. After the anisotropic etching step, the bottom of the opening 80 will have a relatively flat surface. Another etching step is then performed using an isotropic etchant, such as a plasma derived from SF6, to form the curved surface 86, as illustrated in Figure 16. By implanting through the curved surface 86, the implant zone has desirably a similarly curved border so that, after annealing, recrystallization will take place along directions that minimize the formation of edge defects.

The DRAM of Figure 14 may also have a surface layer through which implantation is performed similar to the surface layer 136 shown in Figure 12. Such a curved surface layer could be obtained, for example, by etching the surface as described above with respect to Figure 16 and then applying the surface layer to the curved surface. The desired minimum thickness of such a surface layer can be determined using the above equations 1-5. Similarly, the DRAM substrate could also have a generally flat substrate surface with a curved surface layer similar to the surface layer 156 shown in Figure 13. Embodiments that require numerous processing steps, including, for example, multiple etching steps for the substrate surface and the surface layer, are generally not preferred because of the additional complexity and time required to perform the steps.

While the methods of preventing defect formation have been described here with respect to structures such as the DRAM in Figures 14-16, the methods described here can be used with other structures and processing steps. For example, embodiments of the present invention can be applied to both mask and maskless (direct ", v '; ..: 04 18 ion beam writing) implantation, since the implantation zone resulting from maskless implantation can have the same morphology as an implantation zone that results from conventional implantation using a mask While the present invention has been described with reference to certain preferred embodiments, it will be further understood that the present invention is not limited to the specific embodiments described herein, rather, the scope of the present invention defined by the following claims.

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Claims (12)

A method for preventing defect formation in a substrate that is subjected to ion implantation followed by annealing, comprising the steps of: 5 providing a substrate having a surface; removing material from the surface to define a first region; implanting ions into the substrate through the first region; and annealing the substrate, characterized in that the first region (134) is formed substantially concave. 10 The method of claim 1, wherein the substrate (130) has a surface (152) oriented perpendicular to the [100] crystallographic direction. The method of claim 1, wherein a depression (136) is formed by etching at least a portion of the substrate (130) using an isotropic etchant. The method of claim 1, further comprising the steps of: providing a surface layer (146) on the substrate (130) over the first region (134); and implanting ions into a source / drain region through the surface layer (146). The method of claim 4, further comprising the steps of removing the surface layer (146) from the substrate (130), and then annealing the source / drain region. The method of claim 4, further comprising the steps of annealing the source / drain region and then removing the surface layer (146) from the substrate (130). 30 The method of claim 1, wherein the step of removing material from the surface to define a first region (134) comprises forming a depression (136) having two sidewall sections (137) and a central section (139 ) between the side wall sections. The method of claim 7 comprising the additional step of forming the depression (136) such that the shape of the center portion (139) is flatter than the shape of the sidewall portions (137). The method of claim 7, comprising the additional step of providing a surface layer (156) on the first region (154), the surface layer (156) having a substantially uniform thickness over the first region (154). The method of claim 9, wherein the minimum thickness of the surface layer (156) is determined by the steps of: selecting a desired angle Θ between recrystallization directions; Determining a projected range of ion implantation distance Rp in the substrate; determining a projected standard deviation ARp along a first axis direction; and determining a projected standard deviation ΔΥ along a second axis direction; and solving the following equation for surface layer thickness t: t = Rp + cos9 [[(A YsinO) 2+ (ARpcosO) 2] 0.5]. The method of claim 1, further comprising the steps of: providing a surface layer (156) on the first region (154) prior to implanting ions into the substrate (150) through the first region (154); and implanting ions into the substrate (150) through the surface layer (156) and the first region (154). The method of claim 11, further comprising the step of removing material from the surface layer (156). ***** t | 1010154