MY8800159A - Signal transfer arrangement using a bus as a storage device - Google Patents

Signal transfer arrangement using a bus as a storage device

Info

Publication number
MY8800159A
MY8800159A MY159/88A MY8800159A MY8800159A MY 8800159 A MY8800159 A MY 8800159A MY 159/88 A MY159/88 A MY 159/88A MY 8800159 A MY8800159 A MY 8800159A MY 8800159 A MY8800159 A MY 8800159A
Authority
MY
Malaysia
Prior art keywords
bus
storage device
signal transfer
transfer arrangement
arrangement
Prior art date
Application number
MY159/88A
Other languages
English (en)
Inventor
Wyatt Virgil Dean
Kraft Wayne Richard
Thoma Nandor Gyorgy
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of MY8800159A publication Critical patent/MY8800159A/xx

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers
    • G06F13/4077—Precharging or discharging
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7839—Architectures of general purpose stored program computers comprising a single central processing unit with memory
    • G06F15/7864—Architectures of general purpose stored program computers comprising a single central processing unit with memory on more than one IC chip
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Microcomputers (AREA)
  • Logic Circuits (AREA)
MY159/88A 1981-12-24 1988-12-30 Signal transfer arrangement using a bus as a storage device MY8800159A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/334,185 US4567561A (en) 1981-12-24 1981-12-24 Large scale integration data processor signal transfer mechanism

Publications (1)

Publication Number Publication Date
MY8800159A true MY8800159A (en) 1988-12-31

Family

ID=23305998

Family Applications (1)

Application Number Title Priority Date Filing Date
MY159/88A MY8800159A (en) 1981-12-24 1988-12-30 Signal transfer arrangement using a bus as a storage device

Country Status (7)

Country Link
US (1) US4567561A (xx)
EP (1) EP0082980B1 (xx)
JP (1) JPS58114154A (xx)
CA (1) CA1180456A (xx)
DE (1) DE3271462D1 (xx)
MX (1) MX157488A (xx)
MY (1) MY8800159A (xx)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0152939B1 (en) * 1984-02-20 1993-07-28 Hitachi, Ltd. Arithmetic operation unit and arithmetic operation circuit
FR2560410B1 (fr) * 1984-02-24 1986-06-06 Efcis Circuit de precharge de bus de transfert de donnees logiques
JPH0738187B2 (ja) * 1984-03-23 1995-04-26 株式会社日立製作所 Ｌｓｉに構成されたマイクロコンピュータ
JPS63118856A (ja) * 1986-11-06 1988-05-23 Nec Corp シリアル・バス・インタフエ−ス回路
DE3866003D1 (de) * 1987-04-28 1991-12-12 Siemens Ag Schaltungsanordnung zur beschleunigten umladung des spannungspegels einer bus-leitung einer integrierten schaltung.
US4774422A (en) * 1987-05-01 1988-09-27 Digital Equipment Corporation High speed low pin count bus interface
US4829515A (en) * 1987-05-01 1989-05-09 Digital Equipment Corporation High performance low pin count bus interface
JPH0823821B2 (ja) * 1988-04-21 1996-03-06 松下電器産業株式会社 マイクロコンピュータ
EP0345493B1 (de) * 1988-06-08 1994-03-09 Landis & Gyr Technology Innovation AG Anordnung zur Überwachung, Steuerung und Regelung einer betriebstechnischen Anlage eines Gebäudeautomationssystems
JPH02132917A (ja) * 1988-11-14 1990-05-22 Toshiba Corp バスドライバー集積回路
CA2008071A1 (en) * 1989-01-27 1990-07-27 Jeffrey S. Watters Pump bus to avoid indeterminacy in reading variable bit field
CA2278129A1 (en) * 1997-01-22 1998-07-23 Gerd Mattern Method and apparatus for playing a time-limited dart game
DE19961727A1 (de) * 1999-12-21 2001-07-05 Micronas Gmbh Schaltungsanordnung mit einer Datenübertragungsvorrichtung
US8064269B2 (en) 2008-05-02 2011-11-22 Micron Technology, Inc. Apparatus and methods having majority bit detection

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3938094A (en) * 1971-08-31 1976-02-10 Texas Instruments Incorporated Computing system bus
JPS49128630A (xx) * 1973-04-09 1974-12-10
US4045684A (en) * 1976-01-19 1977-08-30 Hewlett-Packard Company Information transfer bus circuit with signal loss compensation
US4075606A (en) * 1976-02-13 1978-02-21 E-Systems, Inc. Self-memorizing data bus system for random access data transfer
US4144589A (en) * 1977-07-08 1979-03-13 Xerox Corporation Precharged data line driver

Also Published As

Publication number Publication date
JPS58114154A (ja) 1983-07-07
EP0082980A1 (en) 1983-07-06
US4567561A (en) 1986-01-28
DE3271462D1 (en) 1986-07-03
CA1180456A (en) 1985-01-02
JPH0218498B2 (xx) 1990-04-25
MX157488A (es) 1988-11-25
EP0082980B1 (en) 1986-05-28

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