MY191085A - Lead frame, lead frame package, and method for manufacturing same - Google Patents

Lead frame, lead frame package, and method for manufacturing same

Info

Publication number
MY191085A
MY191085A MYPI2018701818A MYPI2018701818A MY191085A MY 191085 A MY191085 A MY 191085A MY PI2018701818 A MYPI2018701818 A MY PI2018701818A MY PI2018701818 A MYPI2018701818 A MY PI2018701818A MY 191085 A MY191085 A MY 191085A
Authority
MY
Malaysia
Prior art keywords
lead frame
face
manufacturing same
package
main body
Prior art date
Application number
MYPI2018701818A
Inventor
KUBO Kimihiko
FURUNO Ryota
Original Assignee
Mitsui High Tec
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsui High Tec filed Critical Mitsui High Tec
Publication of MY191085A publication Critical patent/MY191085A/en

Links

Classifications

    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/60—Electroplating characterised by the structure or texture of the layers
    • C25D5/615—Microstructure of the layers, e.g. mixed structure
    • C25D5/617—Crystalline layers
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D21/00—Processes for servicing or operating cells for electrolytic coating
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/18—Electroplating using modulated, pulsed or reversing current
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/60—Electroplating characterised by the structure or texture of the layers
    • C25D5/605—Surface topography of the layers, e.g. rough, dendritic or nodular layers
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/60—Electroplating characterised by the structure or texture of the layers
    • C25D5/605—Surface topography of the layers, e.g. rough, dendritic or nodular layers
    • C25D5/611—Smooth layers
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00—Electroplating characterised by the article coated
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Organic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Metallurgy (AREA)
  • Materials Engineering (AREA)
  • Electrochemistry (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Electroplating Methods And Accessories (AREA)

Abstract

Provided is a method of manufacturing a lead frame (I 0) including a lead frame main body (11) and a plating film (12) on a surface thereof. The manufacturing method includes a plating step of performing plating treatment to dispose a first electrode (32) connected to a polarity inversion power source (30) so as to face a first main face (lla) of a lead frame main body (I I) and to dispose a second electrode ( 42) connected to a pulse power source ( 40) so as to face a second main face (11 b) opposite to the first main face (lla) and fonning the plating film (12) on the first main face (11 a), the second main face ( 11 b ), and a side face (11 c) of the lead frame main body (11 ). (FIG. 5)
MYPI2018701818A 2015-11-18 2016-10-11 Lead frame, lead frame package, and method for manufacturing same MY191085A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2015225542A JP6685112B2 (en) 2015-11-18 2015-11-18 Lead frame, lead frame package, and manufacturing method thereof
PCT/JP2016/080137 WO2017086063A1 (en) 2015-11-18 2016-10-11 Lead frame, lead frame package, and method for manufacturing same

Publications (1)

Publication Number Publication Date
MY191085A true MY191085A (en) 2022-05-30

Family

ID=58718702

Family Applications (1)

Application Number Title Priority Date Filing Date
MYPI2018701818A MY191085A (en) 2015-11-18 2016-10-11 Lead frame, lead frame package, and method for manufacturing same

Country Status (6)

Country Link
JP (1) JP6685112B2 (en)
CN (1) CN108352376B (en)
MY (1) MY191085A (en)
SG (1) SG11201803826YA (en)
TW (1) TWI651825B (en)
WO (1) WO2017086063A1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109468670B (en) * 2018-11-16 2021-03-26 中山品高电子材料有限公司 Method for electroplating copper layer on lead frame
US11562948B2 (en) * 2019-11-04 2023-01-24 Mediatek Inc. Semiconductor package having step cut sawn into molding compound along perimeter of the semiconductor package
CN112760702A (en) * 2020-12-24 2021-05-07 铜陵蓝盾丰山微电子有限公司 Silver plating device for lead frame
US20240145356A1 (en) * 2021-09-03 2024-05-02 Dai Nippon Printing Co., Ltd. Lead frame and manufacturing method thereof

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4329678B2 (en) * 2004-11-11 2009-09-09 株式会社デンソー Manufacturing method of lead frame used in semiconductor device
JP4857594B2 (en) * 2005-04-26 2012-01-18 大日本印刷株式会社 Circuit member and method of manufacturing circuit member
JP6093646B2 (en) * 2013-05-14 2017-03-08 新光電気工業株式会社 Manufacturing method of plating film
CN203333784U (en) * 2013-06-18 2013-12-11 中山品高电子材料有限公司 Double-sided local plating equipment for lead frame

Also Published As

Publication number Publication date
JP2017098291A (en) 2017-06-01
TW201729377A (en) 2017-08-16
CN108352376B (en) 2021-04-16
JP6685112B2 (en) 2020-04-22
CN108352376A (en) 2018-07-31
WO2017086063A1 (en) 2017-05-26
TWI651825B (en) 2019-02-21
SG11201803826YA (en) 2018-06-28

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