MY164421A - A method of producing vertical nanowires - Google Patents

A method of producing vertical nanowires

Info

Publication number
MY164421A
MY164421A MYPI2012701094A MYPI2012701094A MY164421A MY 164421 A MY164421 A MY 164421A MY PI2012701094 A MYPI2012701094 A MY PI2012701094A MY PI2012701094 A MYPI2012701094 A MY PI2012701094A MY 164421 A MY164421 A MY 164421A
Authority
MY
Malaysia
Prior art keywords
nanowires
gold catalyst
substrate
nitride layer
silicon
Prior art date
Application number
MYPI2012701094A
Inventor
Bien Chia Sheng Daniel
Aun Shih Teh
Wai Yee Lee
Anuar Abd Wahid Khairul
Original Assignee
Mimos Berhad
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mimos Berhad filed Critical Mimos Berhad
Priority to MYPI2012701094A priority Critical patent/MY164421A/en
Priority to PCT/MY2013/000227 priority patent/WO2014088405A1/en
Publication of MY164421A publication Critical patent/MY164421A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02551—Group 12/16 materials
    • H01L21/02554—Oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02603—Nanowires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • H01L21/02645—Seed materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02653—Vapour-liquid-solid growth

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Catalysts (AREA)

Abstract

A METHOD OF PRODUCING VERTICAL NANOWIRES USING SINGLE CATALYST MATERIAL IS PROVIDED, THE METHOD INCLUDES THE STEPS OF DEPOSITING AN INSULATING OXIDE OR NITRIDE LAYER (101) ON A SUBSTRATE (105) SURFACE, DEPOSITING A GOLD CATALYST LAYER (103) ON TOP OF THE INSULATING OXIDE OR NITRIDE LAYER (101), ANNEALING THE SUBSTRATE (105) WITH GOLD CATALYST AT TEMPERATURE ABOVE 350°C, SUCH THAT NANOPARTICLES ARE OF DIAMETER IN RANGE OF 1 TO 100 NM, GROWING ZINC OXIDE NANOWIRES FROM EXPOSED GOLD CATALYST BY CHEMICAL VAPOUR DEPOSITION (CVD) WITH DIETHYLZINC AS A PRECURSOR, AND GROWING SILICON NANOWIRES (107) FROM REMAINING GOLD CATALYST NANOPARTICLES WITH SILICON AS PRECURSOR, SUCH THAT VERTICAL TYPE ZINC OXIDE NANOWIRES ARE PRODUCED AND LATERALLY CONNECTED BY SILICON NANOWIRES (107) WHEREIN THE INSULATING OXIDE OR NITRIDE LAYER (101) IS NOT REQUIRED WHEN THE SUBSTRATE (105) IS INSULATIVE MATERIAL. THE MOST ILLUSTRATIVE DRAWING:
MYPI2012701094A 2012-12-06 2012-12-06 A method of producing vertical nanowires MY164421A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
MYPI2012701094A MY164421A (en) 2012-12-06 2012-12-06 A method of producing vertical nanowires
PCT/MY2013/000227 WO2014088405A1 (en) 2012-12-06 2013-12-03 A method of producing nanowires of two different materials

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
MYPI2012701094A MY164421A (en) 2012-12-06 2012-12-06 A method of producing vertical nanowires

Publications (1)

Publication Number Publication Date
MY164421A true MY164421A (en) 2017-12-15

Family

ID=50023817

Family Applications (1)

Application Number Title Priority Date Filing Date
MYPI2012701094A MY164421A (en) 2012-12-06 2012-12-06 A method of producing vertical nanowires

Country Status (2)

Country Link
MY (1) MY164421A (en)
WO (1) WO2014088405A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114291839B (en) * 2022-01-07 2024-02-02 辽宁师范大学 Low-cost superfine beta-Ga 2 O 3 Method for preparing nanowire

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7339184B2 (en) 2004-07-07 2008-03-04 Nanosys, Inc Systems and methods for harvesting and integrating nanowires
US7608905B2 (en) 2006-10-17 2009-10-27 Hewlett-Packard Development Company, L.P. Independently addressable interdigitated nanowires
KR100902512B1 (en) * 2007-05-17 2009-06-15 삼성코닝정밀유리 주식회사 Method for growing GaN crystal on silicon substrate, method for manufacturing GaN-based light emitting device and GaN-based light emitting device
US8889455B2 (en) * 2009-12-08 2014-11-18 Zena Technologies, Inc. Manufacturing nanowire photo-detector grown on a back-side illuminated image sensor
FR2964982B1 (en) * 2010-09-22 2013-03-08 Commissariat Energie Atomique PROCESS FOR REMOVING METAL CATALYST RESIDUES ON SURFACE OF CATALYTICALLY GROWN-WIRE PRODUCTS
MY147415A (en) * 2010-11-24 2012-12-14 Mimos Berhad A method for nanowires and nanotubes growth

Also Published As

Publication number Publication date
WO2014088405A1 (en) 2014-06-12

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