MY129438A - Semiconductor device and method of fabricating the same - Google Patents

Semiconductor device and method of fabricating the same

Info

Publication number
MY129438A
MY129438A MYPI97004289A MYPI9704289A MY129438A MY 129438 A MY129438 A MY 129438A MY PI97004289 A MYPI97004289 A MY PI97004289A MY PI9704289 A MYPI9704289 A MY PI9704289A MY 129438 A MY129438 A MY 129438A
Authority
MY
Malaysia
Prior art keywords
semiconductor device
trench
fabricating
same
substrate
Prior art date
Application number
MYPI97004289A
Inventor
Makoto Kitano
Shuji Ikeda
Norio Suzuki
Hideo Miura
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of MY129438A publication Critical patent/MY129438A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H01L21/76235—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls trench shape altered by a local oxidation of silicon process step, e.g. trench corner rounding by LOCOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

IN A SEMICONDUCTOR DEVICE HAVING A TRENCH ISOLATION STRUCTURE, AFTER A TRENCH SURFACE IS SELECTIVELY OXIDIZED BY A CONVENTIONAL METHOD, AND OXIDATION PREVENTION FILM (3) IS REMOVED, THE ENTIRE SURFACE OF THE SUBSTRATE (1) IS AGAIN OXIDIZED WHILE ONLY AN OXIDE FILM ON THE SUBSTRATE (1) OR TRENCH SURFACE IS EXPOSED, AND RADIUS CURVATURE IS PROVIDED TO THE SHAPE OF THE OXIDE FILM NEAR THE TRENCH UPPER END PORTION (12). (FIGURES 2A-214)
MYPI97004289A 1996-09-17 1997-09-16 Semiconductor device and method of fabricating the same MY129438A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24444596A JP3611226B2 (en) 1996-09-17 1996-09-17 Semiconductor device and manufacturing method thereof

Publications (1)

Publication Number Publication Date
MY129438A true MY129438A (en) 2007-04-30

Family

ID=17118766

Family Applications (1)

Application Number Title Priority Date Filing Date
MYPI97004289A MY129438A (en) 1996-09-17 1997-09-16 Semiconductor device and method of fabricating the same

Country Status (6)

Country Link
JP (1) JP3611226B2 (en)
KR (1) KR100425064B1 (en)
CN (1) CN1161837C (en)
MY (1) MY129438A (en)
TW (1) TW360945B (en)
WO (1) WO1998012742A1 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW388100B (en) * 1997-02-18 2000-04-21 Hitachi Ulsi Eng Corp Semiconductor deivce and process for producing the same
US5811346A (en) * 1997-04-14 1998-09-22 Vlsi Technology, Inc. Silicon corner rounding in shallow trench isolation process
WO1999044223A2 (en) * 1998-02-27 1999-09-02 Lsi Logic Corporation Process of shallow trench isolating active devices to avoid sub-threshold kinks arising from corner effects without additional processing
JP3917327B2 (en) 1999-06-01 2007-05-23 株式会社ルネサステクノロジ Method and apparatus for manufacturing semiconductor device
JP2004095886A (en) 2002-08-30 2004-03-25 Fujitsu Ltd Semiconductor device and its manufacturing method
TWI253746B (en) * 2003-10-24 2006-04-21 Fujitsu Ltd Semiconductor device group and method for fabricating the same, and semiconductor device and method for fabricating the same
KR100584776B1 (en) * 2004-03-05 2006-05-29 삼성전자주식회사 Method of forming active structure, isolation and MOS transistor

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63234534A (en) * 1987-03-24 1988-09-29 Oki Electric Ind Co Ltd Manufacture of semiconductor element
KR960006714B1 (en) * 1990-05-28 1996-05-22 가부시끼가이샤 도시바 Semiconductor device fabrication process
JP3208575B2 (en) * 1991-08-16 2001-09-17 ソニー株式会社 Semiconductor device manufacturing method
US5316965A (en) * 1993-07-29 1994-05-31 Digital Equipment Corporation Method of decreasing the field oxide etch rate in isolation technology
JP2955459B2 (en) * 1993-12-20 1999-10-04 株式会社東芝 Method for manufacturing semiconductor device
US5536675A (en) * 1993-12-30 1996-07-16 Intel Corporation Isolation structure formation for semiconductor circuit fabrication

Also Published As

Publication number Publication date
CN1161837C (en) 2004-08-11
KR100425064B1 (en) 2004-03-30
KR20000036123A (en) 2000-06-26
TW360945B (en) 1999-06-11
JP3611226B2 (en) 2005-01-19
JPH1092919A (en) 1998-04-10
WO1998012742A1 (en) 1998-03-26
CN1231064A (en) 1999-10-06

Similar Documents

Publication Publication Date Title
EP0459397A3 (en) Semiconductor device having a trench for device isolation and method of fabricating the same
TW353215B (en) Novel shallow trench isolation technique
MY130168A (en) Semiconductor device and manufacturing method thereof
EP0660391A3 (en) Semiconductor device with a trench isolation region and method of manufacturing the same.
EP0797245A3 (en) Method of manufacturing a vertical MOS semiconductor device
EP0772249A3 (en) Nitride semiconductor device
TW327700B (en) The method for using rough oxide mask to form isolating field oxide
EP0526212A3 (en) Method of forming isolated regions of oxide
EP2413352A3 (en) Soi wafer and method for producing soi wafer
EP0624899A3 (en) Oxidation of silicon nitride in semiconductor devices.
AU6178186A (en) Semiconductor device free from the current leakage through a semiconductor layer and method for manufacturing same
SG49343A1 (en) Semiconductor and a method for manufacturing an oxide film on the surface of a semiconductor substrate
EP0622842A3 (en) A method of forming a frontside contact to the silicon substrate of a SOI wafer.
EP0851492A3 (en) Surface-mounted substrate structure and method
EP0631309A3 (en) Semiconductor device with contact structure and method of manufacturing the same.
TW337040B (en) Method of doping trench sidewalls before trench etching
EP0236123A3 (en) A semiconductor device and method for preparing the same
TW350122B (en) Method of forming a shallow groove
EP0928019A3 (en) Reduced etch stop layer erosion
IT8421688A0 (en) PROCEDURE AND DEVICE FOR DIFFUSING ONE OR MORE IMPURITIES IN A SEMICONDUCTOR BODY.
MY129438A (en) Semiconductor device and method of fabricating the same
EP0908941A3 (en) Deposition of carbon into nitride layer for improved selectivity of oxide to nitride etchrate for self aligned contact etching
EP0349107A3 (en) Semiconductor devices
EP0997996A3 (en) Semiconductor device and method for fabricating the same
TW288205B (en) Process of fabricating high-density flat cell mask read only memory