MXPA99007296A - Inspected phase cycle with answer select - Google Patents

Abstract

The present invention relates to a video display apparatus for images from transmission sources having a standard or high definition, which may also display computer generated images. To display this range of sources, a horizontal frequency signal generator can be selectively operated at a plurality of frequencies. The generator comprises an oscillator (300) controlled for synchronized oscillation in a plurality of horizontal frequencies. A source (SW15) of synchronization pulses (5) is coupled to an input of a phase detector (50), which has another input coupled to the oscillator (300/400). The phase detector (50) generates an output signal (11) representing a phase difference between the inputs. A processor (200) is coupled to the phase detector (50) to process the output signal (11), and generate a control signal (201) to control the oscillator (300/400). The gain of the processor (200) is controlled in response to the selected frequencies of the plurality of frequencies.

Description

INSPECTED PHASE CYCLE WITH SELECTED RESPONSE This invention relates in general to the field of horizontal scanning systems for a video display apparatus, and in particular, to the synchronization and generation of horizontal index signals in systems that can operate at multiple horizontal scanning frequencies. In a video display apparatus, the scanning circuits are synchronized with a synchronization component, or synchronizer, derived from the input video signal. From there, a video display device that can operate at multiple horizontal scanning frequencies, must be able to synchronize up to a horizontal standard NTSC signal scanning frequency of nominally 15,734 kHz, or up to an Advanced Television Standards signal Committee, High Definition ATSC that has a horizontal scan frequency of nominally 33.670 kHz with 1080 active lines and interlaced scanning (10801). In addition to the synchronization of transmission video signals, the apparatus may be required to display non-transmitting, computer-generated video signals, such as, for example, a super-video or SVGA graphics adapter signal, that has a horizontal frequency of 37.880 kHz.

Horizontal frequency oscillators - which employ phase locked cycle control are widely known, and are used in video display devices. Secured double and triple phase cycles are also known, and are used to provide a functional separation between the potentially conflicting requirements of synchronization and the generation of scanning waveform. In a double-cycle configuration, a first cycle may be a conventional secured phase cycle, wherein an output of a controlled voltage oscillator, or an output divided therefrom, is compared to the horizontal synchronization pulses derived from the video signal that will be displayed. The second assured phase cycle, which for example operates at the same frequency, compares the output of the oscillator from the first cycle with a horizontal index pulse, for example, a retrace pulse voltage derived from, or representative of, the flow of the deflection current. The error voltage from the second phase comparison is used to generate a modulated amplitude impulse signal that determines the initiation of the deflection output device deactivation, and subsequently the initiation of the retrace, or the phase of each line within of the period of a vertical scan. The response of the first assured phase cycle can be optimized for the reception of marginal area of transmission video signals suffering from poor proportions of the signal to noise. These signals suggest that the response of the first assured phase cycle is relatively slow. In accordance with the above, the first cycle may have a narrow bandwidth to optimize the reduction of phase jumps. However, it is required that a video display apparatus can operate with signals from a variety of sources and with different horizontal frequencies. The response of the first phase of secured phase represents a compromise between a narrow bandwidth to minimize phase jumps, and a fast-cycle response of broadband amplitude capable of fast phase recovery. For example, a narrow-band amplitude cycle is suitable for synchronization by non-transmitting, low-noise computer-generated signals, whereas a fast broadband amplitude response is required, capable of fast phase recovery for the synchronization of video cartridge recorder (VCR) playback signals, where abrupt changes in the horizontal synchronization pulse phase may be present, therefore as 10 microseconds, between the beginning and the end of the vertical blanking interval. Accordingly, departures can be made in the respective cycle responses to provide adequate weak signal operation without significant overall degradation of receiver performance. The second assured phase cycle generally has a faster cycle response. In accordance with the above, the second assured phase cycle may have a wide bandwidth that allows it to track variations in the deviation current due to variations in the storage time of the horizontal output transistor, or to the effects of tuning of the high voltage transformer. This narrow tracking produces a straight grid without bends independent of the current load of the beam. The use of controlled voltage oscillators for the generation of the horizontal frequency signal is well known. It is known to employ an oscillator which operates at a multiple of the horizontal synchronization input frequency, to achieve synchronization by means of a down counter, with a selectable division between two stages. However, when the input signals have horizontal scanning frequencies that are not integer, simple halving or duplicating a down-counting rate of the oscillator can not immediately provide synchronization. In addition, the input signals "which are subject to widely different distortions, need different processing characteristics to provide optimized visual display operation.

The conflicting requirements of synchronization of the horizontal oscillator with multiple frequencies and synchronization signals from different sources, are conveniently solved by a configuration of the invention. A horizontal frequency signal generator can operate in a selectable manner in a plurality of frequencies. The generator comprises a controlled oscillator for synchronized oscillation in a plurality of horizontal frequencies. A synchronization pulse source is coupled to an input of a phase detector, which has another input coupled to the oscillator. The phase detector generates an output signal that represents a phase difference between the inputs. A processor is coupled to the phase detector to process the output signal and generate a control signal to control the oscillator. The gain of the processor is controlled in response to the selected frequencies of the plurality of frequencies. In a further inventive configuration, a synchronization circuit comprises a controlled voltage oscillator that generates a horizontal frequency signal at a plurality of frequencies. A synchronizing element synchronizes the controlled voltage oscillator with a horizontal synchronization pulse source. An active low pass filter is coupled to the synchronizing element to filter a voltage from the synchronizing element, to be coupled in order to synchronize the controlled voltage oscillator. The bandwidth of the active filter is changed in response to the operation at one of the plurality of frequencies. Figure 1 is a block diagram of an exemplary horizontal frequency oscillator employing three phase locked cycles with different configurations of the invention. Figure 2 is a schematic diagram of part of Figure 1, and shows a switched active filter of the invention.

Figure 3 shows a controlled voltage oscillator including the characteristics of the invention, which form part of Figure 1. Figure 4 is a schematic diagram of the switching interlock of the invention, which forms part of Figure 1.

Figure 5A is a graph illustrating the gain versus frequency characteristic of the active switched filter of the invention of Figure 2. Figure 5B is a graph illustrating the phase versus frequency characteristic of the active switched filter of the invention of the Figure 2. Figure 1 shows a horizontal frequency oscillator and a deviation amplifier that employs three phase locked cycles, and that can operate in a plurality of frequencies. In a first secured phase cycle 10, an input video display signal, for example, a standard definition NTSC signal, is coupled with a synchronization separator, SS, where the component of the horizontal synchronization signal is separated . A voltage-controlled oscillator has a frequency of 32. times a horizontal frequency of NTC, lFh, and is divided by 32 in a counter, illustrated as, +32. The signal of the split oscillator is coupled as an input with the PD phase detection, by the second input coupled with the separate synchronization component. The resulting phase error between the divided oscillator signal and the separate synchronization component is coupled from the phase detector, PD, to synchronize the controlled voltage oscillator of 32Fh. The functional elements of the secured phase cycle 10 form part of an integrated bus-controlled circuit, for example, type TA1276. The standard definition horizontal synchronization component from the secured phase cycle 10 is coupled with a selector switch of the synchronization source SWl5, which provides selection among a plurality of synchronization signals coupled as input sources, to synchronize the second and third cycles of the controlled horizontal oscillator IDO and 410, respectively. The selector switch SW15 is illustrated with three example synchronization sources, i.e., a standard definition NTSC synchronization signal, a high definition synchronization signal, for example, ATSC 10801, and a computer-generated SVGA synchronization signal.; however, the synchronization selection for the synchronization signal of the horizontal oscillator is not limited to these examples. The synchronization switch SW15 is controlled by the switching signal 15A, which is generated by the microcontroller 800 in response to a user control command, for example, as generated by a RC remote transmitter, which is communicated using IR wireless elements with the IRR receiver, 801, which inputs the remote control data to the microcontroller 800. The RC remote control allows to display the selection of the signal source, for example, by changing the TV transmission channels between the transmissions high definition and standard definition, or watch a computer program with a selectable visual display resolution. The three phase locked oscillators illustrated in Figure 1 are conveniently controlled to provide optimized operation, not only with the input signals of different frequencies, but also with the signals subject to time disturbances. During the visual display of the NTSC signals, cycles 10, 100 and 410 are used. However, the NTSC signals may originate from a transmission source, or a video cartridge recorder. The last source may be subject to synchronization phase disturbances, and therefore, these signal alterations are conveniently accommodated within the assured phase cycle 100 by means of a controlled selection of the low pass filter characteristic. The selection of the high definition signal inputs, for example, ATSC or SVGA signals, causes the assured phase cycle 10 to be derived, reducing the synchronization system to two cycles, for example, the assured phase cycle 100 and the secured phase cycle 410. Accordingly, microcontroller 800 is required to control the selection of input video display in response to user commands, to control the selection of the control synchronization source in response to the selection of the display visual, to control the frequency of the oscillator, the oscillator divider, and the characteristics of the low pass filter of the phase locked oscillator. The selected synchronization signal 5, from the switch 15, is coupled with an input of the phase detector 50, to facilitate the synchronization of the second assured phase cycle 100. At a second input to the phase detector 50, the signal is supplied to it 401, derived by dividing the signal from the controlled voltage oscillator 301. The resulting phase error signal 11 is filtered in low pass, and applied to control the controlled voltage oscillator 300, thereby achieving synchronization with the Horizontal synchronizer of the input video display signal. The third secured phase cycle 410 compares a signal from the controlled voltage oscillator VCO 300 with a signal related to the Hrt scan, for example, an impulse derived from the horizontal scan resulting from a scanning current generated by a scanning amplifier. 500. The center frequency of the horizontal oscillator 300 is determined by means of the control bus 420, for example, an I2C bus, which conveniently transmits data words that independently change the frequency of the oscillator and the characteristics of the low pass filter . In addition, a convenient protection circuit 600 prevents damage to the circuit resulting from accidental and undesired accidental switching of the counter which divides between two 415A, by means of an electronic interlock. The operation of the second and third cycles of the horizontal oscillator and the scanning amplifier of Figure 1 is as follows. A horizontal synchronization signal 5, illustrated as an example positive pulse, is selected by the switch 15, from either the secured phase cycle 10 or the synchronization signals derived from a plurality of input visual display signals. The synchronization signal 5 is applied to a phase detector 50, where it is compared to a horizontal index signal 401 produced by the division of the secured line clock signal LLC, 301, from the controlled voltage oscillator, VCO 300 Block 400 represents an example deviation processing integrated circuit, IC 400, for example, of type TDA9151. The integrated circuit 400 is controlled with a busbar, for example, by the busbar I2C 420, and also includes a phase detector PLL3, and the dividers 415 and 415A. The divider 415A is controlled by the signal 402, to provide the division ratios of 432 and 864, respectively, and thus produces the horizontal index signals in two frequency bands, nominally IFh and 2Fh. The control signal 402 is coupled to the switch 412, which inserts or drifts the divider 415A, to provide two division ratios. Therefore, the controlled voltage oscillator, VCO 300, operates in a single frequency band of approximately 13.6 MHz, but is synchronized with horizontal frequencies that differ by more than 2: 1. Examples of these horizontal non-integer frequencies are the NTSC signals, where the horizontal frequency, represented by lFh, is 15,734 kHz, and an ATSC 10801 signal with a horizontal frequency, represented in relation to the NTSC signal as 2.14Fh , or 33,670 kHz. During the visual display of the NTSC derived images, the switch 412 selects the divider 415A, which provides a division ratio of 864: 1, producing a frequency nominally as the horizontal frequency of NTSC of lFh. In a similar manner, for the visual display of the images with horizontal frequencies of 2Fh or greater, for example, an ATSC signal 10801, the switch 412 derives the divider 415A, resulting in a division ratio of 432, which produces a frequency horizontal 2Fh, 31,468 kHz, twice that of the NTSC standard. However, the horizontal frequency of ATSC 10801 is not an integer multiple of the NTSC signal lFh, and is actually 2.14 times the frequency of NTSC. Accordingly, to achieve synchronization with an input signal 10801, or any synchronization index other than 2Fh, it is required to change the frequency of the controlled voltage oscillator to a frequency which, when divided by 432, produces a frequency that is can synchronize with that of ATSC 10801, or the selected horizontal index of the input signal. The divided secured line clock signal 401 is also coupled to synchronize the third cycle 410 by means of the phase detector PLL3, which compares the clock signal 401 with an impulse derived from the scanning current Hrt, 501. A output signal 403 from the PLL3 by means of a stage of the impeller 450 to a horizontal scanning stage 500, which generates a current related to the scan, for example, in a visual display device, or in a beam deflection coil of electrons In addition to the coupling with the PLL3, the scanning pulse Hrt is also coupled to the protection circuit 600 and the X-ray protection circuit 690. In Figure 4 a protection circuit 600 is shown, which provides different functions protective devices related to the presence or absence of the scanning current, as indicated by the detection of the Hrt pulse, 501. The circuit block 610 detects the presence or absence of the impulse 501, and generates an active low interruption, SCAN -LOSS INTR. 615 (EXPLORING LOSS INTERRUPTION), which is coupled with a microcontroller, μ CONT. 800. A second protective function provided by the 600 circuit, is to inhibit the selection of the horizontal frequency during the presence of the pulse 501, that is, during the scan. The horizontal frequency selection data is coupled from the microcontroller 800 via the busbar 420. The control data from the busbar is demultiplexed, and the frequency selection data is converted from digital to analog by the digital converter to 700 analog, to form the switching signal 1H_SW, to be coupled to the circuit block 650. The circuit of the block 650 allows the logic state of the signal 1H_SW to be coupled for the frequency selection only if the scanning amplifier 500 is not generating impulses Hrt. Consequently, any change in the horizontal frequency is inhibited or interassured until "the impulses related to the exploration cease. In block 610 of Figure 4, the pulses derived from the Hrt scan are rectified by the diode DI and the charging capacitor Cl positively by means of a resistor R2 to the positive supply. The junction of the resistor R2 and the capacitor Cl joins the base of a PNP transistor Ql, with the result that the positive charge developed through the capacitor Cl turns off the transistor when the pulses related to the deviation are present. The emitter of the transistor Ql is coupled with a positive voltage supply by means of a diode D2, which prevents the breaking of the base emitter zener, and ensures that the transistor Ql turns off when the charge derived from the pulse through the capacitor Cl is of approximately 1.4 volts or less. The collector of transistor Ql is coupled to ground by resistors R3 and R4 connected in series. The junction of the resistors is coupled to the base of an NPN transistor Q2, which has the emitter to ground, and the collector coupled by means of a resistor R7, to form an open collector output signal. Accordingly, when the Hrt pulses are present, the transistor Ql turns off, which in turn turns off the transistor Q2, providing the output signal 615, the loss of scanning interruption, and the open circuit. When the impulses related to the exploration are absent, for example, as a consequence of a control function derived from the bus, a circuit failure, or X-ray protection, the positive charge developed through the capacitor Cl is dissipated by means of the series combination of the resistors Rl and T2, thus allowing the capacitor Cl to charge towards the ground potential. When the potential through the capacitor Cl is nominally 1.4 volts, the transistor Ql is activated, the collector terminal assuming the nominal potential at the cathode of the diode D2. Therefore, this positive potential of approximately 7 volts in the collector of the transistor Ql, is applied by means of the potential splitter formed by the resistors R3 and R4, to the base of the transistor Q2, which is activated leading to the collector and the 615 output signal up to nominal ground potential. The signal 615 is an interruption signal which, when low, signals to the microcontroller 800 that the scanning current in the visual display or in the example coil is absent. The collector of the transistor Ql of FIG. 4 also couples with the circuit block 650, which conveniently allows or inhibits the horizontal frequency changes caused by the microcontroller, and communicates by means of the busbar 420 with a frequency converter. digital to analog DAC 700. The digital-to-analog converter 700 generates an analog control signal 1H_SW, which has two voltage values. When the control signal 1H_SW is nominally zero volts (Vcesat), the division between two stages of the processor 400 is derived, and the divider 415 divides the output signal of the controlled voltage oscillator LLC, 301, between 432, to produce a frequency in a higher band of horizontal frequencies equal to, or greater than 2Fh. When the control signal 1H_SW is approximately 9.6 volts, the division between two stages 415A, which produces a combined division of 864, is selected. Therefore, the line clock secured by the LLC 301 controlled voltage oscillator is divided into 864 to produce a nominal frequency of IFh. The collector of transistor Ql is coupled by means of the series-connected resistors R5 and R6, which form a potential divider to ground. The junction of the resistors R5 and R6 is coupled to the base of an NPN transistor Q3, which has an emitter to ground. The collector of transistor Q3 is connected to the positive supply by means of a load resistor R8, and also coupled to the base of an NPN transistor Q4 by means of a resistor RIO. The emitter of the transistor Q4 is coupled with the junction of a potential divider formed between the positive supply and the ground, where the resistor R9 is connected to the supply, and the resistor Rll is connected to ground. Accordingly, the emitter of transistor Q4 is biased at approximately 4 volts. From there, transistor Q4 is activated when the base voltage exceeds approximately 4.7 volts, causing the collector to assume the nominal emitting potential. The collector of the transistor Q4 is connected directly to the junction of the signal 1H_SW, and both the input of the TR trigger and the threshold input of the input TH of the integrated circuit 1, for example, the integrated circuit of type LMC 555. Accordingly, with both trigger and threshold inputs held at 4 volts, changes in the control signal 1H_SW resulting from the commands generated by the busbar or by the collection of the wrong signal are prevented from changing the output status of the integrated circuit. . The threshold input of the Ul circuit responds when the voltage value of the control signal 1H_SW exceeds approximately 5.3 volts, and results in the selection of the scanning frequency lFh. The trigger input of the integrated circuit Ul responds to a negative transition of the control signal 1H_SW, when the voltage value is less than about 2.6 volts, which results in the selection of the scanning frequency 2Fh. The operation of the circuit 650 is as follows. The presence of the pulses Hrt coupled with the circuit 610 deactivates the transistor Ql, the collector taking on a nominal potential of earth by means of the parallel combination of the resistors connected in series R3 and R4, and the resistors connected in series R5 and R6. Consequently, transistor Q3 is also deactivated, the collector taking on the nominal supply voltage by means of resistor R8. This positive potential is applied to the base of transistor Q4, which activates the connection of the junction of the control signal 1H_SW and the integrated circuit Ul with a potential of approximately +4 volts. Applying +4 volts to both trigger and threshold inputs of the integrated circuit Ul, prevents "the Ul from responding to changes in the control signal 1H_SW. Accordingly, the current state of the selected horizontal frequency control signal 202/402 is maintained, and can not be changed while the scanning pulses Hrt are present. Accordingly, any horizontal frequency change is prevented, and the failure of the horizontal scanning stage 500 is prevented. In the absence of the scanning pulses, the transistor Ql is activated, and the collector assumes the nominal supply potential. This positive potential is coupled by means of the series resistors R5 and R6, and activates the transistor Q3, which in turn turns off the transistor Q4. With the transistor Q4 deactivated, the inhibition of the integrated circuit Ul is removed, and therefore, for the operation of IFh, the signal 1H_SW assumes a high voltage value, and the output SEL. H. FREQ. of the integrated circuit Ul assumes a low voltage value. In a similar way, when the 2Fh operation is selected, the control signal 1H_SW assumes a low voltage, assuming the output SEL. H. FREQ. of the Ul a high voltage value. Convenient control of the integrated circuit Ul by means of the presence or absence of the Hrt pulse, is also used in the circuit block 655 of Figures 1 and 4. In Figure 4, a power supply switching command is coupled. 2H_VCC, from the digital-to-analog converter 700, with the resistors connected in series R13 and R14, which form a ground potential divider. The junction of the resistors is connected to the base of a transistor Q5, which has the emitter earthed, and the collector connected as an open collector output to generate the power supply control signal SEL. 1H_VCC, 6156. The base of a transistor Q5 is also connected to a discharge output of the integrated circuit Ul. The operation of the circuit block 655 is as follows. A power supply switching command is generated by the microcontroller 800, and is transmitted via the busbar 420 to the digital-to-analog converter 700, for the demultiplexing and the generation of the control signal 2H-VCC, 702. When the control signal 702 is high, for example, of approximately +9.6 volts, transistor Q5 is activated, and collector and output control signal SEL. 1H__VCC, 656, assume a potential of nominally zero volts (Vcesat) of transistor Q5. However, the operation of the transistor Q5 is controlled by the discharge output circuit of the integrated circuit Ul, which prevents the transistor Q5 from inverting the power supply control signal 2H_VCC, holding the base to the nominal earth potential, Vcesat, of the integrated circuit discharge transistor Ul. Accordingly, the power supply switching, and the SEL signal is prevented. 1H_VCC, 656 remains high, sustaining a power supply condition of lFh, for example, a lower operating voltage. The discharge circuit of the integrated circuit Ul becomes inactive when the output circuit of the Ul changes state, that is, the output signal SEL H. Freq. it is lowered in response to the selection of an operating mode of 2Fh. Therefore, selecting the power supply for 2Fh and higher horizontal frequencies requires that a 2Fh scan frequency is initially selected, while the scan is inactive. As described, the operating frequency of the second and third phase locked cycles can be changed in the ratio of 2: 1 by means of the switching divider 415A. However, to achieve synchronization of the controlled voltage oscillator at frequencies other than harmonically related frequencies, for example, with an ATSC 10801 frequency of 2.14Fh, or an SVGA signal with a horizontal frequency of 2.4Fh, the oscillator is required. The controlled voltage of the second assured phase cycle is controlled to achieve a nominal horizontal frequency of between 2.14 and 2.4 times that of a horizontal frequency of NTSC. In the controlled voltage oscillator 300, a convenient frequency that establishes the direct current potential, FREQ. SET, 302, determines a frequency of the oscillator that, when divided, generates a nominal horizontal frequency. The frequency that establishes the direct current potential is generated by a digital-to-analog converter, and is applied to a variable voltage capacitor or a varicap diode, which is part of the network that determines the frequency of the oscillator. The oscillator is synchronized with the input synchronization signal by means of an error signal from the phase detector, which is filtered and applied to an inductor, which is part of the network that determines the frequency of the controlled voltage oscillator 300 In simple terms, a direct current is applied that establishes the frequency at the end of the varicap diode of the network tuned in series, with the phase error signal applied at the end of the inductor. Thus, the frequency and phase control signals are applied through the tuned circuit that determines the frequency. The controlled voltage oscillator 300 is illustrated in Figure 1, and is shown in a schematic form in Figure 3. The operation of the suitably controlled oscillator 300 is as follows. The microcontroller 800 and a memory (not shown), the access and output frequency setting data by means of the data bus 420, for example, and the bus bar IC, as illustrated in Figure 1. I2C busbar is connected with a digital synchronization processor 400, to provide different control functions, and with a digital-to-analog converter 700, which separates and converts the data into analog voltages. The digital-to-analog converter 700 generates the frequency switching control signal 1H_SW, 701, and the frequency setting voltage of the controlled voltage oscillator 302. In Figure 3, the frequency setting voltage FREQ. SET 302 is coupled by means of a resistor Rl with the junction of resistors R3, R4 and a capacitor C3, which in conjunction with resistor Rl, forms a low-pass filter to ground. The resistors Rl and R3 form a potential divider for the frequency setting voltage, with the resistor R3 connected to the reference voltage of the digital-to-analog converter 700 (Vref). Accordingly, the analog voltage 302 is nominally halved, and is referenced with the reference voltage of the digital-to-analog converter (Vref), by applying a nominal voltage of about +3.8 volts of polarizing potential to the varicap diode DI. The junction of the resistors Rl, R3 and the capacitor C3 is coupled to the cathode of the varicap diode DI by means of a resistor R4. Therefore, the value of the nominal direct current voltage, derived from the voltage (Vref), plus a frequency setting voltage determined by the data 302, from the analog-to-digital converter 700, are applied to the varicap diode DI of the network that determines the frequency of the oscillator. The frequency setting voltage 302 is nominally zero volts in the modes lFh and 2Fh, and rises to approximately +7 volts when the operation is selected in 2.4Fh, for example, SVGA. The controlled voltage oscillator 300 is formed by the PNP transistor Q3, which has the emitter connected to a positive supply by means of a resistor R7, and the collector connected to earth by means of a parallel combination of a resistor R8 and a capacitor C4 . The base of transistor Q3 is connected to the positive supply by means of a resistor R6, and is coupled to ground by means of a capacitor C5. The frequency of the oscillator is largely determined by a series resonant network formed by an adjustable inductor Ll, and a parallel combination of diode varicap DI and capacitor C4. The junction of the resistor R4, the cathode of the diode DI and the capacitor C4 is coupled to the base of the transistor Q3 via the capacitor C6. The collector of transistor Q3 is connected via capacitor C8 to the junction of inductor Ll and a resistor, illustrated in FIG. 2 as R6, the processed phase error signal 201 is supplied for synchronization of the oscillator. Accordingly, the frequency control and phase synchronization signals are applied through the series resonant network formed by the elements DI, C4, Ll.

The initial tuning of the oscillator can be achieved by setting the voltage of the digital-to-analog converter 302 to nominally zero volts, and with a horizontal synchronization signal NTSC, IFh, coupled to the phase detector 50, the inductor Ll is adjusted to center the signal Error of the phase detector within its operating range. In an alternative oscillator setting method, a non-adjustable inductor Ll is used. An IFh horizontal frequency synchronization signal is applied to the phase detector 50, and the voltage of the digital-to-analog converter 302 is varied, by means of the microcontroller, by means of the busbar, until the error signal of the sensor is centered. phase detector. The data value corresponding to this centering value of the voltage 302 is then stored. To determine the frequency setting voltage for the operation at an example speed of 2.4Fh, the method immediately above is repeated, storing the data value that it focused on. the cycle. The output signal of the oscillator is extracted from the emitter of the transistor Q3 in the resistor R7, and coupled with the emitter of the PNP transistor Q4 by means of a coupling capacitor C6. Transistor Q4 is configured as a base amplifier to ground, with the base uncoupled to ground via a C7 capacitor, and connected to a positive supply by means of a resistor Rll. The collector of transistor Q4 is connected to ground via the RIO resistor. Accordingly, the oscillator output signal is developed through the RIO resistor, and coupled with the synchronization processing integrated circuit 400 as an insured line clock, LLC 301. The selection among the plurality of horizontal frequencies is initiated by means of a control command coupled from the microcontroller 800 by means of the busbar 420, and is directed to the synchronization processing integrated circuit 400. The control command, LFSS, initiates or stops the horizontal and frame generation inside the circuit integrated 400, so that the horizontal pulse output signal 403 can be terminated, as illustrated by the output switch 412a. Accordingly, in the absence of the horizontal pulse signal 403, the horizontal scanning amplifier 500 stops generating current flow, and consequently the impulse Hrt is no longer produced. Following the horizontal deactivation command, the microcontroller transmits control words addressed to the digital-to-analog converter DAC 700. A first control word addressed to the digital-to-analog converter 700 may represent a horizontal frequency commutation command, which occurs from the digital-to-analog converter 700 as the analog control signal 1H_SW, 701, and is coupled as described, with the switching interlock 650. The digital-to-analog converter can also receive a second control word, which, as described, it generates an FREQ analog frequency setting potential. SET 302. Having deactivated the horizontal pulse 403, and thus the generation of the impulse Hrt ended, the control signal 1H_SW is allowed to change the state of the integrated circuit Ul. With the inhibition removed from the integrated circuit Ul, the output signal SEL. H. FREQ. 402 can change the state, selected in this way a different ratio of the divisor, and therefore, a different horizontal frequency, for the assured phase cycles. From there, the signal 402 is applied to the synchronization processor 400, causing the divider 415A to be inserted or derived from the divider chain, without causing damage to the horizontal driver 450 or the horizontal scanning amplifier 500. The microcontroller transmits the command of horizontal deactivation before transmitting the horizontal frequency switching command, in order to ensure that the horizontal scanning amplifier 500 is passive and in this way damage to the circuit is avoided. Nevertheless, the protection circuit 600 provides an additional level of protection, ensuring that the selection of the horizontal frequency by the signal 402 can only occur in the absence of horizontal scanning pulses Hrt. Accordingly, the synchronization processor 400 and the scanning amplifier 500 are protected against changes in the divider of the controlled voltage oscillator resulting from the noisy signals generated, for example, by the analog-to-digital converter 700, or resulting from wandering functions of the circuit, charge of power supply, or arc formation of the cathode ray tube. The output signal from the integrated circuit Ul, SEL. H. FREQ., 202, is also coupled with the active low pass filter of the invention 200, which is shown in Figure 2, and operates as follows. A phase error signal F ERROR, 11, which results from the phase comparison between the signal 401, the divided controlled voltage oscillator, and the synchronizer of the input signal 5, is coupled with the input resistor R1. The input resistor R1 is connected in series with the resistor R2 to a reversing input of an integrated circuit amplifier 210. The connection of the resistors R1 and R2 is connected to a fixed contact IFh of the SI switch. The moving contact of the SI switch is connected to the junction of a parallel combination of the resistor R3 and the capacitor C3, and a parallel combination of the resistor R4 and the capacitor C4. Negative feedback is applied from the output of the amplifier 210 to the reversing input by means of a frequency-dependent network formed by the capacitor C2 and the series-connected combination of the parallel networks of the resistor R4 and the capacitor C4 and the resistor R3 and the capacitor C3. The parallel network R3, C3 is connected between the switch of the switch SI and the inverting input of the amplifier 210. When the switch SI selects the position lFh, the resistor R2 is connected in parallel with the parallel combination of the resistor R3 and the capacitor C3 , with the result that the newly formed parallel network, R2, R3, C3 has little effect in determining the gain of the amplifier or the frequency response. Accordingly, when synchronized in lFh, with the position of the selected lFh switch, the gain of the amplifier is established by the input resistor Rl, with the frequency response determined by the capacitor C2 and the parallel network R3, C3. When the visual display is operating at a horizontal frequency greater than IFh, the SI switch selects the 2Fh position, and the resistor R2 becomes the predominant gain determining component, with the frequency response controlled by the capacitor series combination C2 and the parallel networks R3, C3 and R4, C4. The non-inverting input of the amplifier 210 is biased to a positive potential of approximately 2.5 volts. The output from the amplifier 210 is coupled by means of the series connected resistors R5 and R6, to form a processed phase error signal, PROC. F ERROR, 201, to be coupled in order to synchronize the controlled voltage oscillator 300. The junction of resistors R5 and R6 is uncoupled to ground via a Cl capacitor, which forms a low pass filter to prevent high noise. frequency generated, for example, by the operation of the power supply in switched mode from the phase modulation of the noise-controlled controlled voltage oscillator. The junction of the resistors R5 and R6 is connected to a peak-to-peak limiter or clip formed by the emitters of the PNP transistor Ql and the NPN transistor Q2. The collector of transistor Ql is connected to ground with the collector of transistor Q2 connected to a positive supply by means of a resistor R9. The base of transistor Q2 is connected to the union of the RIO and R7 series connected resistors. The RIO resistor is connected to ground, and the resistor R7 is connected in series with an additional positive supply by means of a resistor R8. The junction resistors R7 and R8 are connected to the base of the transistor Ql. Accordingly, resistors R7, R8 and RIO form a potential divider which determines the peak-to-peak clamping values of approximately +0.3 volts and +2.2 volts, where the processed error signal 201 is limited. In a phase cycle assured, the selection of the output leakage of the phase detector, as described, is a compromise between the stability of the static or insured phase, and the dynamic or insured operation inside. For example, synchronization with a computer-generated SVGA signal may require, or may benefit from, a narrowband amplitude controlled voltage controlled oscillator control signal, which will provide a stable oscillator highly in phase and horizontal frequency. However, as described above, the reproduction timing signals of video cartridge recorders may include abrupt horizontal synchronization phase changes in the vicinity of the vertical synchronizer and the vertical blanking intervals. To prevent or mitigate the effect of that phase change, the cycle is required to have a bandwidth wider than that required for computer-generated SVGA signals or transmission signals that are not subject to abrupt phase alterations. The suitable amplifier 210 is configured as an active low-pass filter, wherein the components of the output signal are fed back to the reversing input by means of the network connected in series dependent on the frequency C2, C3, C4 and R3, R4 Conveniently, the SI switch is controlled in response to a selected frequency of the horizontal oscillator, such that, in the position of the switch lFh, the resistor R2 is connected in parallel with the parallel combination R3, C3 to form an impedance in series with the investment input. This parallel combination of resistors R2, R3 and C3, has little effect on filter gain or frequency response. In the position of the switch lFh, the gain of the filter is determined by the impedance of the network C2, Cl and R4, divided by the value of the input resistor R1. Clearly, as the operating frequency of the cycle approaches direct current, the impedance of the capacitor C2 becomes large, and the cycle gain approaches an upper limit condition, as illustrated in FIG. 5A. When operating on a frequency different from the horizontal lFh, the SI switch is controlled to select the 2Fh position. At the position of the switch 2Fh, the gain of the filter is determined by the impedance of the feedback network R3, C2, Cl and R4, divided by the series combination of resistors R1 and R2. Since the resistor R2 is significantly larger than the resistor R3, the gain in the 2Fh is reduced relative to that of the switch position lFh. Accordingly, the gain of the active filter and the bandwidth are controlled to be different in the response to a selection of the horizontal operating frequency. During operation at a horizontal frequency of 2Fh or higher, the SI switch selects the 2Fh position, with the result that the gain at frequencies close to direct current is approximately 10 dB, as illustrated by the dotted line in the amplitude versus frequency graph of Figure 5A. Then the gain drops to zero at about 10 Hz, and continues to fall, reaching -20 dB at approximately 100 Hz. Accordingly, when operating in a 2Fh mode with the SI switch in the 2Fh position, the zero gain bandwidth is about 10 Hz. Figure 5B shows phase versus frequency graphs for the two horizontal frequencies, with the 2Fh mode indicated by a dotted line. When operating in an NTSC frequency of lFh, the SI switch is controlled to select the position lFh, which increases the filter gain, and provides a zero gain bandwidth in excess of 10 kHz. The reference to Figure 5A illustrates that a higher gain of the low frequency filter is used during IFh operation than that used during operation at higher horizontal frequencies. In addition, the filter produces a significantly wider phase error signal bandwidth than that obtained in 2Fh mode. The active filter gain and frequency response switching are conveniently achieved with a single switch contact, which provides savings in printed circuit board area, which consequently reduces the susceptibility to parasitic field pickup and phase instability noisy The gain and bandwidth switching of the invention in an active low pass filter of an assured phase cycle, facilitates the rapid response to abrupt changes of horizontal phase at a horizontal frequency, while "providing better phase stability". and freedom of jumping to a second horizontal frequency.

Claims (20)

1. A horizontal frequency signal generator that can operate selectively in a plurality of frequencies, this generator being characterized by: an oscillator (300) controlled for synchronized oscillation in a plurality of horizontal frequencies; a source (SW15) of synchronization pulses (5); a phase detector (50) having inputs coupled to the oscillator (300) and to the source (SW15), and generating an output signal (11) representing a phase difference between the inputs; a processor (200) coupled with the phase detector (50) to process the output signal (11), and generate a control signal (201) to control the oscillator (300), the processor gain being controlled in response to the selected frequencies of the plurality of frequencies.

2. The horizontal frequency signal generator of claim 1, characterized in that the gain is increased during the operation of the oscillator (300) at a lower frequency of the plurality of frequencies.

3. The horizontal frequency signal generator of claim 1, characterized in that the processor (200) has a low pass filter characteristic.

The horizontal frequency signal generator of claim 3, characterized in that the bandwidth of the low pass filter is controlled in response to the selected frequencies of the plurality of frequencies.

5. The horizontal frequency signal generator of claim 1, characterized by the oscillator (300) being selectively operable in first and second frequencies, wherein the second frequency is substantially twice the first frequency.

6. The horizontal frequency signal generator of claim 1, characterized in that the oscillator (300) can be selectively operated in integer multiples of the first frequency.

The horizontal frequency signal generator of claim 1, characterized in that processor (200) is an active low pass filter.

8. The horizontal frequency signal generator of claim 7, characterized in that the gain of the active low pass filter is controlled by a contact pair (SI).

9. The horizontal frequency signal generator of claim 7, characterized in that the bandwidth of the active low pass filter changes by an order of magnitude in response to the selected frequencies of the plurality of frequencies.

10. A synchronization circuit, characterized by: a controlled voltage oscillator (300) that generates a horizontal frequency signal (401) in a plurality of frequencies; a source (SW15) of horizontal synchronization pulses (5); an element (50) for synchronizing the controlled voltage oscillator (300) and the horizontal synchronization pulses (5); and, an active low pass filter (200) coupled with the synchronization element (50) for filtering a voltage (11) from the synchronization element (50) to be coupled in order to synchronize the controlled voltage oscillator (300). ); wherein the bandwidth of the active filter is changed in response to the operation at one of the plurality of frequencies.

11. The synchronization circuit of claim 10, characterized in that the gain of the active low pass filter is changed in response to a converted digital-to-analog signal (701).

The synchronization circuit of claim 10, characterized in that the active low pass filter (200) is controlled in response to a data bus signal.

13. The synchronization circuit of claim 10, characterized by increasing a voltage gain of the active low pass filter (200) during operation at a lower frequency of the plurality of frequencies.

14. A video display that can operate in a plurality of horizontal frequencies, characterized by: a controlled voltage oscillator (300) that can operate in a plurality of frequencies; a source of synchronization pulses (SW15); a phase detector (50) coupled with the oscillator (300) and the source (SW15), to generate an output signal (11) which represents a phase difference between the inputs; and an active filter (200) coupled with the output signal (11), to filter the output signal (11), and generate a voltage (201) to control the oscillator (300), wherein the active filter (200) ) is controlled up to a first gain value at a first frequency of the plurality of frequencies, and the active filter (200) is controlled up to a second gain value at a second frequency of the plurality of frequencies.

15. The video display of claim 14, characterized in that the active filter (200) having selectable gain values has a low pass frequency characteristic.

16. The video display of claim 14, characterized in that the first frequency of the plurality of frequencies represents a lower frequency of the plurality of frequencies.

17. The video display of claim 14, characterized in that the gain of the active filter is increased when the oscillator (300) operates on the first frequency of the plurality of frequencies.

18. The video display of claim 14, characterized in that the gain of the active filter decreases when the oscillator operates on the second frequency of the plurality of frequencies.

19. The video display of claim 18, characterized in that the second frequency of the plurality of frequencies is nominally twice the first frequency.

20. The video display of claim 18, characterized in that the second frequency of the plurality of frequencies is greater than twice the first frequency.