MXPA99003984A - Composite memory material comprising a mixture of phase-change memory material and dielectric material - Google Patents

Abstract

A composite memory material (36) comprising a mixture of active phase-change memory material and inactive dielectric material. The phase-change material includes one or more elements selected from the group consisting of Te, Se, Ge, Sb, Bi, Pb, Sn, As, S, Si, P, O and mixtures of alloys thereof. A single cell memory element (30) comprising the aforementioned composite memory material (36), and a pair of spacedly disposed contacts (6, 8).

Description

COMPOSITE MEMORY MATERIAL COMPRISING A MIXTURE OF PHASE CHANGE MEMORY AND DIELECTRIC MATERIAL DESCRIPTION OF THE INVENTION The present invention relates generally to electrically operated memory material. More specifically, the invention relates to composite memory material comprising a mixture of phase change memory material and inactive dielectric material. The Ovonic EEPROM is an electronic memory device, novel, patented, high performance, non-volatile thin film. Its advantages include non-volatile data storage, potential for high bit density, and, consequently, low cost due to its simple two-terminal fingerprint device configuration, large reprogramming cycle life, low programming power and high speed . The Ovonic EEPROM is capable of both analog and digital forms of information storage. Digital storage can be either binary (one bit per memory cell) or multi state (multiple bits per cell). Only minor modifications are necessary to compute between two digital modes. For purposes of the present invention, the terms "memory elements" and "control elements" will be used synonymously. EARLY PHASE CHANGE MEMORY The general concept of using phase change materials that are written and erased in an electrical form (ie, materials which can be switched electronically between generally amorphous and generally crystalline states) for electronic memory applications is well known in the art, as described, for example, in U.S. Patent No. 3,271,591, assigned to Ovshingsky, filed on September 6, 1966, and U.S. Patent No. 3,530,441, assigned to Ovshinsky, filed on October 6, 1966. September 22, 1970 and both descriptions that are incorporated herein by reference (hereinafter "Ovshinsky patents"). As described in the Ovshinsky patents, such phase change materials are electrically switched between generally amorphous and generally crystalline local order structural states between different local detectable states between the full spectrum between completely amorphous and fully crystalline states. That is, Ovshinsky's patents describe that electrical switching of such materials is not required to take place between fully amorphous and fully crystalline states but can be incremental stages reflecting changes of local order to provide a "gray scale" represented by a multiplicity of conditions of local order that extend the spectrum between completely amorphous and completely crystalline states. The first materials described by the Ovshinsky patents may also, if required, be switched between just the two generally amorphous and generally crystalline structural order states to accommodate the storage and retrieval of individual bits of coded binary information. The electrically erasable phase change memories described in the Ovshinsky patents, as well as subsequent electric solid state memory, have a number of limitations that prevent their worldwide use as a direct and universal replacement for current computer memory applications, such as such as cassettes, floppy disks, magnetic or optical hard disk drive, solid state disk drive, DRAM, SRAM, and plug pulse memory. Specifically, the following represents the most significant of these limitations: (i) a relatively low electrical switching speed (by current standards), particularly when switching in the higher local order direction (in the increased crystallization direction); (ii) a relatively high input energy requirement necessary to initiate a detectable change in the local order; and (iii) a relatively high cost per megabit of stored information (particularly in comparison to current hard drive drive means).

The most significant of these limitations is the relatively high input energy required to obtain detectable changes in the electronic and / or chemical bond configurations of the chalcogenide material in order to initiate a detectable change in the local order. Also significant are the switching times of the electrical memory materials described in the Ovshinsky patents. These materials typically require times in the range of a few milliseconds for the set time (the time required to switch the material from the amorphous to the crystalline state); and about one microsecond for the re-time (the time required to switch the material from the crystalline state back to the amorphous state). The electrical energy required to commute these materials typically measured in the range of about one microjoule. It should be noted that this amount of energy must be supplied to each of the memory elements in the solid state array of lines and columns of memory cells. Such high energy levels are translated into requirements that carry high current for the address lines and for the cell / address device isolation associated with each discrete memory element. Taking into consideration these energy requirements, the choices of memory cell isolation elements by a person skilled in the art can be limited to very large simple crystal or transistor diode isolation devices, which can make use of lithography of scale in microns and therefore impossible a high packing density of memory elements. In this way, low bit densities of matrix arrays made of this material can result in a high cost per megabit of stored information. By effectively decreasing the distinction in price and performance between non-volatile mass memory, file, and volatile, fast system memory, the memory elements of the present invention have the ability to allow the creation of a novel "universal memory system". , not hierarchical. Essentially all the memory in the system can be inexpensive, file and fast. Compared with the original phase-shifting electrical memories of the Ovshinsky type, the memory materials described herein provide more than six orders of programming time faster in magnitude (less than 30 nanoseconds), and use extremely low programming power ( less than 0.1 to 2 nanojoules) with demonstrated long-term stability and cycle (in excess of 10 trillion cycles). Also, experimental results indicate that additional reductions in element size can increase switching speeds and cycle life. In general, the development and optimization of the case of chalcogenide memory materials has not proceeded in the same proportion as other types of solid state electrical memories which now have substantially faster switching times and substantially lower setting and resetting energies. These other forms of memories typically employ one or two solid state microelectronic circuit elements per memory bit (as many as three or four transistors per bit) in some memory applications. The primary "non-volatile" memory elements in such solid-state memories, such as EEPROM, are typically floating-gate field-effect transistor devices which have limited reprogrammability and which maintain a load on the gate of a transistor of field effect to store each bit of memory. Since this load may be lost over time, the storage of information is not truly non-volatile as this is in the phase change means of the prior art where the information is stored through change in the actual atomic configuration or electronic structure of the chalcogenide material from which the elements are manufactured. These other forms of memories now enjoy acceptance in the market. In contrast to DRAM and SRAM, volatile memory devices, and other "pulse" devices such as floating gate structures, field effect transistor devices are required in the electrical memory devices of the present invention. In fact, the electrically erasable memory elements, with direct overwriting capability, of the present invention represent the simplest electrical memory device, comprising only two electrical contacts for a monolithic body of thin film chalcogenide material and a diode semiconductor for insulation. As a result, a very small "on-chip" current state is required to store a bit of information, so inherently high-density memory chips are provided. Additionally, additional increases in information density can be made through the use of multibit storage in each discrete memory cell. In order to drive the impulse EEPROM market and be considered as a universal memory, the memory elements must be truly non-volatile. This is even more significant if the memory element is claimed to possess multibit storage capabilities. If a fixation resistance value is lost or even significant variation is found over time, the information stored in it is destroyed, users lose confidence in the memory file capabilities. In addition to the fixing resistance stability, another highly important factor which may be required of a universal memory is the low switching current. This is extremely significant when using EEPROM for large-scale file storage. Used in this way, EEPROMs can replace mechanical hard drives (such as hard magnetic or optical drives) of current computer systems. One of the main reasons for this reem lazamiento of conventional mechanical hard drives with the "hard drives" of EEPROM can be to reduce the comparatively large energy consumption of the mechanical systems. In the case of laptops, this is of particular interest since the mechanical hard disk drive is one of the largest energy consumers in them. Therefore, it may be especially advantageous to reduce this energy load, whereby the time of use of the computer by charging the power cells is substantially increased. However, if the replacement of EEPROM by hard mechanical drive has high requirements for high switching power (and therefore high energy requirements), the energy savings may be inconsistent or perhaps not substantial. Therefore, any EEPROM which is considered a universal memory requires low switching power. Still another requirement of a universal memory EEPROM is high thermal stability of the information stored in it. Today's computers, especially personal computers, are routinely subjected to high temperatures. These high temperatures can be caused by internally created heat such as from energy sources or other internal components that produce heat. These high temperatures can also be caused by environmental factors, such as using the computer in a hot climate or storing the computer in an environment which heats up dire or indire to more than normal temperatures. Whatever the cause of high temperatures, current computer memory systems, especially "hard" or archive memory, must be thermally stable even at relatively high temperatures. Without this thermal stability, data loss can occur leading to loss of data. loss of credibility mentioned above. Yet another requirement of a universal EEPROM memory is the long write / erase cycle life. For EEPROM, as in the case with all the archival memory, cycle life plays an important role in consumer confidence and acceptance. If the life cycle of a memory device is too short, the consumer will refuse to use this device for fear of losing valuable data. If the EEPROM is used as a replacement for main memory or computer display memory, that is, as a replacement for DRAM, SRAM or VRAM, the requirement for a long cycle life is even more critical. The main and display memory are a storage area for more frequent written / deleted data from the computer. Each time a new computer program is loaded, a portion of the main memory of the computer is erased and rewritten. During the execution of a computer program, a portion of the main memory of the computer is constantly being cycled. Each time the display of the computer monitor is changed, portions of the display memory are cycled. If EEPROMs are used to replace the main memory and display of the computer they do not have a relatively long write / erase cycle life, these computers may need to be replaced excessively. An object of the present invention is to provide a solid state memory material that has reduced switching current requirements and higher thermal stability of data stored therein. It is also an object of the present invention to provide a memory element comprising the aforementioned memory material. These and other objects of the present invention are made by a composite memory material comprising: a mixture of active phase change memory material and inactive dielectric material. The phase change memory material includes one or more elements selected from the group consisting of Te, Se, Ge, Sb, Bi, Pb, Sn, As, S, Si, P, O and mixtures or alloys thereof. These and other objects are also carried out by a single cell memory element comprising: a volume of memory material defining a memory element of a cell, the memory material comprising a mixture of phase change material active and inactive dielectric material; and a pair of contacts arranged separately, the contacts providing terminals for read information stored in and written information to the memory element. These and other objects are also realized by a memory element of a cell, electrically operated, directly written, multibitios comprising: a volume of memory material that defines a memory element of a cell, the memory material that constitutes means for assuming a large dynamic range of electrical resistance values with the ability to be set directly to a plurality of resistance values within the dynamic range without the need to be set to a specific start or clear resistance value, regardless of the value of previous resistance of the material in the response to be signal of electrical input selected to provide thus the individual cell with multibitios storage capacities; and a pair of contacts arranged separately to supply the electrical input signal for fixing the memory material to a selected resistance value within the dynamic range, wherein at least one of the contacts arranged separately is a mixture of a first material of contact and a second contact material, wherein the first contact material includes carbon, and wherein the second contact material includes at least one transition metal element. Preferably, the second contact material includes one or more elements selected from the group consisting of Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, and mixtures or alloys thereof. More preferably, the second contact material includes Ti and. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross-sectional view of a single memory element representing the composite memory material and a pair of contacts; Figure 2 is a top view of a possible plane of multiple memory elements showing how the elements can be connected to a group of X-Y address lines. Figure 3 is a schematic diagram of the memory elements of Figure 1, which further shows how the isolation elements such as diodes are connected in series with the memory elements to electrically isolate each of the devices from the others; and Figure 4 is a schematic representation illustrating a single crystal semiconductor substrate with the integrated memory array of the present invention as depicted in Figure 1 placed in electrical communication with an integrated circuit chip in which the directors / actuators / decoders. Disclosed herein is a composite memory material comprising a mixture of phase change memory material and inactive dielectric material. The composite memory material of the present invention provides switching within a wide dynamic range of stable states with low energy inputs at fast speeds such that it can be used to manufacture improved electrical memory elements. The composite memory material is non-volatile and will maintain the integrity of the stored information (within a selected error margin) without the need for periodic renewal signals. The composite memory material can also be overwritten directly in such a way that discrete memory elements (fixed to a specified starting point) need not be deleted in order to change the information stored there. The low and fast power switching for any different resistance values can be attributed to the fact that commutation occurs without the need for coarse atomic shuffling of the phase change switching material. As stated, the composite memory material is a mixture of active phase change memory material and inactive dielectric material. The active phase change memory material of a plurality of constituent atomic elements is formed. The phase change memory material includes one or more elements selected from the group consisting of Te, Se, Ge, Sb, Bi, Pb, Sn, As, S, Si, P, O and mixtures or alloys thereof. The phase change memory material preferably includes at least one chalcogen element and can include at least one transition metal element. Preferably, the chalcogen element is selected from the group consisting of TE, Se, and mixtures or alloys thereof. More preferably, the chalcogen element is a mixture of Te and Se. The term "transition metal" as used herein includes elements 21 to 30, 39 to 48, 57 to 72 and 80. Preferably, the transition metal element is selected from the group consisting of Cr, Fe, Ni, Nb, Pd, Pt and mixtures or alloys thereof. More preferably the transition metal is Ni. Specific examples of such multi-element systems are indicated hereinafter with respect to the Te: Ge: Sb system with or without Ni and / or Se.

Specifically, the tellurium alloys described herein have a valence band made of single-pair states. Since four p-layer electrons (4) are present in Te, and the TE atom is chemically bound by two of these binding electrons in the p-layer, the two external electrons (the single pair) are not used for the purposes of link and therefore do not substantially change the atomic energy of the system. In this regard, it is noted that the most fully filled molecular orbital is the orbital that contains the electron pair alone. This is significant since, in a perfect stoichiometric crystal of tellurium and germanium atoms, after the application of some internal chain in the network from which the crystallite is formed, the valence band can be extended and taken to the position of the existing Fermi level. However, TE Ge crystals are naturally "self-compressed", that is, the crystal preferably wants to build up a TE-rich composition (approximately 52 percent TE and 48 percent Ge). The stoichiometric crystal is a cube centered on the surface; however, with the addition of a minimum amount of energy, the crystal can assume a rhombohedral network structure increasing the number of its spaces Ge and / or Sb. It is this creation of spaces in the crystalline network structure, which can reduce the network chain in the TeGe alloys, responsible for reducing the energy state of the material and moving the Fermi level towards the valence band. It is acceptable, if not essential, to superimpose an amorphous model of the local order on top of a short-range local order model for the purpose of obtaining a descriptive explanation, if not perfectly predictive of atomic behavior. When considering the amorphous nature of the material, note that the density of the defect states in the tails of the band is greater adjacent to the edges of the band, while the depth of the recombination centers for captured charge carriers are more deep away from the edges of bands. The presence of these depth traps and tail states can provide a possible explanation for intermediate stable resistance values between the position of the Fermi level and the edge of the band. Regardless of the theory, when the fully crystalline semiconductor material of the invention is a degenerate semiconductor which exhibits metal-like conduction. It is further believed that the size of the crystallites that exist in the volume of the semiconductor and the memory material is relatively small, preferably less than about 200 A, more preferably between about 50 A and 500 A, and more preferably in the order of about 200 A to approximately 400 A. Additionally, it is believed that these crystallites are surrounded by an amorphous layer which can contribute to the rapid formation of the many positions of Fermi level of the material, detectable as different resistances (conductivities), as well as at lower power requirements for the transitions between these detectable resistance values which the material can be fixed confidently and repetitively. It has also been found that the modulation of the switching characteristics of two or three terminal semiconductor devices manufactured from the microcrystalline materials of the present invention can be controlled in such a way that repeatable and detectable resistance values can be effected. It has been found that, in order that the materials of the present invention are quickly fixed by low energy input signals at a desired conductivity (determined by the Fermi level position), it is only necessary that the materials are capable of have stable (or metastable long life) existence within at least two different Fermi level positions, in which the Fermi level positions are characterized by substantially constant band spaces but different electrical conductivities. As indicated above, it is also believed that the relatively small crystallite size can contribute to the rapid transition between detectable values of the resistance.

A feature of the semiconductor materials of the present invention is their tendency towards the formation of more crystallites and smaller per unit volume. It has been found that the sizes of the crystallites of the broader preferential range of the representative materials exemplifying the present invention are much less than about 2000 A, and generally less than the range of about 2,000 to 5,000 A which is characteristic of the materials of the prior art. The crystallite size of the present is defined as the diameter of the crystallites, or their "characteristic dimension". Which is equivalent to the diameter where the crystallites are not spherically shaped. It has been determined that the compositions in the highly resistive state of the class of TeGeSb materials which meet the criteria of the present invention are generally characterized by substantially reduced concentrations of Te relative to those present in the electronically erasable memory material of the art. previous. In a composition that provides improved electrical switching behavior characteristics, the average concentration of Te in deposited material is below 70%, typically below about 60% and in the range in general from as low as about 23% to about 58% of Te and more preferably about 48% to 58% of Te. The concentrations of Ge are above about 5% and in the range of as low as about 8% to about 30% on average in the material, which generally remains below 50%. More preferably, the concentrations of Ge are in the range of about 8% to about 40%. The rest of the main constituent elements in this composition is Sb. The given percentages are atomic percentages, which 100% total of the atoms are the constituent elements. In this way, this composition can be characterized as TeaGebSb? Oo- (a + b) • These ternary Te-Ge-Sb alloys are starting materials for the development of additional phase change memory materials that have even better electrical characteristics . The phase change memory material preferably includes at least one chalcogen and can include one or more transition metals. Phase change materials which include transition metals are elementally modified forms of the phase change materials in the Te-Ge-Sb ternary system. That is, the elementally modified phase change materials constitute modified forms of the Te-Ge-Sb phase change alloys. This elementary modification is achieved by the incorporation of transition metals in the basic Te-Ge-Sb ternary system, with or without an additional chalcogen element, such as Se. Generally the phase change materials elementally fall into two categories. The first category is a phase change memory material which includes Te, Ge, Sb and a transition metal, in the proportion (TeaGebSB10o- (a + b)) cTM100-c where the suffixes are in atomic percentages in the which 100% total are the constituent elements, where TM is one or more transition metals, a and b are as hereinafter indicated for the Te-Ge-Sb basic ternary system and c is between approximately 90% and approximately 99.99%. the transition metal preferably includes Cr, Fe, Ni, Nb, Pd, Pt and mixtures or alloys thereof. Specific examples of the phase change memory materials encompassed by this system may include (Te56Ge22Sb22) 95I5, (Te56Ge22Sb22) 90Ni? 0, (Te56Ge22Sb22) 95Cr5, (Te56Ge22Sb22) 9oCr? O, (e56Ge22Sb22) 95Fe5, (Te56Ge22Sb22) 9oFe10, (Te56Ge22Sb22) 95Pd5, (Te56Ge22Sb22) 90 days, (Te56Ge22Sb22) 95Pt5, (Te56Ge22Sb22) 9s? O, (Te56Ge22Sb22) 95Nb5, (Te56Ge22Sb22) 9oNb10, (Te56Ge22Sb22) 9oNi5Cr5, (Te56Ge22Sb22) 90NisFe5, (Te5SGe22Sb22) 9 ° Cr5Fe5, (Te56Ge22Sb22) 9 ° Pd5Cr5, (Te5eGe22Sb22) 9oNi5Pd5, (Te5eGe22Sb22) 9 = Pd5Pt5, etc. The second category is a phase change memory material which includes Te, Ge, Sb, Se and a transition metal, in proportion (TeaGebSb? 0o- (a + b)) cTMdSe? Oo- (c + d) ) / where the suffixes are in atomic percentages which 100% are the constituent elements, TM is one or more transition metals, a and b are as indicated below in the present for the Te-Ge ternary system. Sb, c is between approximately 90% and 99.5% and d is between approximately 0.01% and 10%. The transition metal may preferably include Cr, Fe, Pd, Pt, Nb and mixtures or alloys thereof. Specific examples of memory materials encompassed by this system may include (Te56Ge22Sb22) 9oNi5Se5, (Te56Ge22Sb22 soNixoSeio (Te5eGe22Sb22) 9th Cr5Se5 (Te56Ge22Sb22 8oCr10Se? Or (Te5SGe22Sb22) 9oFe5Se5 (Te56Ge22Sb22 soFeíoSeio (Te56Ge22Sb22) 9.Pd5Se5 (Te56Ge22Sb22 8oPd10Se? Or (Te5eGe22Sb22) 9th Pt5Se5 (Te56Ge22Sb22 soPtioSeio, (Te5SGe22Sb22) 9oNb5Se5 (Te5SGe22Sb22 80Nb10Se? or (Te5SGe22Sb22) 85Ni5Cr5Se5 (Te56Ge22Sb22 soNisFesSexo (Te5sGe22Sb22) 85Cr5Fe5Se5 (Te56Ge22Sb22 85Ni5Pd5Se5 (Te56Ge22Sb22) 8oNis t5Se10 (Te5eGe22Sb22 85Ni5Nb5Se5 (Te56Ge22Sb22) 85Pd5Cr5Se5 (Te56Ge22Sb22 80Pd5Pt5Se10 (Te5eGe22Sb22 ) 85Pd5Nb5Se5, (Te56Ge22Sb22 8SPt5Nb5Se5, etc.) The phase change memory material possesses substantially non-volatile fixed resistance values, however, if the resistance value of the phase change material does not vary from its original fixed value, it can be used "compositional modification", described later herein, to compensate for its displacement As used herein, the term "non-volatile" refers to the condition with which The fixed resistance value remains substantially constant for periods of archival time. Of course, software (including the feedback system discussed later in this) may be employed to ensure that absolutely no "displacement" occurs outside of a selected margin of error. Since the displacement of the resistance value of the memory elements can, if left unimpeded, impede gray scale storage of information, it is desirable to minimize the displacement. "Compositional modification" is defined herein to include any means for compositionally modifying the phase change memory material to substantially produce stable values of strength, including the addition of band gap expansion elements to increase the inherent strength of the material. . An example of compositional modification is to include graduated compositional non-homogeneities with respect to thickness. For example, the volume of phase change memory material can be graduated from a first TE-Ge-Sb alloy to a second Te-Ge-Sb alloy of different composition. The compositional degree can take any form which reduces the displacement of fixed resistance value. For example, the compositional gradation need not be limited to a first or second alloy of the same alloy system. Also, the graduation can be done with more than two alloys. The graduation can be uniform and continuous or it can also be non-uniform or not continuous. A specific example of compositional graduation which results in reduced resistance value displacement includes a uniform and continuous graduation of Ge? 4Sb29Te57 on a surface at G22Sb2TeS6 on the opposite surface. Another way to employ compositional modification to reduce resistance displacement is by stratifying the volume of phase change memory material. That is, the volume of phase change memory material can be formed of a plurality of discrete, relatively thin layers of different composition. For example, the volume of phase change memory material may include one or more pairs of layers, each of which is formed of a different Te-Ge-Sb alloy. Again, as in the case with graduated compositions, any combination of layers which results in substantially reduced resistance value displacement may be employed. The layers may be of similar thickness or may be of different thickness. It can be used any number of layers and multiple layers of the same alloy can be present in the volume of memory material, either contiguous or remote from each other. Also, layers of any number of different alloy compositions can be used. A specific example of compositional stratification is a volume of memory material which includes pairs of alternating layers of Ge? 4Sb29Te57 and Ge22Sb22Te56. Still another form of compositional non-homogeneity to reduce resistance displacement is achieved by combining the compositional gradient and compositional stratification. More particularly, the compositional composition mentioned above can be combined with any of the compositional stratification described above to form a stable volume of memory material. Example volumes of the phase shift memory material that employ this combination are: a volume of phase change memory material which includes a discrete layer of Ge22Sb22Te5e followed by a graduated composition of Ge14Sb9TeS7 and Ge22Sb22Te56 and (2) a volume of phase change memory material which includes a discrete layer of Ge? 4Sb29Te57 and a graduated composition of Ge? 4Sb29Te57 and Ge22Sb22Te56. The composite memory material is a mixture of an active phase change memory material, such as those described above, and an inactive dielectric material. Generally, the dielectric material can be any dielectric material that is not chemically reactive with the phase change memory material. Preferably, the dielectric material has a melting point greater than that of the phase change memory material. In particular, the dielectric material can be one or more materials selected from the group consisting of oxides, nitrides, fluorides, sulfides, chlorides, carbides, oxynitrides, carboxy nitrides, borides, phosphides and mixtures or alloys thereof. Other dielectric materials known in the art may also be used. The dielectric material can also be chosen from the group of organic dielectric materials. These include, but are not limited to, materials such as amides, polyamides, imides, polyimides and parilenes. The oxides include silicon oxides such as Si02, titanium oxides such as Ti02, aluminum oxides such as Al203, zirconium oxides, such as Zr03, germanium oxides such as Ge02, and tantalum oxides such as Ta205. Other possible oxides include B203, Sb203, and PbO. The nitrides include silicon nitrides such as Si3N4, aluminum nitrides such as AlN, as well as TiN, SiN, ZrN, and BN and non-stoichiometric silicon nitride SiNx. The sulfides include silicon sulphide such as SiS2, germanium sulfide such as GeS2, and zinc sulfide such as ZnS. Fluorides include MgF2, CaF2 and LiF2. Several glasses can also be used. For example, LaSiON material containing La, Si, O and N; SiAlON material containing Si, Al, 0 and N; SiAlOn material containing yttrium; or NdSiOn material containing Nd, Si, O and N. can be used.

The composite memory material is preferably a heterogeneous mixture of active phase change memory material and inactive dielectric material. One embodiment of such a heterogeneous mixture is that of a multi-stratified structure with layers of ase change memory material intermixed with layers of dielectric material. Preferably, the thickness of each layer may be between about 5 A to about 75 A. More preferably, the thickness of each layer may be between about 10 A to about 50 A. More preferably, the layer thickness may be between about 20. A at about 30 A. The composite memory material can be made by methods such as flashing, evaporation or chemical vapor deposition (DVC), which can be improved by plasma techniques such as RF brightness discharge. The composite memory material of the present invention preferably makes by flashing RF or evaporation. This can be formed by multiple source flashing techniques making use of a plurality of objectives, usually an objective of the phase change memory material and a target of the dielectric material. With these objectives arranged in opposition to a substrate, the flashing is performed while the substrate is rotated in relation to each objective. A target containing both phase change materials and dielectrics can also be used. Also, substrate heating can be used to control the morphology of the phase change material within the composite memory material formed by affecting crystal growth as well as crystal aggregation via surface mobility. The percentage by volume of dielectric material within the composite memory material can be controlled. Preferably, the percentage by volume of dielectric material is between about 10% and about 90%. More preferably, the volume percentage of dielectric material is between about 20% and about 80% More preferably, the percentage by volume of electrical material is between about 405 and about 60%. The composite memory material can also be formed by a spin coating process. The phase memory material can be mixed with a dielectric such as an organic polymer such as polyamide. The resulting mixture can then be spin-coated on a silicon substrate that forms a commemorative memory material with the desired properties. Also described herein is a memory element of a cell comprising the composite memory material described above. The memory element further comprises a pair of contacts arranged separately to supply the electrical input signal to the composite memory material. Figure 1 shows a cross-sectional view of one embodiment of the memory element formed in a single crystal silicon semiconductor wafer 10. The memory element includes the composite memory material 36, a first contact 6 arranged separately, and a second contact 8 arranged separately. The first contact 6 and the second contact 8 can be comprised of two layers of thin film. The thin film layers 38 and 34 deposited adjacent to the composite memory material 36 have excellent diffusion barrier properties which exhibit diffusion and electromigration of foreign material in the composite memory material 36. The adjacent thin film layers 38, 34 may be comprised of a carbon material such as amorphous carbon. Alternatively, the thin film layers 38, 34 may be formed of a compound which includes an element selected from the group consisting of Ti, V, Cr, Zr, Nb, M, Hf, Ta,, and one or more selected elements. of the group consisting of B, C, N, Al, Si, P, S. Preferably, the adjacent thin film layers 38, 34 are formed of a compound which includes Ti and one or more elements selected from the group consisting of of C, N, Al, Si, and mixtures or alloys thereof. In one embodiment, the adjacent thin film layers are comprised of a compound having a composition of, in atomic percent, between about 10% to 60% titanium, 5% to 50% carbon, and 10% to 60% nitrogen . In addition, the titanium carbonitride can also include up to 40% hydrogen. In another embodiment, the adjacent thin film layers 38, 34 are comprised of titanium siliconitride. Preferably, in this embodiment, the adjacent thin film layers are comprised of a compound having a composition of, in atomic percent, between about 10% to 60% titanium, 5% to 50% silicon and 10% to 60%. % nitrogen In addition, the titanium siliconitride can also include up to 40% hydrogen. In a third embodiment, the adjacent thin film layers 38, 34 are comprised of aluminum and titanium nitride. Preferably, in this embodiment, the adjacent thin film layers are comprised of a compound having a composition, in atomic percent, between about 10% to 60% titanium, 5% to 50% aluminum and 10% to 60%. % nitrogen In addition, titanium aluminum nitride can also include up to 40% hydrogen. Titanium carbonitride, titanium siliconitride and titanium aluminum nitride have excellent barrier properties, preventing both diffusion and electromigration of foreign material in the composite memory material. Additionally, titanium carbonitride, titanium siliconitride and titanium aluminum nitride can be deposited by such methods as physical vapor deposition including evaporation, ion plating, as well as flashing DC and RF deposition, chemical vapor deposition, and deposition of chemical vapor assisted with plasma. The exact method used depends on many factors, one of which is deposition temperature constraint imposed by the composition of the target material. The pair of contacts 6 and 8 arranged separately are preferably comprised of the additional thin film layers 32 and 40 which are deposited away from the composite memory material 36. Each of these far thin film layers is comprised of one or more elements of the group consisting of Ti, W and Mo. In one embodiment, each of the far thin film layers is comprised of Ti and W. Preferably, the Distant thin film layers are comprised of a compound, in atomic percent, from 5% to 30% titanium and 70% to 95% tungsten. The Ti-32 and 40 alloy layers are preferably deposited using a DC flashing deposition process. They are preferably arranged at a thickness of about 100 A to 4000 A. They are more preferably deposited at a thickness of about 200 A to 2000 A. The Ti-W alloy layers 32 and 40 have excellent ohmic contact properties. On the other hand, has the necessary barrier properties to prevent both electromigration and diffusion of foreign electrode material in the composite memory material 36. The layer of composite memory material 36 is preferably deposited at a thickness of approximately 200.

A to 5,000 A, more preferably of approximately 250 A to 2,500 A, and more preferably from about 250 A to 500 A in thickness. The memory element shown in Figure 1 can be formed in a multi-stage process. Stages 32, 34 and 46 are first deposited and the insulation layer 46 is then compressed in such a way that there will be a contact area between the composite memory material 36 and the layer 34. The remaining layers 36, 38 and 40 are deposited and the entire stack of layers 32, 34, 36, 46, 38 and 40 is compressed to the selected dimension. A layer of insulation material 39 is deposited on the upper part of the overall structure. Examples of insulation materials Si02, Si3N4 and tellurium oxygen sulfide (for example TeOS) are examples. The layer of insulation material 39 is compressed and an aluminum layer is deposited to form the second electrode mesh structure 42 which extends perpendicular in the direction of the conductors 12 and complete to the XY mesh connection to the memory elements. individual Resting on the complete integrated structure is an upper encapsulating layer of a suitable encapsulant such as Si3N4 or a plastic material such as polyamide, which seals the structure against moisture and other external elements which can cause deterioration and degradation of the behavior. The encapsulant Si3N4 can be deposited, for example, using a plasma deposition process at a low temperature. The polyamide material can be spin coated and baked after deposition according to known techniques to form the encapsulating layer. The term "pore diameter" as used herein is the average cross section of the smallest region of contact between the composite memory material 36, and the electrical contacts 6 and 8. The pore diameter can be as small as the limits of lithographic resolution will allow. The pore diameter is related to device behavior. The reducing pore diameter reduces the volume of the device, so that the current and energy requirements necessary for electrical commutation are reduced. This increases the speed and sensitivity of the device - reducing the switching time and electrical power required to initiate the detectable change in resistance. In prior embodiments of the memory element it is preferred that the pore diameter be selected to substantially conform to the cross section of the memory material whose strength is actually disturbed when the material is switched to either a high or low resistance state. This section of memory material is called the "filamentary portion". Ideally, the pore diameter should be equal to the diameter of the filamentary portion. As a means to reduce the pore diameter beyond that allowed by lithography, the prior arrangements of the memory element have employed "filament confining means" between at least one of the separately arranged contacts and the volume of memory material. . The filament confining means is typically a thin film layer of highly resistive material with at least one low resistance path through which current passes between the electrical contact and the volume of memory material. The filament confinement means provides a high current density within the filamentary portion from the entry of a very low electric current to the separately arranged contacts. The filament confining means plays a role in the "electrical forming process" of the memory device. The electric forming process consists of applying electric current impulses superior to the built-up memory element until the memory element switches from its "virgin" resistance value originally very high to a lower resistance value. Once this happens, the memory element will be "formed". It is now easy for the minor programming current to perform the electrical cycle. The forming process "decomposes" the filament confining means. During one or more of the higher current pulses applied during the forming process, the electrically weaker "decomposition" region in the confinement layer is physically changed and becomes more highly conductive than the rest of the layer. It is through this region that the entire current of any of the subsequent memory cycling pulses (ie, fixed and deflected pulses) will pass. When a very low current is applied to the memory element, all current is channeled through the filament portion. Therefore, due to its extremely small size, the current density is very high within this region of the memory material. In prior embodiments of the memory element, the programming current required for electrical cycling is decreased by either lithographic reduction of the pore diameter or via the introduction of a filament confining means. In contradistinction thereto, in a memory element comprising the composite memory material of the present invention, the desired decrease in the programming current is achieved by restricting the volume of the phase change material via the introduction of the inactive dielectric material. The dielectric material can be made to occupy a selected volume fraction of the new composite material thereby reducing the volume fraction occupied by the active phase change memory material. This reduction in the volume fraction of the active phase change memory material decreases the current necessary to program the memory element. Since the volume fraction of dielectric material can be controlled, in thin film memory applications, the volume of electrically conductive material can be controlled independently of the size of the photolithographically defined contact area. This can allow a reduction in the programming current required on a given scale of photolithography to a value consistent with the current that can be supplied by the memory drives. The composite material serves in this way as a function similar to that of the filament confining means described above. As with the filament confining means, the composite material can define the cross-sectional area of the filament portion within the memory material during both electrical training and during commutation. Therefore, the composite material of the present invention can be used to solve the lithographic limitations of creating a small pore without the need to use an additional layer of the material. Also described herein is a memory element of a cell, electrically operated, written directly, of multibitios comprising a volume of memory material defining a memory element of a cell, the memory material consisting of means to assume a large dynamic range of electrical resistance values with the ability to directly fix to a plurality of resistance values within the dynamic range without the need to set to a specific erased start or resistance value, regardless of the previous resistance value of the material in response to the selected electrical input signal to provide the single cell with multi-bit storage capabilities. The memory element of a cell, electrically operated, written directly, multi-bit further comprises a pair of contacts arranged separately to supply the electrical input signal for fixing the memory material to a selected resistance value within the dynamic range. At least one of the contacts arranged separately is a mixture of a first and second contact material. The first contact material includes carbon, and the second contact material includes at least one transition metal element. The term "transition metal" as used herein includes elements 21 to 30, 39 to 48, 57 and 72 to 80. Preferably, the second contact material includes one or more elements selected from the group consisting of Ti, V , Cr, Zr, Nb, Mo, Hf, Ta, W and mixtures or alloys thereof. More preferably, the second contact material includes Ti and W. The contact can be made by a co-flashing process. The top view of a possible configuration for multiple memory elements is shown in Figure 2. As shown, the devices form an X-Y array of memory elements. The horizontal strips 12 represent the group X of an X-Y electrode mesh to address the individual elements. The vertical strips 42 represent the group Y of addressing lines. Other circuit configurations for electrically erasable memory of the present invention are, of course, possible and feasible to complement. A particularly useful configuration is a three-dimensional, multi-layered arrangement in which a plurality of memory or control element planes and their respective isolation devices are stacked one on top of the other. Each plane of memory elements is arranged as a plurality of lines and columns of memory elements, whereby addressing X-Y is allowed. This application of plans, in addition to increasing the memory storage density, allows an additional Z dimension of interconnection. This arrangement is particularly useful for stimulating a neural network for a truly intelligent computer. Each memory element is electrically isolated from others using some type of insulation element. Figure 3, a schematic diagram of the plane of the memory device, shows how electrical isolation using diodes can be performed. The circuit comprises an X-Y mesh with the memory elements 30 which are electrically interconnected in series with isolation diodes 26. The steering lines 12 and 42 are connected to external steering circuitry in a manner well known to those skilled in the art. The purpose of the isolation elements is to allow each discrete memory element to be read and written without interfering with information stored in adjacent or distant memory elements of the array. Figure 4 shows a portion of a single crystal semiconductor substrate 50 with a memory array 51 of the present invention formed therein. Also formed on the same substrate 50 is an address array 52 which is suitably connected by integrated circuitry connections 53 to the memory array 51. The address array 52 includes signal generating means which define and control the setting and reading of pulses applied to the memory array 51. Steering array 52 includes signal generating means which define and control the set and read pulses applied to memory array 51. Of course, the address array 52 can be integrated with and formed simultaneously with the solid state memory array 51. Experimentation has shown that factors such as chalcogenide composition, thermal preparation (post-deposition annealing), signal pulse duration, impurities such as oxygen present in the composition, crystallite size and waveform conformation of signal pulse have an effect on the magnitude of the dynamic range of resistances, the absolute end point resistances of the dynamic range, and the voltages required to fix the device to these resistances. For example, relatively thick chalcogenide films (ie, approximately 4000 A) will result in higher clamp voltage requirements (and therefore higher current densities within the volume of memory material), while relatively thin chalcogenide layers (ie, approximately 250 A) will result in lower fixation (and current density) voltage requirements. Of course, the possible meaning of crystallite size and, therefore, the ratio of the number of surface atoms to the number of atoms of volume has been previously described. The dynamic range of resistors also allows a wide gray scale and multi-layered analog memory storage. The multilayered memory storage is performed by dividing the wide dynamic range into a plurality of sub-ranges or levels. The continuous resistance programming capability allows multiple bits of binary information to be stored in a cell of a memory. This multi-layered storage is performed by imitating multiple bits of binary information in a pseudo analog form and storing this analogous information in a single memory cell. In this way, by dividing the dynamic range of resistances into 2O analogous levels, each memory cell can be provided with the capacity to store n bits of binary information. Through the use of the patented materials and device configurations described herein, a directly written, electrically erased memory element has been developed which provides fast read and write speeds, achieving those SRAM devices; reprogramming capabilities of non-volatile and random access of an EEPROM, and a price per megabit of storage significantly below any other semiconductor memory. It is understood that the description set forth herein is presented in the form of detailed embodiments described for the purpose of making a full and complete description of the present invention, and that such details are not construed as limiting the true scope of this invention as indicates and defines in the appended claims.

Claims (25)

1. CLAIMS 1. An electrically operated memory element, characterized in that it comprises a volume of memory material comprising: A mixture of phase change memory material and inactive dielectric material; and A pair of contacts arranged separately to supply an electrical signal for the previous material. The memory element according to claim 1, characterized in that the memory material includes one or more elements selected from the group consisting of Te, Se, Ge, Sb, Bi, Pb, Sn, As, S, Si, P, O and mixtures or alloys thereof. 3. The memory element according to claim 1, characterized in that the dielectric material is one or more elements selected from the group consisting of oxides, nitrides, fluorides, sulfides, chlorides, carbides, oxynitrides, carboxy nitrides, borides, phosphides, and mixtures thereof. . The electrically operated memory element characterized in that it comprises a volume of phase change memory material; and a pair of separately arranged contacts that supply an electrical signal of the memory material where at least one of the contacts is a mixture of the first contact material and a second contact material, the first contact material includes carbon, the second material contact includes at least one transition metal element. The memory element according to claim 1 characterized in that the second contact material also includes one or more elements selected from the group of Ti, V, Sr, Zr, Nb, Mo, HF, Ta, W and a mixture of the same. 6. The composite memory material according to claim 3, characterized in that at least one transition metal is selected from the group consisting of Cr, Fe, Ni, Nb, Pd, Pt and mixtures or alloys thereof. The composite memory material according to claim 1, characterized in that the dielectric material is one or more materials selected from the group consisting of oxides, nitrides, oxynitrides, carbonitrides, fluorides, sulfides, chlorides, carbides, borides, phosphides and mixtures or alloys thereof. 8. The composite memory material according to claim 1, characterized in that the dielectric material is an organic dielectric material. 9. The composite memory material according to claim 1, characterized in that the volume percentage of the dielectric material is between about 10% and about 90%. 10. The composite memory material according to claim 9, characterized in that the volume percentage of the dielectric material is between about 20% and about 80%. 11. The composite memory material according to claim 10, characterized in that the volume percentage of the dielectric material is between about 40% and about 60%. 12. A single cell memory element characterized in that it comprises: A volume of memory material defining a single cell memory element, the memory material comprising a mixture of active phase change material and inactive dielectric material; and A pair of separately arranged contacts, the contacts that provide terminals to read information stored in and write information to the memory element. The memory element according to claim 12, characterized in that the phase change memory material includes one or more elements selected from the group consisting of TE, Se, Ge, Sb, Bi, Pb, Sn, As, Yes, Si, P, O and mixtures or alloys thereof. The memory element according to claim 13, characterized in that the phase change memory material includes at least one chalcogen element and at least one transition metal element. 15. The memory element according to claim 14, characterized in that the chalcogenic element is selected from the group of Te, Se, and mixtures or alloys thereof. 16. The memory element according to claim 15, characterized in that the chalcogenic element is a mixture of both Te and Se. The memory element according to claim 14, characterized in that the at least transition metal element is selected from the group consisting of Cr, Fe, Ni, Nb, Pd, Pt, and mixtures or alloys thereof . The memory element according to claim 12, characterized in that the dielectric material is one or more materials selected from the group consisting of oxides, nitrides, fluorides, sulfides, chlorides, carbides, oxynitrides, carboxy nitrides, borides, phosphides and mixtures or alloys thereof. 19. The memory element according to claim 12, characterized in that the dielectric material is an organic dielectric material. The memory element according to claim 12, characterized in that the volume percentage of the electrical material is between approximately 10% and approximately 90%. 21. The memory element according to claim 20, characterized in that the volume percentage of the dielectric material is between about 20% and about 80%. 22. The memory element according to claim 21, characterized in that the volume percentage of the dielectric material is between about 40% and about 60%. 23. A memory element of an electrically operated, directly written, multibit cell characterized in that it comprises: A volume of memory material defining a memory element of a cell, the memory material constituting means for summing up a large dynamic range of electrical resistance values with the ability to be set directly to a plurality of resistance values within the dynamic range without the need to be set to a specific starting or erasing resistance value, regardless of the previous resistance value of the material in response to an electrical input signal selected to provide the individual cell with multibit storage capacities; and A pair of contacts arranged separately to supply the electrical input signal for fixing the memory material to a selected resistance value within the dynamic range, wherein at least one of the contacts arranged separately is a mixture of a first material of contact and a second contact material, wherein the first contact material includes carbon, and wherein the second contact material includes at least one transition element metal. The memory element according to claim 23, characterized in that the second contact material includes one or more elements selected from the group consisting of Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, W and mixtures or alloys thereof. 25. The memory element according to claim 24, characterized in that the second contact material includes Ti and W.