MXPA98000692A - Elements of memory of celda unica of multiples bits, with electric determination and direct over-writing and arrangements manufactured of the - Google Patents

Abstract

The present invention relates to an electrically operated memory element (30) including a volume of memory material (36) characterized by a large dynamic range of electrical resistance values, and the capacity of at least a portion of filament to be adjusted by means of the selected electrical signal at any resistance value in the dynamic range, regardless of the previous resistance value of the material to provide a single cell with storage capacity for multiple bits. The memory element (30) also includes a pair of contacts (6, 8) includes (1) a thin film layer (34, 38) preferably titanium carbonitride or titanium siliconitride, disposed adjacent to the memory material (36) used as a diffusion barrier to inhibit the entry of foreign material into the memory material (36), and (2) a thin film layer (32, 40), preferably a Ti-W alloy, placed remote disposed to the memory material used to provide a barrier to electromigration, aluminum diffusion and provide ohmic contact at the aluminum interface

Description

ELEMENTS OF SINGLE-CELL MEMORY OF MULTIPLE BITS, WITH ELECTRIC DELETION AND DIRECT OVER-WRITING AND ARRANGEMENTS MANUFACTURED FROM THEM DESCRIPTION OF THE INVENTION This application is a partial continuation of the US application. do not. series 08 / 423,484 filed March 19, 1995, which is a partial continuation of the US application. do not. series 08 / 789,234 filed November 7, 1991, now US Pat. do not. 5,414,271 which is a partial continuation of the US application. No. 07768,139 filed September 30, 1991, now US Pat. do not. 5,335,219, and a partial continuation of the request for USA not of series 07 / 747,053 filed on August 19, 1991, now US patent do not. 5,296,716, each in turn partial continuations of the US application. serial number 07 / 642,984 filed on January 18, 1991, now patent of USA do not. 5,166,758. The present invention relates to a unique single-cell analogue and multilevel memory element of solid state, electrically and optically operated, directly overwritable, low energy, with very fast switching and to memory arrays manufactured with those elements. More specifically, the present invention relates to a new chemical composition for the contact layers that are an integral part of the memory element.

The Ovonic EEPROM is a novel thin-film, non-volatile, high performance, patented electronic memory device, its advantages include non-volatile data storage, power for high bit density, and consequently, low cost due to its small configuration and simple of two terminals, long repogramming life cycle, low programming energy and high speed. The Ovonic EEPROM is capable of storing information both analog and digital. Digital storage can be either binary (one bit per memory cell) or multi-state (multiple bits per cell), only small modifications are required to switch between the two digital modes. For the purposes of the present invention, the terms "memory elements" and "control elements" can be used interchangeably as synonyms. EARLY PHASE CHANGE MEMORY The general concept of using phase change materials in which you can write and erase electrically (This is materials that can be electrically modified between generally amorphous and generally crystalline states) for applications in electronic memories is well known in. the technique, as described for example in the patent of USA do not. 3,271,591 to Ovshinsky, published September 6, 1996 and in U.S. Pat. do not. 3,530,441 to Ovshinsky, published September 22, 1970, both by the same owner of the present invention (hereinafter referred to as "Ovshinsky patents"). As described in the Ovshinsky patents, those phase change materials can be electrically modified between generally amorphous and generally crystalline structural order states or between different local detectable states across the spectrum, completely amorphous and completely crystalline states . That is, the ovshinsky patents that the electrical commutation of these materials should not take place between completely amorphous and completely crystalline states but can be increasing stages that reflect changes of local order to provide a "gray scale" represented by a multiplicity of conditions of the local order expanding the spectrum between completely amorphous and completely crystalline states. The above materials described in the Ovshinsky patents could also, if required, switch between only the two generally amorphous and generally crystalline structural order states to result in storage and retrieval of joined bits of coded binary information. The phase shift memories with electric blanking described by the Ovshinsky patents, as well as the subsequent solid state electrical memory, had several limitations: (i) a relatively slow electrical switching speed (according to current standards) particularly when switching in the direction of greatest local order (in the direction of greatest crystallization); (ii) a relatively high energy requirement to initiate a detectable change in the local order, and (iii) a relatively high cost per megabyte of stored information (particularly compared to current hard disk media). The most important of these limitations is the relatively high energy input required to obtain detectable changes in the chemical and / or electronic bond configurations of the chalcogenide material to initiate a detectable change in the local order. Also important were the modification times of the electrical memory materials described in the Ovshinsky patents. These materials typically required times in the range of a few milliseconds for the fixation time (the time required to modify the material from the amorphous to the crystalline state); and about one millisecond for the reset time (the time required to return the material from the crystalline state to the amorphous state). The electrical energy required to modify those materials typically measured in the range of approximately one mierojoule. It should be noted that this amount of energy must be conducted to each memory element in the solid state matrix of rows and columns of memory cells. These high energy levels translate into high power requirements for the addressing lines and for the cell addressing / isolating device associated with each discrete memory element. Taking into consideration these energy requirements, the options of memory cell insulator elements for someone skilled in the art would be limited to a single very large glass insulator device for diodes and transistors, which would make it impossible to use micrographic lithography and therefore the high density of memory elements. Thus, the low bit densities of matrix arrays made of this material will result in a high cost per megabyte of stored information. By reducing the price and performance distinction between the archivable non-volatile mass memory and the fast volatile system memory, the memory elements of the present invention provide a new non-hierarchical "universal memory system". Essentially all the memory in the system can be cheap, archivable and fast. Compared to Ovshinsky-type electric phase shift memories, the memory materials described here provide programming times more than six orders of magnitude greater (less than 30 nanoseconds) and the use of extremely low programming power (less than 0.1 to 2 nanjoules) with a proven long-term stability and cyclability (more than 10 trillion cycles). Also, experimental results indicate that additional reductions in element size can increase switching speeds and cycle life. A newly developed memory device is the amorphous metal electrical memory switch (MSM). See Rose et al. "Amorphous Silicon Analogue Memory Dvices" Journal of non Crvstallline Solids. 115 (1989), p. 168-70 and Hajto et al. -Transport of electrons quantified in amorphous silicon memory structures "Physical Review letters, vol 66, No. 14, April 8 *, 1991, pages 1918-21 The MSM switch is manufactured by means of the deposition of metallic contacts Specifically selected on either side of a thin film of amorphous silicon (a-Si) type P. The importance of the selection of metallic contact materials will be discussed later.The MSM memory switches are described with a relatively fast analog switching behavior (10-100ns) for voltage pulses of 1-5 volts, providing a resistance range of approximately 103 to 10ß ohms in which they can be adjusted in a non-volatile manner, as should be apparent to those skilled in the art, switches of MSM memory by Rose et al. and Hajto et al., although they have electrical switching characteristics (this is, energies and resulting resistance) similar to the electrical switching characteristics of the memory elements of the present invention, there are actually important differences between them. The most important electrical switching difference lies in the impossibility of overwriting directly into the MSM memory switches. That is, MSM switches can not be directly bi-directionally modulated from any resistance in the analog range of resistors to any other resistance in the range without first being erased (adjusted to a specific initial resistance or 'initial state'). More specifically the MSM switch must first be set to a high resistance (clear) state before the switch can be adjusted to gold resistance value within the analog range. In contrast, the memory elements of the present invention do not need to be erased before setting another resistance in the range, that is, they can be overwritten directly on them. Another important difference in the electrical switching characteristics that exist between the MSM memory switches of Rose et al. and Hajto, et al. and the electrical memory elements of the present invention is the bipolar behavior of the MSM switches. As described by Rose et al, MSM switches must be erased using reverse polarity electrical pulses from those pulses used for writing. Significantly, this inversion of applied pulse polarity is not required in the memory elements of the present invention, whether the present memory elements are used for digital or analog switching. These differences in the electrical switching characteristics between the MSM switches and the memory elements of the present invention indicate the fundamental differences in the switching mechanisms that characterize the operation mode of the two devices. The electrical switching characteristics of the MSM memory switches critically depend on the metal (s) from which the contacts are manufactured. This is because those MSM switches require an "energetic" "forming" process in which the metal of at least one of the contacts is transported and formed as an integral portion of the switching body. In this process, a plurality (at least 15 of Figure 1 of the Rose et al. Document) of pulses of 5-15 volts progressively growing 300 nanoseconds, are employed to form the switch. Rose et al affirm "..the X-ray microanalysis studies of the devices have been carried out and the upper electrode material embedded in the filamentous region of a-Si has been found." This suggests that the upper material is distributed in the filament and may have a role in the switching mechanism .. "Rose et al also specifically found that the dynamic range of existing resistors is determined by the metal from which the upper electrode contact is made. As affirmed by Rose et al. : it has been found that its value is completely dependent on the upper contact, and completely independent of the lower metallization, that is, the upper electrode devices of Cr are always digital and the upper electrode devices V are always analog without taking the electrode into account lower. It is within 1 metal filament region where electrical commutation is performedand without this mass migration of the metal in the a-SI, there would be no commutation, see document Hajto et al. In contrast, the memory elements of the present invention do not require migration of the contact material in the thin film memory element to obtain a very fast, low energy, analog and direct overwrite memory switch. Indeed, in the manufacture of the memory elements of the present invention, care is taken to prevent diffusion of the metal from any electrode to the chalcogenide material. MSM memory switches do not qualify as a free charge concentration modulator. These switches simply rely on the creation of a filamentary metal path through the amorphous silicon material to obtain a range of resistivities in the same way that a modulated switch is used to control the flow of electrical current. A filtering path is established, whose diameter can be increased or decreased to change its resistivity; movements of the positions of the Fermi levels in the switching process are not included. It is not required to go to the changes in the activation of the semiconductor material to explain the operation. There is no atomic-scale movement of unlinked electron pairs. The size of the crystallite or its surface to volume ratio is not important. But most importantly, it is impossible for Rose et al and Hajto et al to directly overwrite the information stored in the cells of their memory material. The MSM switch requires that the stored information be deleted before new information can be stored. No solid state memory system developed in advance of the present invention has been inexpensive, easy to manufacture, non-volatile, with direct writing and direct erasing (overwriting) using low input energies; multi-bit storage layers in a single cell(with a gray scale); and capable of a very high packing density. The memory system described below, because it overcomes all the shortcomings of known memory systems, we will find an immediate diffusion of use as a universal replacement for virtually all types of computer memories currently on the market. It was said before that an important consideration in the design and manufacture of the present invention is to prevent the diffusion and electromigration of the metallic electrode material in the chalcogenide memory material. Previous memories of Ovonic EEPROM included two layers of carbon thin film that were deposited adjacent to the upper and lower chalcogenide memory material. An important role played by the carbon was that of diffusion barrier preventing the foreign material from entering the chalcogenide. Although it has good diffusion barrier properties, carbon unfortunately presents several problems when used as a material during semiconductor fabrication technical appointments. For example, when a carbon target is used during the sputter deposition process, the carbon particles can be a source of contamination of the device and apparatus. As well as when the carbon is part of a semiconductor device that is subject to a dry resistance deposition process, the exposed carbon layers can be removed by the same oxygen plasma used to remove the photoresist material, making the procedure unsuitable, due to Those problems, carbon is not well accepted in the semiconductor industry as good material for the manufacture of devices. Therefore, there has been a need to find a suitable replacement material that has at the same time the properties necessary for the proper operation of the Ovanic EEPROM device, be more compatible with the most current semiconductor processing techniques.

Single-cell memory elements are described here, essentially new ones of solid state, with direct overwriting, electronic, non-volatile, high density, low constellation, easy fabrication, which have reduced switching current requirements and great stability. thermal data stored in them. These memory elements use a unique class of chalcogenide memory materials that exhibit speeds several orders of magnitude greater than the chalcogenide memory materials prior to markedly reduced energy levels. The novel memory materials, from which the elements and memory arrays of the present invention are formed, are characterized inter alia by stable and truly non-volatile detectable configurations of atomic and / or electronic order that can be selectively and repeatably set by means of of electrical input signals of different pulses of current, voltage and duration. The memory devices of the present invention are therefore switchable between atomic and / or electronic configurations of different local order to provide at least two stable settings. The orders of magnitude of the improvement in the switching speeds and in the switching energies made possible by means of the memory elements described here is not only incremental in nature, but because it represents a fundamental improvement beyond what was previously thought That was possible.

Although the theories of memory materials described here are currently being investigated, none of the proposed theories explains all the extraordinary electrical switching behaviors. Specifically, the semiconductor materials can be switched between several electrically detectable conditions in nanosecond time period with the power input of picojoules. The present memory materials are really non-volatile and they can be recycled (written and rewritten) almost indefinitely while maintaining the integrity of the information stored in the memory cell without the need for periodic refresh signals. The present memory material can be directly overwritten in such a way that the information stored in the other memory elements does not need to be erased (as required by ferroelectric storage systems and other instantaneous ones) in order to change the information stored in a memory. given group of memory elements. One embodiment of the present invention comprises a single cell memory element, of multiple bits, directly overwritable, electrically operated. The memory element includes a volume of memory material that defines the memory element of a single cell. The memory material is characterized by (1) a broad dynamic range of electrical resistance values (2) the ability to adjust one of a plurality of resistance values within a dynamic range in response to the electrical input signals selected to provide the storage capacity of multiple bits in a single cell; and 93) the ability to adjust at least one filament portion, by means of the electrical signal to any resistance value in the dynamic range regardless of the previous resistance value of the material. The memory element also includes two separate electrical contact layers pi to provide the electrical input signal to adjust the memory material to a selected resistance value within the dynamic range. Each electrical contact layer includes a layer of thin film that is deposited adjacent to the memory material. At least one of the adjacent thin film layers consists of one or more elements selected from the group consisting of Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, W and their mixtures and alloys, in combination with two or more elements selected from the group consisting of B, C, N, 0, A1 Si, P, S and mixtures and alloys thereof. Preferably, at least one of the adjacent thin film contact layers consists of titanium carbonitride or titanium silicotitrute. Each of the separately arranged contacts preferably includes an additional thin film layer positioned away from the memory material. Distant thin film layers consist of one or more elements selected from the group consisting of Ti, W, Mo and mixtures or alloys thereof. Preferably each remote thin film layer is an alloy consisting of Ti and W. Other embodiment and features of the present invention as well as other advantages and objects will be determined and will be apparent from the detailed description of the invention which follows, especially when Take in combination with the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross-sectional view of a simple memory element; Figure 2 is a top view of a possible distribution of multiple elements showing how the elements would be connected to a pair of X-Y direction lines; Figure 3 is a schematic diagram of the memory elements of Figure 2 further showing how the insulating elements such as diodes are connected in series with the memory elements to electrically isolate each of the devices from each other; Figure 4 is a schematic representation illustrating a single crystal semiconductor substrate with the integrated memory array of the present invention as shown in Figure 1 placed in electrical communication with an integrated circuit pickup on which the routers are operatively fixed. / impellers / decoders; Figure 5 is a ternary phase diagram of the Ge: Sb: Te alloy system from which the memory elements of the present invention are manufactured, that phase diagram shows some of the multiple phases in which various mixtures of those elements are add after rapid solidification; Figure 6 shows the formation of atomic structural layers of three ternary alloys of the Ge-Sb-Te system of Figure 6 as well as the atomic structure of binary Ge-Te to illustrate the anisotopic structure of the system; Figure 7 is a graphical image of the data illustrating cycle characteristics of a memory element with an adjacent upper contact layer consisting of titanium carbonitride and a lower adjacent contact layer consisting of carbon; Figure 8 is a graphical image of the data illustrating cycle characteristics of a memory element with an adjacent upper contact layer consisting of titanium siliconitride and a lower adjacent contact layer consisting of carbon; Figure 9 is a graphical image of the data illustrating the capability of multiple states (ie the ability of the memory element to be adjusted at multiple resistance levels within the dynamic range of resistors) of a memory element with a layer of adjacent contact consisting of titanium carbonitride; Figure 10 is a graphical image of the data illustrating the values of adjustment strength and readjustment of memory devices with upper adjacent contact layers consisting of titanium carbonitrate material of four different resistivity values. Erasable electrical memories manufactured from the broad class of chalcogenide materials have employed structural changes that were obtained by the movement of certain atomic species within the material to allow phase change by changing the material from the amorphous state to the crystalline state. For example in the case of electrically modifiable chalcogenide alloys formed of tellurium and geranium such as those comprising about 80 to 85% tellurium and about 15% germanium together with other elements in small amounts of about one to two percent each , such as sulfur and arsenic; the most ordered or crystalline state was typically characterized by the formation of a highly electrically conductive crystalline Te filament within the modifiable pore of the memory material. A typical composition of this prior art material would be for example TeßiGßisSaASa or Te81gelsS2Sb2. Because Te is highly conductive in its crystalline state, a condition of very low resistance was established throughout the Te filament in the most orderly or crystalline state; this resistance is several orders of magnitude less than pore resistance in a less ordered or amorphous form. However, the formation of a conductive Te strand in the crystalline state requires the migration of atoms from their atomic configuration in the amorphous state to the new atomic configuration locally concentrated in the crystalline Te filament state. Similarly, when the chalcogenide filament material returned to its amorphous state, the Te that had receded into the crystalline filament had to migrate into the material from its locally concentrated form in the filament back to its atomic configuration in the amorphous state. . This migration, diffusion or atomic rearrangement between the amorphous and crystalline states required in each case a waiting time or delay long enough to lead to migration making the required switching time and energy very high. The present inventors have described a marked reduction in the required switching time and power input for a fundamentally different type of electrically erasable memory, directly overwritable in a new class of chalcogenide semiconductor materials. furtherThe chalcogenide materials provide commutation within a wide dynamic range of stall states with remarkably low energy inputs and remarkably fast speeds so that the newly discovered class of materials can be used to manufacture improved memory elements. Specifically, the memory material can be modified between electrically detectable conditions of different resistance in nanosecond time periods (the minimum switching speed and the minimum energy requirements have not yet been determined, however the experimental data in presenting this request have shown that the electrical memory can be modulated (although not optimized) with programming pulses as small as 1 nanosecond, with an input of picojoules of energy.This memory material is not volatile and will maintain the integrity of the information stored in the memory cell ( with a margin of error selected) without the need for periodic refresh signals.In contrast to many other semiconductor materials and systems hitherto specified for memory applications, the material is semiconductor memory and the systems of the present invention can be overwritten directly in such a way that the ele discrete memory items do not need to be erased (adjusted to a specific starting point) in order to change the information stored there. The remarkably fast and low-energy switching to any of the different resistance values can be attributed to the fact that such switching occurs without the need for significant atomic arrays of the switching material.

The memory material is formed of a plurality of constituent atomic elements, each of which is present throughout the volume of memory material. The plurality of constituent atomic elements preferably include at least one chalcogenic element and can include at least one transition metal element. The term "transition metal" used herein includes elements 21 to 30, 39 to 48, 57 and 72 to 80. More preferably the plurality of constituent atomic elements forming the volume of memory material include elements selected from the group consisting of Te , Se, Ge, Sb, Bi, Pb, Sn, As, S, Si, P, 0 and their mixtures or alloys, more preferably the transition metal includes Cr, Fe, Ni and their mixtures or alloys and the chalcogenic element includes Tea and Se. more preferably the transition metal is Ni. Specific examples of such multi-element systems will be mentioned below with respect to the Te: Ge: Sb system with or without Ni and / or Se. Without taking into account the explanation of how programming is performed, the present invention provides a combination of valuable electrical switching characteristics never before existing in a single memory element. The specific semiconductor alloys employed in the manufacture of the memory devices include chalcogenide elements which are characterized particularly by the presence of "solitary pairs" of electrons. Therefore it is necessary to discuss the effect of those lone pairs of electrons in the existing chemical bonding configurations. Put simply, a lone pair is a pair of electrons in the valence band of an atom that is typically not included in the bond. These lone electron pairs are important both structurally and chemically. They influence the shape of the molecules and crystal lattice structures by exerting strong repulsive forces on neighboring pairs of electrons that are included in the binding configurations as well as on other solitary pairs. These lone pairs of electrons are not limited in a binding region by a second nucleus, they are capable of including and contributing to low energy electronic transitions. As Ovshinsky first pointed out, lone pairs can have 1 and 3 center links; as shown by Kasner, Adler and Fritsche, they have alternating pairs of valence. Specifically, the tellurium alloys described here have a valence band conformed by states of solitary pairs, since four (4) electrons of the p band are present in te, and the te atom is chemically bound by two of those bond electrons in the p-band, the external electrons (the lone pair) are not used for binding purposes and therefore do not substantially change the atomic energy of the system. In this regard, it should be noted that the highest molecular orbit is the orbit that contains the lone pair of electrons. This is important because, in a perfect stoichiometric crystal of tellurium and germanium atoms, up to the application of some internal tension in the network from which the crystallite is formed, the valence band can be extended and moved up to the position of the level of existing fermi then. However, the TeGe crystals are naturally self-compensating, that is, the crystal preferably wants to assume a Te-rich composition (approximately 52 percent Te and 48 percent Ge). The stoichiometric crystal is a cube with a central face; However, with the addition of a minimum amount of energy, the crystal can assume a rhombohedral structure by increasing the number of its Ge and / or Sb gaps. In this creation of gaps in the crystal lattice structure, which can reduce The tension in the TeGe alloy network is responsible for decreasing the energy state of the material and moving the Fermi level towards the valence band. It is acceptable if not essential to superimpose an amorphous model of local order on the top of a short-range local order model with the purpose of obtaining a descriptive explanation if not perfectly predictive of atomic behavior. When considering the amorphous nature of the material, it should be noted that the density of the defective states at the ends of the bands is greater adjacent to the edges of the bands. The presence of these deep traps and extreme states would pde a possible explanation of stable intermediate resistance values between the Fermi level position and the edge of the band. Despite the theory, when it is completely crystalline, the semiconductor material of the present invention is a degenerate semiconductor having a metallic type conduction. It is further believed that the size of the crystallites that exist in the mass of the semiconductor and the memory material is relatively small preferably less than about 2000 A, more preferably between about 50 and 500 A, and more preferably in the order of about 200 A to 40? Furthermore, these crystallites are believed to be surrounded by an amorphous crust that can contribute to the rapid formation of many positions of the Fermi level in the material, detectable as different resistances (conductivities) as well as the lower energy requirements for transitions between these values. of detectable resistance to which the material can be reliably and repeatable. It has been found that the modulation of the switching characteristics of two or three terminal semiconductor devices made of microcrystalline materials of the present invention can be controlled in such a way that repeatable and detectable resistance values can be obtained. It has been found that in order for the materials of the present invention to be adjusted rapidly by means of low energy input signals at a desired conductivity determined by the position of the Fermi level) it is only necessary that those materials are capable of existing Stable (or metastable prolonged) within at least two different Fermi level positions, the Fermi level positions are characterized by substantially constant band spaces but different electrical conductivities As noted above, it is also believed that the crystallite size is relatively small can contribute to the rapid transition between detectable resistance values. A feature of the semiconductor materials of the present invention is their tendency to form more and less crystallites by volume bonding. The crystallite sizes of the widely preferred range of representative materials of the present invention are less than about 2000 A, and generally less than the range from about 2000 to 5000 A having the characteristics of prior art materials. The crystallite size is defined here as the diameter of the crystallites or their "characteristic dimension" which is equivalent to the diameter at which the crystallites do not have spherical shape. It has been determined that compositions of the very high resistive state of the class of TeGeSb materials that meet the criteria of the present invention are generally characterized by substantially reduced concentrations of Te in relation to the electrically erasable memory materials of the art. previous. In a composition that pdes substantially impd electrical commutation characteristics, the average concentration of Te in the deposited materials was below 70%, typically below about 60% and varied from about 235 to about 58% Te and more preferably about 40%. to 58% Te. The concentrations of Ge were above about 5% and in the range of about 8 to 30% per average in the material, generally staying below 50%. The rest of the main constituent elements in this composition was SB. The percentages given are atomic percentages that add up to 100% of the atoms of the constituent elements, so the composition can be characterized as TeaGebSb100_ (a + b). These Te-Ge-sb ternary alloys are useful starting materials for the development of additional memory materials that have better electrical characteristics. A ternary diagram of the Te: Ge: Sb system is shown in figure 6. Fusions of different mixtures of Te, Ge and Sb, the melts were segregated in multiple phases after rapid solidification. Analysis of these solidified melts rapidly indicated the presence of ten different phases (not all present in a rapidly solidified melt). Those phase are; Ge, Te and Sb elementals, the GeTe binary compounds, Sb2Te3 and five different ternary phases. The elemental composition of all the ternary phases are based on pseudo-binary GeTe-Sb2Te3 and are indicated by means of the reference letters A, B, C, D and E in the ternary diagram shown in Figure 6. The atomic proportions of the elements In these five ternary phases, they are mentioned in Table 1. A more detailed description of Figure 6 is presented below. Table I Observed ternary crystalline phases of the TeGeSb system Designation% Ge% of Sb% of Te A 40 10 50 B 26 18 56 C 18 26 56 D 14 29 57 E 8 35 56 The novel memory elements of the present invention include a volume of memory material, that memory material preferably includes at least one chalcogen and can include one or more transition metals. Memory materials that include transition metals are elementally modified forms of our memory materials in the Te-Ge-Sb ternary system. this is the modified memory materials elementally constitute modified forms of memory alloys Te-Ge-Sb. this elementary modification is achieved through the incorporation of transition metals in the Te-Ge-Sb ternary system, with or without an additional chalcogenic element such as Se. Generally elementary modified memory materials fall into two categories. First a memory material that includes Te, Ge, Sb and a transition metal, in the proportion (TeaGebSb100. (A + b,) cTM10o-c in which the subscripts are the atomic percentages that add up to 100% of the elements constituents, where TM is one or more transition metals y and b are as described above the Te-Ge-Sb ternary system and c is between 90 and 99.5% The transition metal may preferably include Cr, Fe, Ni and mixtures thereof Alloys Specific examples of memory materials encompassed by this system include (Te56Ge22Sb22) 95Ni5, (TeS6Ge22Sb22) 90Ni10, (Te56Ge22Sb22) 95Cr5, (TeB6Ge22Sb22) 90Cr10, (Te56Ge22Sb22) 95Fe5, (Te56Ge22Sb22) MFe10, (Te56Ge22Sb22) 95Ni5Cr5, (TeS6Ge22Sb22) ), oNi5Fe5, (Te56Ge22Sb22) 90Cr5Fe5, etc. The second is a material that includes Te, Ge, Sb, Se and a transition metal, in proportion (TeaGebSb100. < a + b)) cTMdSe100_ (c + d) where the subscripts are the atomic percentages that add up to 100% of the constituent elements, where TM is one or more transition metals and a and b are as described above the Te-Ge-Sb ternary system and c is between 80 and 99% and d is between about 0.5 to 10%. The transition metal may preferably include Cr, Fe, Ni and mixtures of its alloys. Specific examples of memory materials encompassed by this system include (Te5ßGe22Sb22) 90Ni5Se5 (Te5ßGe22Sb22) .oNi-.0Se10, (Te56Ge22Sb22) TOCr5Se5, (Te56Ge22Sb22) ß0Cr10Se10, (Te56Ge22Sb22) 90Fe5Se5, (Te56Ge22Sb22) 80Fe10Se10, (Te56Ge22Sb22) ß5NisCrsSe5, ( Te56Ge22Sb22) ßoNi5Fe5Se10, (Te56Ge22Sb22) 90CrsFe5Se5, etc. The memory elements of the present patent application possess values of resistance to substantially non-volatile istes. However, if the resistance value of the present memory elements, under some circumstance deviates from its originally adjusted value, the "composition modification", described below, can be used to eliminate this deviation. As used herein the term "non-volatile" will refer to the condition in which the adjusted resistance value remains substantially constant during periods of archival time, it is clear that software (including feedback system described below) can be employed to ensure that no displacement is present outside a selected margin of error. Due to the displacement of the resistance value of the memory elements, if it is not prevented, harm the gray scale storage of the information, it is desirable to minimize the displacement. The "composition modification" as defined herein includes any means for modifying the composition of the Volume of memory material to give substantially stable values of strength including the addition of expander elements between the webs to increase the inherent strength of the material. An example of composition modification is to include qualified composition inhomogeneities with respect to thickness, for example, the volume of the memory material can be classified from a first Te-Ge-Sb alloy to a second Te-Ge-Sb alloy. of different composition. The composition classification can have any shape that reduces the displacement of the adjusted resistance value. For example, the composition classification does not need to be limited to a first and a second alloy of the same alloy system. Also the classification can be achieved with more than two alloys. Classification can be uniform and continuous or it can also be non-uniform or non-continuous. A specific example of the composition classification of Ge14sb29TeS7 on one surface and Ge22Sb22Te5ß on the opposite surface. Another way to use composition modification to reduce resistance shifts is by layering the volume of memory material. This is the volume of the memory material can be formed of a plurality of relatively thin discrete layers of different composition. For example, the volume of the memory material may include one or more pairs of layers, each of which is formed of a different alloy of Te-Gb-Sb. Again, as was the case with the classified compositions, any composition of layers which results in a displacement of the reduced resistance value can be used. The layers may have the same thickness or different thickness. Any number of layers can be used and these multiple layers of the same alloy can be in the volume of the memory material, either continuously or away from each other. Layers of any number of different alloy compositions can also be used, a specific example of laying composition layers is a volume of memory material including pairs of alternative layers of Ge14Sb29TeS7 and Ge22Sb22Teß6. Another form of compositional lack of homogeneity to reduce resistance displacement is achieved by combining compositional classification and compositional layer formation. More particularly, the aforementioned compositional classification can be combined with any of the compositional layering described above to form a stable volume of memory material. Exemplary volumes of memory material employing this combination are: (1) a volume of memory material that includes a discrete layer of Ge22Sb22Te56 followed by a Gex classified composition «Sb29TeS7 and Ge22Sb22Teß and (2) a volume of memory material that includes a discrete layer of Ge14Sb29Te57 and a classified classification of Ge14Sb29Teß-- and Ge ^ b ^ Te ^.

Referring to Figure 1, a cross-sectional view of a memory element of the present invention formed in a single semiconductor crystal chip of silicon 10 is shown. The memory element 30 includes the memory material 36 and a pair of contacts placed separately 6 and 8, to feed the electrical input signal to the memory material. Each of the separate disposed contacts may consist of two layers of thin film. Layers 34 and 38 deposited adjacent to the mr-grain material have excellent diffusion barrier properties that inhibit the migration of foreign material in the chalcogenide memory material 36. Previously, in the Ovonic EEPROM, adjacent thin film layers 34 and 38 both consisted of amorphous carbon, amorphous silicon or a dual structure of amorphous carbon / amorphous silicon. In the present invention at least one of the thin film contact layers has been modified to a new material. The new material is formed of a compound that includes element selected from the group consisting of Ti, V, Cr, Zr, nb, M, Hf, Ta, W and two elements selected from the group consisting of B, C, N, O, Al , Si, P, S. In one embodiment at least one of the adjacent thin film contact layers consists of titanium carbonitride. Preferably, at least one of the thin film contact layers consists of a compound having a composition of, in atomic percent, between about 10 to 60% titanium, 5 to 50% carbon and 10 to 60% nitrogen. In addition, titanium carbonitride can include up to 40% hydrogen. In another embodiment, at least one of the adjacent thin film layers consists of titanium silico-tri- tride. Preferably in this embodiment at least one of the thin film layers consists of a compound having an atomic percentage composition of between about 10 to 60% titanium, 5 to 50% silicon and 10 to 60% nitrogen. The titanium carbonitride and the titanium siliconitrute have excellent barrier properties, preventing both diffusion and electromigration of foreign material in the chalcogenide memory material. The layers of titanium siliconitrute and titanium carbonitride can be deposited by methods such as physical vapor deposition including evaporation, ion plating as well as DC and RF sizzle deposition, chemical vapor deposition, and plasma assisted chemical vapor deposition. The exact method used depends on many factors, one of which are the deposition temperature restrictions imposed by the composition of the chalcogenide target material. The layers of titanium carbonitride or titanium siliconitride are preferably deposited at a thickness of about 100 to 2000 A. They are more preferably deposited with a thickness of about 200 to 1000A. The pair of contacts placed apart 6 and 8 preferably consist of the additional thin film layers 32 and 40 which are deposited away from the chalcogenide memory material. Each of these remote thin film layers consists of one or more elements consisting of Ti, W and Mo. In one embodiment each of the thin film layers consists of Ti and W. Preferably, the thin film layers consist of a compound, in atomic percentage of 5 to 30% titanium and 70 to 95% tungsten. The Ti-W alloy layers 32 and 40 are preferably deposited using a DC sizzle deposition process. they are preferably deposited with a thickness of about 100 to 4000A. They are deposited more preferably with a thickness of 200 to 2000A. Ti-W alloy layers 32 and 40 have excellent ohmic contact properties. In addition, they have the necessary barrier properties to prevent electromigration and diffusion of foreign electrode material in the chalcogenide memory material. The layer of memory material 36 is formed of a semiconductor material of multiple elements, such as the described chalcogenide material. The layer 36 can be deposited by methods such as sputtering, evaporation or by means of chemical vapor deposition (CVD), which can be improved by means of plasma techniques such as RF luminescence discharge. The chalcogenide memory materials of the present invention are more preferably made by means of RF sizzle and evaporation. The typical deposition parameters for the RF sizzle and evaporation of the chalcogenide layer 36 as shown in Tablets 2 and 3, respectively. Table 2 RF sizzle deposition parameters Technical parameter Base pressure 8xl0"7-lxl0" 6 Torr Sizzle gas pressure (Ar) 4-8 m Torr Sizzle power 40-60 W Frequency 13-14 Mhz Speed deposition 0.5-10 A / second Deposition time 2-25 minutes Film thickness 250-1500A Ambient temperature substrate-300 * C Table 3 Evaporation deposition parameters Parameter Typical interval Base pressure Ixl0"751xl0" 6 Torr Temperature evaporation 450-600ßC Deposition rate 2-4 A / second Deposition time 2-20 minutes Film thickness 250-1500A Ambient temperature of substrate-300 * C It is important to note that evaporated films deposited on a hot substrate have characteristics of anisotropic growth (see the description of figure 6) in which oriented layers of the chalcogenide elements are successively deposited. It has yet to be proven if this is important for electrical applications; however, this type of film promises thermoelectricity (due to the high thermal power already measured in these compositions, this is a factor of four greater than that measured for bismuth systems) or for specific applications of semiconductor or superconductivity. The layer of the memory material 36 is preferably deposited in a thickness of from about 200 A to 5000 A, more preferably from about 250 A to 2500 A and most preferably from about 400 to 1250 A thick. The term used herein "pore diameter" generally means the cross section of the smallest region of contact between the memory material 35, and the electrical contact layers 6 and 8. The pore diameter of the memory material 36 is less than approximately one or two micras approximately, although there is no practical limit in the lateral dimension. It has been determined that the diameter of the actual conductive path of the high conductivity material is significantly less than one diameter. The pore diameter can thus be as small as the lithographic resolution limits allow and in fact the lower the pore, the lower the power requirements for the electrical commutation. It is preferred that the pore diameter be selected such that it substantially conforms to the cross section of the memory material whose strength is currently disturbed when the material is switched to a high or low resistance state. The pore diameter of the memory material 36 is preferably less than about one such that the volume of the memory material 36 is limited, to the extent possible lithographically, that the volume of the material 36 that is actually switched between the different states reference. This also reduces the switching time and electrical power required to initiate the detectable load on the resistor. Ideally, the pore diameter should be equal to the diameter of the filament formed when the commutation material is in the dynamic state. It is further preferred that the pore region of the memory element 30 be insulated and / or thermally controlled except by the electrical contact with the upper and lower electrodes that are necessary for the proper operation. This confines, limits and controls the transfer of heat from the commuted volume of the pore as well as the electrical energy required for the resistance transitions. Such a thermal insulator is achieved in the embodiment of FIG. 1 by the insulating material 39 surrounding the lateral periphery of the memory element 30. We observe a tendency in the performance of the memory elements that is generally related to the pore diameter. When the device is used in a binary mode, we see a general increase in the resistance ratio from on to off as we test the devices through a pad in which the pore diameters are consistently in the range of one little more than one miera to closed completely. If the pore diameter is controlled within the range, for example from one meter to about one sixth, there is an importunity to improve the performance of our devices. Since factors such as current density and energy density are important for device programs, the reduction in the volume of the device, resulting in the reduction in pore diameter, should result in an increase in sensitivity and speed. To minimize the adjusted power / current / voltage ratio, pore diameters as small as 1500 A, or even as small as 100A can be used. The memory elements of the present invention employing filament confining means 48 between at least one of the separate contacts and the volume of the memory material provide memory elements with better thermal stability, less than current adjustment / readjustment requirements., greater life cycle and a greater dynamic range of resistances. In those memory elements, resistance switching appears to occur in a filament portion of the volume of the memory material and this portion of filament appears to be affected by the filament confining means. The filament confining means defines the size and position of the filament portion during the electrical formation of the memory element. The memory confining means also limits the size and confines the location of the filament portion during the use of the memory element, providing a high current density within the filamentary portion of a single-cell memory element afterwards. the entrance of a very low electric current to the contacts placed separately. Typically, the filament confining means means a thin layer of film placed between one of the separated contacts and the volume of the memory material, preferably this thin film layer has a thickness between 10 and 100 A. This thin film layer is It is a highly resistive material and has at least a low resistance path through it, through which electrical signals pass between the electrical contact and the volume of the memory material. The low resistance path area in the highly resistive thin film layer can be less than about 2 percent of the total area of contact between the thin film layer and the volume of the memory material. An exemplary thin layer is formed of a silicon nitride material that includes silicon, nitrogen and hydrogen. The composition of this film is preferably, in atomic percentage, between about 30-40% silicon, 40-505 nitrogen and up to 30% H. The filament confining means plays a role in the "electrical formation process" of the memory device. The process of electrical formation consists of applying pulses of high electrical current to a newly constructed memory element until the memory element changes its value from "virgin" resistance originally very high to a lower resistance value . Once this happens, the memory element is said to be formed. Now it is ready for the subsequent cycles of low electrical current. The forming process "breaks" the thin silicon nitride film layer of the filament confining means. The thin film layer of silicon nitride as deposited is highly resistive. During one or more of the larger current pulses applied during the formation process, the electrically weaker "break" reaction in the confinement layer physically changes and becomes much more conductive than the rest of the layer. It is through the region that the entire current of any subsequent memory cycle pulse will pass (this is adjustment pulses and readjustment). this current defines the size and position of the resistance switching filament portion of the memory material volume, since the rupture region does not move or grow during low current memory switching, acts to confine the location and the limit size of the resistance switching filament portion during the use of the memory element. When a very low current is applied to the memory element, all current is channeled through the filament portion. Therefore, due to its extremely small size, the current density is very high within this region of the memory material. The memory element shown in Figure 1 can be formed in a multi-stage process. The layers 32, 34 and 46 are first deposited and the insulating layer 46 is recorded to form the pore. The remaining layers 48, 36, 38 and 40 are deposited and the entire stack of layers 32, 34, 36, 46, 48, 48 and 40 are recorded to the selected dimension. Deposited in the upper part of the structure is a layer of insulating material 29 of Si02 or Si3N4. This is etched and the aluminum layer is deposited to form the second electrode grid structure 42 extending perpendicular to the conductors 12 and completing the grid connection X-Y to the individual memory elements. Covering the complete integrated structure is an upper encapsulating layer of a suitable encapsulant such as Si3N4 or a plastic material such as polyamide, which seals the structure against moisture and other external elements that could cause deterioration and degradation of performance. The Si3N4 encapsulant can be deposited for example using a plasma deposition process at a low temperature. The polyamide material can be deposited by centrifugation and baked after deposition according to known techniques to form the encapsulating layer. It is important to note that conventional CMOS technology can not use this type of three-dimensional memory arrays since CMOS technology forms the semiconductor devices required in the mass of a single-crystal semiconductor chip, and therefore can only be used to manufacture a Simple layer of devices. In addition (1) CMOS can not produce as small as a fingerprint (actual element dimension) to effectively produce large arrays with comparably low costs and (2) CMOS devices because they exist in a single plane can not be interconnected in the Z direction Therefore, CMOS devices can not be manufactured with the three-dimensional interconnection required for advanced parallel processing computers. The three-dimensional thin film memory arrangement structures of the present invention, on the other hand, are capable of both providing conventional serial information as well as processing parallel information. Parallel processing and therefore multidimensional memory array structures are required for the rapid performance of complete tasks such as model recognition, classification or associative learning, etc. Other uses for and description of parallel processes are presented in patent no. 5,159,661 that is assigned to the owner of the present application. With the integrated structure shown in the modality of figure 1; however, a completely vertical integrated memory structure can be formed, thus minimizing the area occupied on the substrate. This means that the density of the memory elements in the integrated circuit is limited only by the resolution capability of the lithography. The top view of a possible configuration of multiple memory elements is shown in Figure 2. As shown, the devices form an X-Y array of memory elements. The horizontal strips 12 represent the group X of an X-Y electrode grid to address the individual elements. The vertical strips 42 represent the group Y of lines. Other circuit configurations of the electrically erasable memory of the present invention are, for example, possible and feasible to implement. A particularly useful configuration is a multi-level tridi enisonal arrangement in which a plurality of planes of the memory or control elements and respective isolation devices are stacked one on top of the other. Each plane of the memory elements is positioned as a plurality of rows and columns of memory elements, allowing X-Y addressing. This stacking of planes in addition to increasing the storage density allows for an additional Z interconnect dimension. This arrangement is particularly useful for simulating a neural network for a truly intelligent computer. Each memory element is electrically isolated from the others using some type of insulating element. Figure 3 is a schematic diagram of the distribution of the memory device, showing that the electrical insulator can be achieved using diodes, the circuit comprises an XY grid, the memory elements being electrically interconnected in series with isolating diodes 26. The addressing lines 12 and 42 are connected to external addressing circuits in a manner well known to those skilled in the art. The purposes of the isolated elements is to allow each described memory element to be read and written without interfering with the information stored in adjacent or remote matrix memory elements. Figure 4 shows a portion of a simple semiconductor crystal substrate 50 with a memory array 51 of the present invention formed therein. Also formed on the same substrate 50 is an addressing matrix 52 which is suitably connected via integrated circuit connections 53 to the memory array 51. The addressing matrix 52 includes signal generating means that define and control the pulses. of adjustment and reading applied to the memory matrix 51. It is clear, the addressing matrix 52 can be applied to the memory matrix 51. It is clear that the addressing matrix 52 can be integrated with and formed simultaneously with the state memory matrix. solid 51. In semiconductor memories of the prior art and low switching energies appear to be necessary for most of their applications, at least one transistor and charge storage elements are required for each memory element. The formation of those memories in the form of an integrated circuit requires at least three connections along with other additional complexities that make up a certain minimum substrate regardless of how the integrated circuit is distributed. The integrated circuit configuration of the electrically-erasable memory of the present invention requires only two connections to each memory element and these can be realized in a vertical relationship with each other. In addition, each memory element, complete with diode isolation and the pair of contacts for the element, is completely integrated in such a way that a significantly higher bit density is possible. In fact, the memory of the present invention provides a bit density that is greater than that obtainable even in dynamic solid state random access memories (DRAMs), which are volatile and therefore do not have the other advantages that the non-volatiles provided by the present invention have. The growth in bit density obtainable with the present invention results in a corresponding reduction in manufacturing costs due to the smaller areas of the chip occupied per bit of the integrated circuit configuration. This enables the memory of the present invention to compete with and surpass other existing memories for a wider range of applications, not only in terms of electrical performance and memory storage capabilities, but also in terms of cost. In comparison with the semiconductor memories of the prior art formed of at least one transistor and one capacitor for each bit, the integrated circuit configurations of the present invention, as shown in FIG. 1, can be formed into a chip with a higher density of bits compared to the prior art configurations using the same lithographic resolution. In addition to the cost advantages that the higher bit density provides, the elements are placed close together and the wiring lengths are minimized, the capacitance and other related parameters are minimized also improving the performance. Experimentation has shown that the factors such as pore dimensions (diameter, thickness and volume), the chalcogenide composition, the thermal preparation (post-deposition fixation), pulse pulse duration, impurities such as oxygen present in the composition, Crystallite size and waveform of the signal pulses have an effect on the magnitude of the dynamic range of resistances, the absolute end resistances of the dynamic range, and the voltages required to adjust the device on those resistors. For example, relatively thick chalcogenide films (this is about 4000 A) will result in higher requirements of adjusted voltage (and therefore higher current densities within the volume of the memory material) while relatively thin chalcogenide layers (ie approximately 25? A) result in lower requirements for adjustment voltage (and current density). It is clear that the possible importance of the crystallite size and therefore the proportion of the number of surface atoms in relation to the number of atoms in the mass has been previously described. The duration of the signal pulse required to adjust the memory element to the desired resistance level within the dynamic range of electrical resistances will likewise depend on all the above factors as well as the current current level. Typically the duration of the signal pulses will be less than about 250 nanoseconds and preferably less than about 50 nanoseconds. It should be noted that even the short pulse widths of 25 nanoseconds depend on the size and shape of the pore as well as the thickness and composition of the semiconductor alloy used. It is believed that the pulse duration can be significantly reduced without interfering with the operation of the memory switch. Experimentation suggests that the entry of smaller amounts of energy will increase the life cycle of the elements. A feedback circuit that reads, and when required, adjusts the resistance of a given memory element can be incorporated into the memory system of the present invention, For example a memory element can initially be set to a desired resistance; however over time the resistance of the element may shift slightly from the value at which it was originally adjusted. The feedback loop in this case would equalize and issue a pulse of refresh signal of the voltage and duration required to the memory element to reassemble a preselection resistance value. Also, there may be circumstances in which the pulse conducted to a memory element may not result in the adjustment of the element to the desired resistance value. In this case the feedback loop will drive additional signal pulses to the element until the desired level is achieved. The total duration of this series of fixation / adjustment cycles is less than about 1000 nanoseconds and preferably less than about 500 nanoseconds. The ability to reversibly move up and down the linear portion of the resistance versus the current curve of the device can not be overemphasized. A pulse of a selected current can adjust the memory element to a desired resistance, regardless of its preconditions. This ability to move reversibly along the curve provides direct overwriting of previously stored data. This direct overwrite capability is not possible with the phase change and memory materials MSM (a-Si) of the prior art, this ability to reversibly adjust the intermediate resistance values is to note -.e. One thousand pulses of successive medium current achieve the same resistance value as a higher current pulse followed by a simple average current pulse or a lower current pulse followed by a single medium current pulse. The dynamic range of resistors also allows the storage of a large gray scale and multi-level analog memory. Multi-level memory storage is achieved by dividing the wide dynamic range into a plurality of sub-intervals or levels. The continuous resistance programmability allows multiple bits of binary information to be stored in a single memory cell. This multi-level storage is achieved by imitating multiple bits of binary information in pseudo-analog form and storing this information in a single memory cell. Thus, by dividing the dynamic range of resistors into analog levels 2n, each memory cell will be provided with the capacity to store n bits of binary information. As indicated above, Figure 5 is a ternary diagram of the Ge-Te-Sb semiconductor alloy system. In addition to the information previously described, which binary and ternary phases are indicated by tables (.), This diagram gives information on the segregation of other alloys. These other alloys are indicated by triangles (*), diamonds (*) and circles (•) and phases in which the alloys may segregate after rapid solidification of the melt are indicated by the lines (solid or dotted) extending from he. The initial compositions of the two Te-rich melts are indicated by circular symbols in the ternary diagram. After rapid soldering, those phases of mixtures segregate in Te elemental plus phases B, C and D. Melts with compositions to the right of the pseudobinary line, indicated with the diamond symbols, solidify in the phases indicated by the lines in the diagram. Other mixtures indicated by triangles in the phase diagram solidify in elementary Ge and Sb and in phase A. An alloy of particular interest for use in the improved memory elements of the present invention is Ge22Sb22Te56 also referred to as Ge2Sb2Tes or 2-2- 5. this alloy 2-2-5, after rapid solidification, segregates the phase in a mixture of two different phases of the compositions B (Ge26SblßTe56) and C (Ge ^ b ^ Te ^) indicated in the phase diagram of the figure 6. Another alloy of particular interest is Ge14Sb29Te57 (also referred to as Gbsb2Te2 or 1-2-4) which is composition D in the pseudo-binary line GeTe-Sb2Te3. The alloys 2-2-5 and 1-24 are of interest to form the volume of the memory material in compositionally classified form, layered or combined classified / layered, as described above. Figure 6 shows the atomic structure of three ternary alloys of the Ge-Sb-Te system as well as the atomic structure of the Ge-Te binary alloy. Two of the three ternary alloys are compositions 1-2-4 (composition D in the ternary diagram of figure 6) and 2-25 described above. The third ternary alloy is Ge8Sb33TeS9 which is also called GeSb4Te7 or 1-4-7. This alloy 1-4-7 corresponds to composition E in the ternary phase diagram of Figure 5. In the representations of the atomic structures of these alloys, the hollow circles represent Ge atoms, the fluted circles represent Sb atoms and the dotted circles show Te atoms. As shown in figure 6, the atomic configuration of each of the alloys, when it has the crystal structure cubes entry into the faces, in the form of repeated ordered layers of atoms. The fcc configuration forms three different types of layers that are labeled A, B and C in Figure 6. The alloys 1-4-7, 1-2-4 and 2-2-5 shown in Figure 6 are of interest as base memory materials and for use in the elementally modified memory materials of the present invention. The transition metals together with Se, when present, are incorporated relatively uniformly into the Te-Ge-Sb matrix and improve the electronic / atomic structure to produce the reduced switching current requirements and increase the theoretical stability of the retention of data. The current analysis shows that the Te is replaced in the structure and although the placement of the transition metal is not known, it seems that the transition metal bonds with the chalcogen element. Also as mentioned before, the Ge-Sb-Te alloy materials are deposited by means of evaporation on the hot substrate, the materials are deposited in anisotropic form. This is when deposited in this manner the crystals of alloy materials are oriented in such a way that the layers of the constituent atomic elements are aligned substantially parallel to the surface of the substrate. This will result in an anisotropic current flow, but offers the long-term possibility of arranging the atoms of the material to employ and readjust the pulses in the low resistance direction and thus achieve lower currents, voltages and / or adjustment and readjustment energy. . Figure 7 is a graphical sample of the data illustrating the cycle characteristics of a memory element with a top adjacent contact layer consisting of titanium carbonitride. The resistance of the device is shown in the ordinate and the cycle number is plotted in the abscissa. To go from a state of low resistance (state of adjustment) to a state of high resistance (state of readjustment) an electrical pulse with a height of approximately 2 mA and a width of approximately 40 ns is applied to the memory device. To return to the low resistance state, a pulse of a height of approximately 1 ma and a width of approximately 100 ns is applied to the device. thus, by applying a series of pulses with an appropriate height and width, the device can be used in cycles as shown. Figure 8 is a graphical representation of the data illustrating the characteristics of the cycles of a memory element with an adjacent contact layer consisting of titanium siliconitride. To go from a low resistance state (adjusted state) to a high resistance state (reset state), an electrical pulse of approximately 2 mA and a width of approximately 40 ns is applied to the memory device. To return to the low resistance state, a pulse with a height of approximately 1 mA is applied and a width of approximately 100 ns is applied to the device. Figure 9 is a graphical representation of data illustrating multistate capabilities (this is the ability of the memory element to be set at any of a plurality of resistance levels within the dynamic range of resistors) of a memory element of the present invention. The data shows that a memory device has an adjacent upper contact layer 38 consisting of titanium carbonitride. The graph is made when programming the memory device to increase the resistance values. This is achieved by applying electrical pulses of 40 ns of increasing program currents. Fig. 10 is a graphical representation of the data showing the average of adjusted and readjusted resistors for the memory elements having titanium carbonitride as the adjacent upper contact layer. The adjustment and readjustment resistances were determined using layers of titanium carbonitride with four different resistivities. The resistivity increased as the percentage of carbon in the titanium carbonitride compound grew. As shown, the differences between the adjustment and readjustment resistances increases with increasing resistivity of titanium carbonitride. There is a threshold switching value associated with the programming of the Ovonic EEPROM, and therefore it would be expected that like the threshold switches, the programming voltage of the Ovonic EEPROM would show a dependency on the thickness of the chalcogenide alloy film. In fact, in the Ovonic EEPROM, n threshold switching voltage serves to read separately from programming events, eliminating read shift and providing a good operating margin during data reading, our devices show linear resistance characteristics when the applied field is low, followed by a gradual reduction in resistance with a rising field up to the voltage value. Once the voltage value has been exceeded, the device presents a negative resistance transition to a highly conductive "dynamic" state. When the applied field is removed, the device returns to its programmed non-volatile resistance state, the value of which depends on the current / energy profile that the device has experienced during its "memory balance time" while in the dynamic state . Although the threshold voltage depends on the resistance of the device, the current of the device in the current voltage is relatively constant for all the resistors of the device. A linear approximation to the thickness, the threshold voltage ratios shows a proportionally smaller factor than that contributed by a wide range of operating range in devices having the same nominal thickness. By the use of the proprietary materials and device configurations described herein, an electrically erasable, and directly writable memory element has been developed which provides fast read and write speeds, approaching those of SRAM1 devices, non-volatile reprogramming capability. random access of an EEPROM; and a price per megabyte of storage significantly below any semiconductor memory. It is to be understood that the present disclosure is presented in the form of detailed embodiments described for the purpose of making a full and complete presentation of the present invention, and that those details should not be construed as imitating the true scope of the invention as established and defined. in the appended claims.

Claims (7)

1. CLAIMS 1.- A simple multi-bit cell memory element with electrically operated direct overwrite that includes a volume of memory material characterized by (1) a large dynamic range of electrical resistance values, (2) the capacity of at least one filamented portion of the memory array that is set to one of a plurality of resistance values within the dynamic range in response to the selected input signals to provide the single-cell memory element with multi-bit storage capacity, and (3) the ability to adjust the filament portion to any resistance value in the dynamic range, regardless of the previous resistance value in the memory material, and a pair of contacts placed separately to deliver the electrical input signal to the memory material at a selected resistance value within the dynamic range, the improvement consisting in that: c One of the contacts placed separately includes a thin film contact layer deposited adjacent to the memory material in which at least one of the thin film contact layers includes one or more elements selected from the group consisting of Ti, V, Cr , Zr, Nb, Mo, Hf, Ta, W and mixtures or alloys thereof in combination with two or more elements selected from the group consisting of B, C, N, O, Al, Si, P, S and their mixtures or alloys
2. 2. The memory element according to claim 1, wherein the adjacent thin film contact layer includes Ti, and two or more elements selected from the group consisting of C, N, Al, Si and their mixtures or alloys. .
3. 3. The memory element according to claim 2, wherein the thin film contact layer includes Ti, C and N.
4. 4. The memory element according to claim 4, wherein the Adjacent thin film contact includes up to 40% hydrogen.
5. 5. The memory element according to claim 2, wherein the adjacent thin film contact layer includes Ti, Si and N.
6. 6. The memory element according to claim 1, wherein the improvement further consists in that: each of the contacts placed separately includes a thin film contact layer placed remotely to the memory material, wherein the thin film contact layer is composed of one or more elements selected from the group consisting of Ti, W, Mo and their mixtures or alloys.
7. 7. The memory element according to claim 6, wherein the adjacent thin film contact layer includes Ti, and W. BE-2IH-? H An electrically operated memory element (30) includes a volume of memory material (36) characterized by a large dynamic range of electrical resistance values; and the capacity of at least one portion of filament that is adjusted by means of the selected electrical signal at any resistance value in the dynamic range, regardless of the previous resistance value of the material to provide a single cell with storage capacity for multiple bits. The memory element 930) also includes a pair of contacts (6, 8) includes (1) a thin film layer (34, 38) preferably titanium carbonitride or titanium siliconitride, disposed adjacent to the memory material (36) used as a diffusion barrier to inhibit the entry of foreign material into the memory material (36), and (2) a thin film layer (32, 40), preferably a Ti-W alloy, placed remote disposed to the used memory material to provide a barrier to electromigration, aluminum diffusion and provide ohmic contact at the aluminum interface.