MXPA99000911A - Data de-rotator and de-interleaver - Google Patents

Abstract

An apparatus (28) for de-rotating and de-interleaving data includes (i) a first memory (32) for storing D elements of rotated and interleaved data in D storage locations, (ii) a first addresser (36) for addressing the first memory (32) in order to read de-rotated and interleaved data out of the D storage locations and to write rotated and interleaved data into the D storage locations, (iii) a second memory (38) for storing mD elements of the de-rotated and interleaved data read out of the first memory (32), wherein the de-rotated and interleaved data read out of the first memory (32) are stored in mD storage locations of the second memory (38), and (iv) a second addresser (40) for addressing the second memory (38) in order to read de-rotated and de-interleaved data out of the mD storage locations and to write de-rotated and interleaved data from the first memory (32) into the mD storage locations.

Description

G06F 1200, 13/00, H03M 7/00, H04N Al 7/015 ROTATION DETERMINATOR AND DATA DETERTER Technical Field of the Invention > The present invention relates to an apparatus and method for eliminating the rotation of and / or demeasuring data- Background of the Invention In a ground communication system VSB 8, the information can be transmitted to a receiving station at klO through the air. In an example of such a system, every two bits of data to be communicated are converted into a three-bit trellis code, which is mapped as a symbol having 8 possible levels, so that each byte of data is represented by four symbols. The symbols are interleaved, and some of the symbols are rotated before they are transmitted in data blocks. A block of data that is used in a VSBT 8 system is described in the ATSC Digital Television Standard (published September 16, 1995), and particularly in Annex D, section 4.1 thereof. This data block is comprised of a plurality of segments (ie, lines), wherein each segment contains groups of data, and wherein each group of data includes a plurality of data elements. For example, each segment can contain 25 sixty 'and nine data groups, each group of data can REF: -29205 include twelve data elements, and a data element can be a data symbol. The first segment of such data block contains block synchronization information, and ™ each subsequent segment in the data block has an initial portion containing segment synchronization information (in the form of four segment synchronization symbols) , and a successive portion that contains data. Due to the synchronization information of the segment kl-0 and the block contained in a data block, the data elements in certain groups of the data can be rotated in order to facilitate processing of the data by the receiver. This rotation is described in Annex D, section 4.2.5, and in Table 2 of the Standard mentioned above. Therefore, the rotated and interleaved data received by a receiver must be without "rotation, and deinterleaving" The present invention is directed to an apparatus for eliminating rotation and / or deinterleaving data elements, such as symbols.

BRIEF DESCRIPTION OF THE INVENTION In accordance with one aspect of the present invention, an apparatus for processing rotated and interleaved data, comprised means of elimination of rotation and means of deintercalation. The means of eliminating the rotation, eliminate the rotation of the data rotated and interspersed, in order to produce data without rotation and interleaved. The de-interleaving means de-interleave the data without rotation and interleaved, in order to produce data without rotation and deinterleaved. According to another aspect of the present invention, an apparatus for processing rotated and interleaved data comprises first and second storage means, and first and second addressing means. The first storage medium stores D elements of the data rotated and interspersed. The first addressing means directs the first storage means in order to read the data without rotation and interleaved, outside the first storage means, and writes the data rotated and interleaved in the first storage means. The second storage means stores nD data elements without rotation and interleaved, read out of the first storage means. The second addressing means directs the second storage means, in order to read the data without rotation and deinterleaving, out of the second storage means, and 'writes the data without rotation and interleaving the first storage means into the second storage medium. storage.

In accordance with yet another aspect of the present invention, an apparatus is arranged to eliminate rotation of rotated data. The data rotated are rotated in? base to D data elements. The apparatus comprises means storage and means of diECcionamiento. The storage means store D data elements of the data rotated, in D corresponding storage locations. The addressing means directs the storage means in order to read the data without rotate out of the D storage locations, and write the data rotated in the D storage locations.

BRIEF DESCRIPTION OF THE DRAWINGS These and other features and advantages of the present invention will become more apparent from the "detailed consideration of the invention, when taken in conjunction with the drawings, in which: Figure 1 illustrates a example of data in a row increasing order and is useful in explaining the interleaving of the data to be demystified by the present invention, Figure 2 illustrates an example of the data and is useful in explaining the rotation of the data from which the rotation is to be eliminated, by the present invention: Figure 3 illustrates an apparatus for eliminating rotation and demodulator, according to the present invention; > Figure 4 is a timing diagram for the demodulator 30 of Figure 3; Figure 5 is a timing diagram for the controller 34 of Figure 3; Figure 6 illustrates the address generator 36 of Figure 3, in further detail; .10 Figure 7 illustrates an example of the data, which is useful in explaining the operation of the address generator 35 illustrated in Figure 6; Figure 8 illustrates an embodiment of the address generator 40 of Figure 3, in further detail; Figure 9 represents the memory locations of the second memory means 38; Figure 10 illustrates the direction sequences produced by the address generator 40 of Figure 3; Figures HA and 11B are timing diagrams for the address generator 40 of Figure 3; Figure 12 illustrates a first embodiment of the core generator 82, of Figure 8, in further detail; Figure 13 illustrates a second embodiment of the core generator 82, of Figure 8, in further detail; > Figure 14 illustrates the multiplication operator 5 times twelve, and module forty-seven, 98, of Figure 13, in further detail; Figure 15 illustrates the module correction logic forty-seven, 106, of Figure 14, in further detail; and, Figure 16 illustrates another embodiment of the address generator 40, of Figure 3, in further detail.

Detailed Description Figure 1 illustrates a plurality of bytes of data elements, which have resulted from the exploration of a part of a scene. The first byte of f data contains the data symbols A ,, A-, A;, and Ai. Each of these data symbols can represent, for example, two data bits. The first byte of symbols of data, therefore, represents eight data bits. The second data byte contains the data symbols B-L - B "the third data byte contains the data symbols Ci - C, ..., and the twelfth data byte contains the data symbols Li - L ".

A symbol interleaver in a transmitter may be configured to intersperse the data symbols of the Figure 1, although any other arrangement can be interleaved? data symbols or data elements. Therefore, the The symbol interleaver converts the data symbols illustrated in FIG. 1, from an increasing array in a row, to an increasing array in a column, so that the data symbols are transmitted as data elements arranged in an increasing order, in a column. Consequently, in Instead of the transmitter transmitting the data symbol K, after the data symbol A-, the data symbol A (after the data symbol A, -, the data symbol A - after the data symbol A- , the data symbol Bi after the data symbol A--, and so on, the transmitter (ignoring another processing, which can change the order of the data symbols), transmits in sequence the data symbol Ai, the data symbol f B -, ..., the data symbol Lj, the data symbol J,. ... Thus, each column of data symbol as shown in Figure 1, represents a group of twelve elements of data, so that the first column is transmitted first, the second column is transmitted second, and so on. Figure 2 shows a group of the data symbols in a segment 20 of a data block. As shown in the Figure 2., the group of data symbols - in this group of Data symbols, in segment 20, are not rotated. However, other groups of data symbols in segment 20, or in other segments, may be rotated. For example, ™ data symbols in a group of data symbols in a segment 22, have been rotated by eight, and the data symbols in a group of data symbols in a segment 24, have been rotated by four. { although in the embodiment of the present invention described below, it is assumed that the transmitter does not rotate the data by four). Thus, the data symbols ^ 0 shown in Figures 1 and 2, are then transmitted as interleaved and rotated data. Figure 3 illustrates an apparatus 28 for eliminating rotation and deinterleaving the interleaved and rotated data. The apparatus 28 includes a demodulator 30 (such as a demodulator) ATSC 8 VSB). The demodulator 30 receives a signal from the terrestrial mode VSB 8 standard ATSC, and produces the following four "output signals: a block synchronization signal, which occurs at the end of the block synchronization segment, a segment synchronization signal, which occurs coincident with the first symbol clock of each data segment; symbol clock and interleaved and rotated data The interleaved and rotated data is supplied to a first memory 32. There are 312 segment synchronization signals produced by each block, but there is no segment synchronization created by the segment of the block. block synchronization. There are 828 symbol clocks produced by each data segment, and each symbol clock is coincident with a corresponding data symbol. Without However, there are no symbol clocks created during either the 5 time corresponding to the synchronization segment of the block or the time corresponding to the four synchronization symbols of the segment of a segment synchronization. Therefore, the symbol clocks only exist in correspondence to the data symbols. Figure 4 is a synchronization diagram illustrating the outputs of the demodulator 30. The block synchronization signal, the segment synchronization signal, and the symbol clock signal are supplied to a controller 34, and the controller 34 produces the following five output signals: a segment account signal; a group account signal; two signs of W reset, RESET 1 and RESET 2; and, a byte clock signal. The segment account signal is the output of a counter that divides by four, which is reset to zero, by the coincidence of the block synchronization signals and segment synchronization. Therefore, it is incremented by each segment synchronization signal, which causes the segment account signal to cycle through the 0, 1, 2, 3 0, 1, 2, 3 accounts ... Because there are 312 signs segment synchronization per block, and because 312 is divisible by four, the value of the segment account corresponding to the last segment of the block will be 3. Therefore, the second count signal forms a cycle through its four values, 78 times (312/4) per block. The group account signal is the output of a counter that counts groups of twelve symbol clocks. The group count signal is increased by one when the twelve symbol clocks have occurred. Restarts to zero by coincidence of the segment synchronization signal, and the symbol clock signal. Because there are 828 symbols per segment, and because 828/12 = 69, the group account signal will cycle from 0 to 68 during each data segment. Thus, the output of the group account signal, forms a cycle through the accounts 0, 1, ... 68, 0, 1 ... 68, 0 .... The signal of REIN1CI0 1, is derived of the block synchronization signal. The KEINICIO 2 signal is a delayed version of twelve symbol clocks, of the RESET signal 1. The byte clock signal is generated every fourth symbol clock. Figure 5 is a timing diagram illustrating the outputs of the controller 34. The segment count signal, the group count signal, the symbol clock signal, and the RESET signal 1, are supplied to a first address generator 36, which provides the addresses to the first memory 32. Consequently, in response to the segment account signal, the group count signal, the symbol clock signal, and the RESET signal 1 of the controller 34, the address generator 36 reads from the first memory 32, a group of data without > rotation and interleaving, and writes in the first memory 32, a group of data rotated and interleaved, to replace the group of data that has been read. In the previous example, where a data group includes twelve data symbols, and where each data symbol represents two bits of information, the first memory 32 is a memory of twelve symbols. Thus, in response to the segment count signal, the g-rupe account signal, the symbol clock signal, and the RESET 1 signal, the address generator 36 reads from the first memory 32, twelve symbols of data without rotation and interleaved, and writes in the first memory 32, twelve data symbols rotated and interspersed, to replace the twelve data symbols that were read. More specifically, in response to a first symbol clock pulse, the address generator 36 reads "from a first storage location of the first memory 32, a first data symbol, and writes in the first storage location of the first memory 32, a data symbol to replace the first data symbol, which was read. In response to a second symbol clock pulse, the address generator 36 increments its output address by one, reads 25 from a second memory location of the first memory 32, a second data symbol, and write in the second storage location of the first memory 32, a data symbol to replace the second data symbol that is "read, and so on until all twelve data symbols in a group have been read and replaced.The addresses that are supplied by the first address generator 36 to the first memory 32, are arranged to eliminate the rotation of the rotated data symbols, stored in the first memory 32. Elimination of rotated data rotated, ^ 10 stored in the first memory 32, is explained in more detail in relation to Figure 6. Accordingly, the data supplied to the output of the first memory 32, are without rotation, but are still interleaved. A second memory 38 and a second address generator 40, are provided in order to de-interleave the data without rotation, but still The signal clock signal symbol 30 and the RESET signal 2 of the control 34 are provided to the address generator 40. In response to the symbol clock signal, the second address generator 40, generates addresses for the second memory 38, so that each address causes one of the data symbols stored in a corresponding storage location of the second memory 38 to "read and make a data symbol of the first memory 32". , write in that storage location of the second memory 38, to replace the data symbol that was just read, and so on. Based on the directions generated by the W second address generator 40, the data without rotation but interleaved, stored in the second memory 38, are read as data without rotation and deinterleaved. These data without rotation and deinterleaving, are supplied to a serial converter in parallel 42, which receives each data symbol of two bits, of the second memory 38, and converts J-0 the bits of four data symbols, to an eight-bit byte in parallel, in response to the byte clock of the controller 34. The first address generator 36 of Figure 3 is shown in more detail in Figure 6 . The first address generator 36 includes an address counter 50, a compensation generator 52, and a module adder W twelve, 54. The address counter 50 counts twelve symbol clocks and then restarts. The output of the address counter 50, therefore, varies from zero to eleven, and then 20 is reset to zero. The compensation generator 52 responds to the group count signal and the segment count signal of the controller 34, in order to generate a compensation (which can alternatively be referred to as a core). The module adder twelve 54, adds the count of 25 the output of the address counter 50, and the compensation of the compensation generator 52, in order to generate an address, which is supplied to the first memory 32. The compensation generator 52 may simply be a 'set of standard logical elements, which are configured according to the equations shown in the Figure 6. Alternately, the compensation generator 52 may include a read-only memory, and an address decoder, which decodes the group account and segment account signals, in order to have access to ^ LO certain memory locations, in the read-only memory, for the offsets to be supplied to the twelve-module adder 54. Figure 6 provides an example of the offsets, which can be generated by the generator Offsets 52. These offsets are based on the following rotation protocol (see the ATSC Digital Television Standard mentioned above), implemented by a transmitter: (i) the data symbols in the first segment of each set of four segments do not are rotated; (ii) the data symbols in groups 0, 1 and 2, of the second segment in each set of four segments, are rotated by eight, and the other groups of data symbols in this segment are not rotated; (iii) the data symbols in groups 0 and 1 of the third segment in each set of four segments, are rotated by eight, and the data symbols in the other data groups in this segment are not rotated; and (iv) the data symbols in group 0 of the fourth segment in each set of four segments are rotated by eight, and the data symbols in the other data groups in this segment are not rotated. Thus, the rotation protocol is repeated every four segments, and only certain groups of data in certain segments are rotated. Therefore, because the first segment WHAT in each set of four segments (which corresponds to K a segment account of zero), not rotated, the compensation generator 52 provides an output compensation of zero, for the first segment in each set of four segments. This output compensation of zero is added by the module adder twelve 54, to twelve output accounts, of the address counter 50, in order to generate twelve addresses to read twelve data symbols of the first memory 32, and write twelve new data symbols in the first memory 32. 20 When the segment account is one, and the group account is zero (that is, the first group of twelve data symbols, which is in the second segment in each set of four segments, and which is rotated by eight), the compensation generator 52 provides a output compensation of zero. This output compensation of zero is added by the module adder twelve 54, to twelve-account counter address 50, in order to generate twelve addresses to read twelve data symbols of the first memory 32. When the segment account is one , and the group account is one (that is, the second group of twelve data symbols, which is in the second segment in each set of four segments, and which was rotated by eight), the compensation generator 52 it provides an output compensation of eight. This output compensation of eightis added in a twelve module fashion, by the module adder twelve 54, to twelve exit accounts of the address counter 50 in order to generate twelve addresses to read twelve data symbols of the first memory 32. When the account of the segment is one, and the group account is two (that is, the third group of twelve data symbols, which is in the second segment in each set of four segments, and which is rotated by eight), the generator of compensation provides an output compensation of four, which is added in a manner of module twelve by the module adder twelve 54, to twelve output accounts of the output counter 50, in order to generate twelve directions to read twelve symbols Data from the first memory 32. When the segment account is one and the group account is three to sixty-eight, the compensation generator provides an output compensation of zero, which is sum in a way of module twelve, by module adder twelve 54, to sets of twelve exit accounts of address counter 50, in order to generate sets? corresponding twelve directions to read sets corresponding to twelve data symbols of the first memory 32. When the segment account is two and the group account is zero (ie, the first group of twelve data symbols in the third segment in each set of four ? 0 segments), the compensation generator 52 provides an output compensation of zero, which is added by the module adder twelve 54, to twelve output accounts of the address counter 50, in order to generate twelve directions to read twelve data symbols of the first 15 memory 32. When the number of the segment is two, and the account of the group is one (that is, the second group of twelve data symbols f in the second segment in each set of four segments), the compensation generator 52 provides an output compensation of eight, which is added in a way 20 of module twelve, by the module adder twelve 54, to twelve output accounts of the address counter 50, in order to generate twelve addresses to read twelve data symbols of the first memory 32. When the segment account is two and the group account is two to sixty-eight, the compensation generator provides a compensation of output of four, which is added in a manner of module twelve, by the module adder twelve 54, to sets of twelve output accounts of the address counter 50, in order to > generate corresponding sets of twelve addresses for 5 read corresponding sets of twelve data symbols of the first memory 32. When the account of the segment is three and the group account is zero (ie, the first group of twelve data symbols in the fourth segment in each set of four segments), the compensation generator 52 provides a > output compensation of four, which is added in a module manner 12, by the module adder twelve 54, to twelve output accounts of the address counter 50, in order to generate twelve directions to read twelve data symbols of the first memory 32. When the segment account is three and the group account is one up to sixty-eight, the output generator provides an output compensation of zero, which is added by the twelve-module adder 54, to sets of twelve exit accounts of the address counter 50, with the to generate corresponding sets of twelve addresses to read corresponding sets of twelve data symbols of the first memory 32. Figure 7 illustrates an example of how the address generator 36 operates in cooperation with the first memory. 32, in order to eliminate the rotation of the data rotated and interleaved of the demodulator 30. When the data in the last group of the zero segment have been stored in the first memory 32, this data is stored in the storage locations of the first memory 32, in the order of data shown by the row 60. These data are not rotated. Row 62 contains the first group of data from segment one, which has now been received by demodulator 30. These data are rotated by eight, as indicated by row 62. Because the segment account I is one and the group account is zero at this time, the compensation that is applied by the compensation generator 52 to the module adder twelve 54, is zero. Consequently, the addresses provided by the module adder twelve 54, are in order the output accounts supplied by the address counter 50. Thus, the module adder twelve 54, supplies a 'zero address to the memory 32, in order to read the data symbol A of the row 60 of the zero storage location of the first memory 32, and in order to write the data symbol E of row 62, in the zero storage location of the first memory 32. The module adder twelve 54, then supplies an address of one to the memory 32, in order to read the symbol of data B of row 60 of storage location one of the first memory 32, and in order to write the symbol data F of row 62 in the memory location one of the first memory 32. The addresses supplied by the module adder twelve 54, are incremented in order to > eleven, so that the data symbols of the row 60 are read from the first memory 32 and replaced by the corresponding data symbols of the row 62. Accordingly, the row 64 indicates the contents of the first memory 32, when the row 62 has been written in the first memory 32. At this point, the segment account is one, and the The group count is incremented to one, and the next group of f data symbols, as shown in row 66, are received by the demodulator 30. When this data is received, the compensation generator 52 generates a compensation of eight. , which is supplied to the adder of module twelve 54. Accordingly, the module adder twelve 54, adds the compensation of eight to the first exit account of cer-o, of the address counter 50, to generate an address of eight. In response to an address of eight, the data symbol A stored in the location of Eight storage of the first memory 32 (see row 64), is read and replaced by the first data symbol received from group one, ie, the data symbol E of the row 66. Similarly, the symbol of data B is read and replaced by the data symbol F when the address is nine (Compensation of eight plus one account of one), the Data symbol C is read and replaced by the data symbol G, when the address is ten (compensation of eight plus a count of two), the data symbol D is read and V replaced by the data symbol H, when the address is eleven (compensation of eight plus one count of three), the data symbol E is read and replaced by the data symbol I, when the address is zero (compensation of eight plus a count of four, which produces an address zero after the operation of module twelve), and so on successively, so that row 68 of Figure 1 indicates the data symbols now stored at zero to eleven storage locations of the first memory 32. The row 70 indicates the next group of data that is received, that is, when the account of the segment is one and the account of the group is two. When the segment account is * one and the group account is two, the compensation generator 52 generates a compensation of four. This compensation of four is added by the module adder twelve 54, to the output accounts supplied by the address counter 50, in order to generate the addresses for the first memory 32. As the data in the row 70 is received, the module adder twelve 54, adds the compensation from four to the first exit account of zero, of the address counter 50, to generate a direction of four. In response to a four address, the data symbol A stored in the storage location four of the first memory 32 (see row 68) is read and replaced by the first data symbol received from group two, i.e. data symbol E of row 70. Similarly, data symbol B is read and replaced by data symbol F when the address is five (compensation of four plus one count of one), data symbol C it is read and replaced by the data symbol G, when the address is six (compensation of four plus an account of two), the data symbol D is read and replaced by the data symbol H when the address is seven ( compensation of four plus an account of three), the data symbol E is read and replaced by the data symbol I, when the address is eight (core of four plus a count of four), and so on, so that row 72 of Figure 7 indicates the symbols d data now stored in zero storage locations up to eleven of the first memory 32. It is noted that when the output count of the address counter 50 reaches eight, the module adder twelve 54, provides an address of zero (one count of eight more a compensation of four, followed by the operation of module twelve), to the first memory 32. The row 74 indicates that the data of segment one, group three, are without rotation. So, with a compensation of zero, the contents of the first memory 32 as shown by the row 72, is replaced by the received data symbols shown in the row 74, so that the i content of the memory 32 is as shown in row 5 72 , after the data of segment one, group three, are completely stored in the first memory 32. As the data is read from the first memory 32, the data is without rotation, but still interleaved. These data without rotation but interleaved, are processed by JO the second memory 38, and the second address generator 40, in order to de-interleave the data without rotation but interleaved. Because the data symbols in each data byte are interspersed with the corresponding data symbols in another eleven bytes of data, and because there are four symbols per byte, the second memory 38 is a memory of 48 symbols. A first embodiment of the address generator 40 is illustrated in Figure 8. This address generator includes a division counter by forty-eight 80, the which provides any output in each forty-eight account of the symbol clock. The drag output of the division counter by forty-eight 80 is supplied to a core generator 82, and the core generator 82 supplies a core to a first input of an adder 84.

The output of adder 84 is supplied to an operator of module forty-seven 86, which performs a forty-seven module operation at the output of the adder 84- The module operator output forty-eight 86, connects P to the holding circuit 88, which retains the output of the module operator forty-seven 86, ba or the symbol clock control. The output of the retention circuit 88 provides an address to the second memory 38, and is also fed back to the second input of the adder 84. The second memory 38 must have sufficient 0 storage locations to store forty-eight symbols. Although the second memory 38 is a linear memory array, with storage locations marked from 0 to 47, it can be thought of as a rectangular array with R = 12 rows and C = 4 columns. Therefore, N = RxC = 48. The Figure 9 illustrates the directions of the second memory 38, seen in this way. If Xn is a sequence of symbols of? input (where n = 0 .... 47), and if M_ (n) represents a map of the input symbols x "to the memory locations in the second memory 38, M (n) is the address in the second 20 memory 38, where a corresponding symbol x "is to be stored. (The mapping M (n) has a subscript i because there are a number of maps, that is, a number of address sequences supplied by the second address generator 40). If the initial mapping sequence M0 (n) is chosen so that M0 (n) = n for n = 0, 1, 2 (N-l), each input symbol x "in the first block of forty-eight symbols, it is stored in memory location n. This can be visualized by overlaying Figure 1 in the part > FIG. 9. In order to de-interleave this data block, it must be read from the second memory 38, in a different order from the order in which it was written in the second memory 38. Thus, according to the following block of FIG. forty-eight symbols receives one symbol at a time, the symbols of the first block .10 are read from the second memory 38, and are replaced by the corresponding symbols barely received by the second block. To de-interleave the first block, Mt (n) must be - 0, 12, 24, 36, 1, 13 35, 47. The de-interleaving of the first block of symbols according to In these directions, it causes the second block to be written to the second memory 38 in a different order than that which is 'wrote the first block. Therefore, to de-interleave the second block (while simultaneously writing the third block in the second memory 38), a new addressing sequence M (n), which is different from Mi (n). This process continues through a series of addressing sequences, to receive and de-interleave blocks of symbols continuously. If the first mapping sequence is Mo (n) = 0, 1, 2, 3, 4 ....'... 47, then _ (n) can be written as 2 M, (>?) = M0 ((n »R) mod (N - \)) for n = O .... N - l (1) This expression arises because the interleaving depth is R. The adjacent horizontal symbols are separated by R units in the mapping function. The module portion appropriately controls the winding of the end of the line, and causes the appropriate compensation, as the index explores through the mapping function. Similarly, the mapping of any sequence can be generated from the previous mapping, according to the following 0 equation: M, (n) = M, t, ((n »R) moá <(N - S)) for n = 0,1-2, ..... N - 1 (2) Equivalently, using induction, this function of mapping can be generalized to express the nth entry in the first sequence using the initial sequence (i = 0) > as follows: M, (rí) = M "((.? •? ') Mod (-V - 1)) for n = 0,1,2, .....- V - 1. (3) Assuming that the initial sequence is Mo (n) = n, equation (3) can be simplified as follows: M, («) = M" (n »R ') mod (/ V-l) for n = 0,1,2, ...., -V - 1 (4) Equation (4) leads to an expression for the calculation of the nth entry in any sequence -from the nth entry in the preceding sequence as follows: > 5 -VI (.?) = (?, - 1 (n) »?) Mo (? -l)) fara« = 0,1,2 ,, .., -V-l. (5) Equation (4) describes all the addressing sequences that are necessary to de-interleave the input data from one block to the next. There is a finite klO number of different addressing sequences that equation (4) produces, before returning to the initial sequence. This finite number of sequences depends on the values of R and C (or equivalently, the values of R and N). Therefore, there are L unique mappings, where L is the lowest number, so that: (L) mod (-V - 1) = 1 for L different from O. (6) Finally, an expression that relates the nth entry in any sequence i to the (n-l) th entry, in that same sequence, can be established as follows: M. (n. = 0 for n = 0 (7) M, (n) = (M, (n -!) + «') Mod (-V - 1)) for n = 1,2, ... ., N - 1.

If R is 12 (as in the example shown in Figure 1), a value of 23 for L satisfies equation (6). That is, w equation (4) produces 23 unique sequences, which are repeat starting with L = 24. Therefore, for the data array shown in Figure 1, there are 23 sequences, which are required in order to de-interleave the data that is interleaved as described above in relation to Figure 1. Figure 10 JO shows the twenty-three sequences and their corresponding nuclei. The equations (7) are the basis for the address generator 40, in order to generate the repeating address sequences required. It also requires a generator of nuclei, which incorporates equation (6), in order to generate the nucleus for each direction sequence. ? The cores, which are generated by the generator of cores 82, are given by the equation (6 !, where L varies from 0 to 22, in the example given, in this patent application. These nuclei consist of the following; 1, 12, 3, 36, 9, 14, 27, 42, 34, 32, 8, 2, 24, 6, , 18, 28, 7, 37, 21, 17, 16, and 4. On every forty-eight symbol clock pulse, the core generator 82 supplies a corresponding one of these cores to the adder 84, which adds the nucleus to the output of the circuit retention 88 in each symbol clock pulse. The modulo operator forty-seven 86, performs a modulo operation forty-seven (if > 47, subtract 47), on the output of the adder 84, and supplies the result to the circuit of retention 88. The retention circuit 88 retains this result and supplies this retained result as an address to the second memory 38. In this way, a unique sequence of forty-eight addresses is produced for each core generated by the core generator. 82 The core generator 40 is driven by "RESET 2, and the symbol clock, because the processing occurring in the first memory 32 takes exactly 12 symbol clocks Because the symbols passing through the first memory 32 are delayed for 12 symbol clocks, RESET 2, is correctly aligned with the first symbol of a block, according to . it leaves the first memory 32. The synchronization diagrams of Figures HA and 11B assume a recent acquisition of the signal VSB 8, so that the initial value of the counter 80, the trailing output of the counter 80, the core generator 82, and the holding circuit 88, are unknown. RESET 2 and the first symbol clock cause the counter 80 to be initialized to zero, which, in turn, ensures that the drag output is low. THE RESET 2, too causes the core generator 82 to produce the first core (1). The RE1NICIO 2 and the first symbol clock also cause the output of the holding circuit 88 to be cleared synchronously to zero. The subsequent symbol clocks ™ cause the counter 80 to increase. When the counter 80 reaches a count = 47, it produces a drag signal, which in turn, causes the core generator 82 to produce the next sequential core (12). This drag signal also causes the latch circuit 88 to be wiped synchronously to the Next JO symbol clock. Accordingly, the entrainment signals from the counter 80 cause the core generator 82 to cycle through its 23-core sequence, repeatedly. Each nucleus therefore has a duration of 48 symbol clocks. The complete sequence of 15 23 cores, therefore, encompasses 23 x 48 = 1104 symbols. Because there are 258336 data symbols in a block, the "sequence of 23 cores occurs exactly 234 times in each block (234 x 1104 = 258336) .Therefore, the start of a new block indicated in the synchronization diagram of 20 Figures HA and 11B by RESET 2 pulse # 2 ), always aligns with the first core (1) This alignment is an advantage, because it allows the use of the first RESET signal 2 (derived from the block synchronization signal as previously explained), after the acquisition of signal VSB 8, to initialize the core generator 82 to an output of 1, regardless of the effect of the subsequent RESET 2 signals (one per block), because they will always coincide with a point in time when the? Core generator 82 has an output of 1-5 The sequence of cores, once started after the acquisition of the signal, should not be interrupted. This is necessary for the continuous, correct deinterleaving operation. The timing diagram also shows the output of the holding circuit 88 which corresponds to the required M. (n). The portions of M0 (n), Mi (n), and 2 (n) are illustrated, which occur after RESET 2 pulse # 1. It is assumed that the sequences have cycled through all the M. (n), many times until the end of the first block M22 (n), it is shown that it occurs just before the reset 2, pulse # 2. The second block starts with M0 (n, as expected.) The deinterleaving operation is similar to the rotation elimination operation, which was explained with respect to Figures 6 and 7. That is, when a symbol of Data is read from a storage location in the second memory 38, as determined by the second address generator 40, that data symbol is replaced by the next data symbol, which is received from the first memory 32. consequently, when the symbol clock cause the division counter by forty-eight 80, reach an account of 47, the counter 80 will produce a drag signal, which is supplied to the core generator 82, and to the holding circuit 88 (via the OR gate 89). This drag output causes the core generator 82 to supply a new core to the adder 84. This drag output also clears the latch circuit 88 (in the next symbol clock), so that its output is zero. The output of the latch circuit is also supplied back to the second input of the adder 84. For each of the 23 sequences shown in FIG.

Figure 10, the adder 84 adds the zero output of the latch circuit 88 (which represents the first address in each sequence), to the core supplied by the core generator 82. This output of the adder 84 is controlled by a modulo operation forty-seven, and the result is supplied at the entrance of the holding circuit 88. The next symbol clock causes the holding circuit 88 to supply this result of the module operator forty-seven 86, to the second memory 38. This output of the holding circuit 88 is again fed back to the adder 84 to be added to the core of the core generator 82. Thus, the nucleus of the core generator 82 recursively adds itself to the module 47, to produce a corresponding sequence of addresses, which they are supplied to the second memory 38.

Each such sequence of addresses is given by equation (7). At each rotation of the twenty-three sequences, the first sequence is always in order from zero to 47.? In addition, the core of that first sequence is supplied by the core generator 82 is one, as determined by equation (6). Figure 12 illustrates a first embodiment of the core generator 82 in more detail. The core generator 82 includes a multiplier 92, a module operator forty-seven 94, and a holding circuit 96. The multiplier 92 multiplies the output of the holding circuit 96 by twelve, the operator of the forty-seventh module 94 performs a modulo operation forty-seven at the output of the adder 92, and the holding circuit 96 retains the output of the module operator forty-seven 94. When the RESET 2 is produced by the controller 34, k the latch circuit 96 is reset, so that its output is one. This one is supplied as the nucleus for the adder 84. This one is also multiplied by twelve times the multiplier 92, and the result is operated in the module operator forty-seven 94. The output of the module operator forty-seven 94, is supplied to the holding circuit 96, which retains this output until reception of the next drag output of the division counter by forty-, and eight 80. With the receipt of this output of In this case, the output of twelve of the holding circuit 96 is fed back to the multiplier 92, which multiplies this twelve by twelve to produce an output of 144, which is "operates by the forty-seven module operator 94. The five module operator forty-seven output 94 (three) is supplied to the latch circuit 96, which retains this output until the next entrainment output is received. division counter by forty-eight 80. With the reception of this drag output, the output of three of the -10 retention circuit 96, is fed back to multiplier 92, which multiplies this three by twelve to produce an output of thirty-six, which is operated on the operator of module forty-seven 94. The output of the operator of the moa- No. forty-seven 94 (that is, thirty-six), is supplied to the holding circuit 96, which retains this output through receipt of the next output of 'drag of the division counter for forty and eight 80. With the reception of this drag output, the thirty-six output of the latch circuit 96, feeds back to multiplier 92, which multiplies this thirty-six by twelve, to produce an output of 432, and so on. Accordingly, the core generator 82 produces the twenty-three cores described above. Figure 13 illustrates a second embodiment of the core generator 82 in more detail. This generator nuclei 82 includes a multiplication by twelve, and modulo operator forty-seven 98, and a latch circuit 10. Multiplication by twelve and modulo operator forty? and seven 98, as shown in more detail in Figure 14, includes an adder 102, which adds the four most significant bits of the output of the latch circuit 100, after the two least significant bits have been discarded at 104, to a correction factor of a modulus forty correction logic and seven 106, which is shown in more detail in Figure 15. When the RESET 2 is produced by the controller 34, the holding circuit 100 is re-addressed so that its output is one. This one is supplied with the kernel for the adder 84. This one is also multiplied by twelve and the result is processed by a modulo operation forty-seven, by multiplication by twelve, and the operator of f modulo forty-seven 98. The output of the multiplication by twelve and the module operator forty-seven 98, is supplied to the holding circuit 100, which retains this output until the receipt of the following drag output of the division counter by forty-eight 80. The twelve output of the holding circuit is fed back to the multiplier 100, which multiplies twelve by twelve, and the result (144) is processed by a forty-seventh moaulo operation, by multiplication by twelve, and he module operator forty-seven 98, to produce an output of three. The output of three of the multiplication by twelve, and the operator of module forty-seven 98, is ™ supplies the holding circuit 104, which retains this output until the reception of the next drag output, the division counter by forty-eight 80, and so on. Accordingly, the core generator 82, produces the twenty-three cores described above. The multiplication by twelve and the operator of the module O forty-seven 98, is shown in more detail in Figure 14. When the output of the latch circuit 100 is one (i.e., a digital value of 000001), the two bits less significant (01), are fed to the module correction logic forty-seven 106, which provides an output 15 of twelve. The output of twelve is added by the adder 102 to the four most significant bits (0000) of the output of the 'holding circuit 100, and the result of twelve, is supplied to the holding circuit 102. The holding circuit 102 retains the twelve at its output until the reception 20 of the next pulling output, the division counter by forty-eight 80. When the output of the latch circuit 100 is twelve (i.e., a digital value of 001100), the two least significant bits (00) are fed to the module correction logic forty-seven 106, which provides an output of zero. This output from zero adds up by the adder 102 to the four most significant bits (0011), of the output of the holding circuit 100, and the result of three, is supplied to the holding circuit? 102. The holding circuit 100 retains the three at its output until the receipt of the next drag output of the division counter by forty-eight 80, and so on. The module correction logic forty-seven 106, is shown in more detail in Figure 15, and includes the logical IOS. The two least significant ones, OUT 0 and OUT 1, of the logical 108, are always zero. The four most significant outputs, OUTPUT 2 - OUTPUT 5, of the logic 108, are controlled by the two least significant bits in the output of the retention circuit 100, INPUT 0 and INPUT 1. A second mode of the second generator of address 40, based on equation (4) is illustrated in FIG.

Figure 16. This second embodiment includes a counter 112, which counts symbol clock pulses, and supplies a output in each count to a multiplier 114. The trailing output of the counter 112 is supplied to a core generator 116, which may be a state machine, or a RAM, or the like, to the core generator 82, the generator of nuclei 116 is tilted through twenty-three states by the trailing output of the counter 112, in order to supply a corresponding core, as determined by equation (6), with each tilt. The multiplier 114 multiplies the counter count of the counter 112, by the > core provided by the core generator 116, and supplies the result to a module operator forty-seven 118. The output of the module operator forty-seven is supplied to the input of the holding circuit 120. The output of the holding circuit 120 is reset to zero by the trailing output of counter 112. Thus, at the start of each direction sequence, the output of the holding circuit 120 120 is equal to zero, which is always the first direction of each direction sequence. At the end of each address sequence (i.e., the forty-eight count), the core generator 116 is tilted in order to supplying a new core to the multiplier 114. Certain modifications of the present invention have been discussed above. Other modifications will occur to those who practice the technique of the present invention. For example, although the present invention has been specifically described in terms of two-bit data symbols, it should be understood that the present invention is applied to other data elements. In addition, the present invention can be used in conjunction with different arrays of data blocks, and different protocols of rotation 'and / or collation.

Accordingly, the description of the present invention is constructed as illustrative only, and is for the purpose of teaching those skilled in the art, the best mode of carrying out the invention. The details may vary substantially without departing from the spirit of the invention, and exclusive use is reserved for all modifications, which are within the scope of the appended claims. It is noted that in relation to this date, the best method known by the applicant to carry out the aforementioned invention, is the conventional one for the manufacture of the objects to which it relates. Having described the invention as above, property is claimed as contained in the following:

Claims (7)

1. An apparatus for reordering first and second "groups of data elements from a first order to a second order, characterized in that it comprises: a memory having a plurality of memory locations, wherein the first group of data elements is stored in the memory, to be replaced by the second group of data elements, and JO an address generator arranged to generate addresses and to supply the addresses to the memory, so that as each address is received by the memory, a first element of data of the first group of data elements, is read from a first location of 15 memory, and so that a data element of the second group of data elements is written to the first location 'of memory, before a second data element of the first group of data elements is read from a second memory location.

2. The apparatus according to claim 1, characterized in that the address generator is arranged to supply addresses to the memory, so as to eliminate the rotation of the data elements of the first and second groups of data elements.

3. The apparatus according to claim 1, characterized in that the address generator is arranged to supply addresses to the memory, so as to de-scale the data elements of the first and second groups of data elements. The apparatus according to claim 1, characterized in that the memory is a first memory, wherein the address generator is a first address generator, wherein the apparatus further comprises a second memory, and a second address generator, wherein the first address generator substantially alone, supplies addresses to the first memory, and the second address generator substantially alone, supplies addresses to the second memory, so that the data elements entering the first memory are rotated and interleaved, so that the data elements are read from the first memory as data elements without rotation and interleaved, so that the non-rotated and interleaved data elements are stored in the second memory, and so that the data elements are read of the second memory as data elements without rotation and deinterleaved. 5. The apparatus according to claim 1, characterized in that each of the first and second groups of data elements, includes D elements of data, and where the memory stores substantially D data elements at one time. 6. The apparatus in accordance with > claim 5, characterized in that the data elements 5 in the first and second groups of data elements, are rotated as received by the apparatus, and wherein the address generator comprises: address account means for counting from 0 to D-1, to provide an output account corresponding 10 from 0 to D-1, and to restart after reaching an account > ] of D-1; means for generating compensation, to generate compensation, wherein the compensation is dependent on the degree of extension of the rotation of the D data elements; and, combination means, to combine the compensation and the exit account, to generate the addresses. 7. The apparatus according to claim 6, characterized in that the compensation also depends on the group of D data elements. The apparatus according to claim 7, characterized in that the data elements are arranged in S segments, wherein each S segment of 25 data elements, is comprised of G groups of elements of data, wherein the G groups of data elements include the first and second groups of data elements, and wherein the compensation also depends on the data segment. W data elements. 9. The apparatus according to claim 8, characterized in that the means generating the compensation generate a zero compensation for a first of the S segments, wherein the means generating the compensation generate a zero compensation for a first -10 group of a second of the S segments, where the means that generate the compensation generate a compensation of eight for a second group of the second of the S segments, where the means that generate the compensation generate a compensation of four for a third group of the second of 15 S segments, where the means that generate the compensation generate a zero compensation for 'any remaining groups of the second of the S segments, where the means generating the compensation generate a zero compensation for a first group of a third of the 20 S segments, where the means generating the compensation generate a compensation of eight for a second group of the third of the S segments, where the means that generate the compensation generate a compensation of four for any remaining groups of the third of the S segments, 25 where * the means that generate the compensation generate a compensation of four for a first group of a quarter of the S segments, and where the means that generate the compensation generate a zero compensation for any remaining groups of the fourth of the S segments. The apparatus according to claim 1, characterized in that the data elements are arranged in m groups of data elements, wherein the m groups of data elements include the first and second group of data elements, where each group of data elements have D data elements, wherein the data elements are interleaved according to a first order, wherein the apparatus is arranged to de-interleave the data elements to a second order, and where the memory stores substantially mD One-time data elements. The apparatus according to claim 10, characterized in that the address generator comprises: means of counting to count from 0 to mD-1, to provide an output account when an mD-1 account is reached, and to restart after providing the exit account; generator means of cores, which respond to the output account to generate a kernel; Y, conversion means to convert the output account and the kernel to a sequence of addresses. The apparatus according to claim 11, characterized in that the nucleus generating means is arranged to generate L cores, where L is given by the following equation: (-?) mod (mD-1) = 1 where L is 0, 1, 2, ..., until the nuclei begin to repeat in Lm -.x, where R = D, where the direction sequences are given by the following equation: ME (n) = 0 for n = 0 Mi (n) = (M1 (n-D + R1) mod (mD-l) for n = 0, 1, 2, ... .mD-1 wherein i varies from 0 to LBax-1. The apparatus according to claim 1, characterized in that the memory comprises first and second memories, wherein the address generator comprises first and second address generators, wherein the first generator is arranged to supply addresses to the first memory, so that they eliminate the rotation of the data elements, and where the second address generator is arranged to supply addresses to the second memory, so that it deinterleaves the data elements, thus producing the second order. 1

4. The apparatus according to claim 13, characterized in that the first memory 5 stores D data elements at one time, where the second memory stores D data elements only once, and where m is an integer. 1

5. The apparatus according to claim 14, characterized in that the first generator Management JO comprises: first account means to count from 0 to D-1, to provide a corresponding exit account from 0 to D-1, and to restart after reaching a D-1 account; means that generate a compensation, to generate a compensation, wherein the compensation depends on the degree of rotation of the D data elements; Y, ? first conversion means, for converting the compensation and the corresponding exit account of the first account means, to a first sequence of addresses; and, wherein the second address generator comprises: second account means to count from 0 to mD-1, to provide an exit account when an mD-1 account is reached, and to reset after providing the account. of exit; generator means of cores, which respond to the exit account of the second account means, to generate a core; and, second conversion means for converting the core to a second sequence of addresses. 1

6. The apparatus according to claim 15, characterized in that the means generating the compensation generate a zero compensation for a first of the S segments, wherein the means that 10 generate the compensation generate a zero compensation for > a first group of a second of the S segments, where the means that generate the compensation generate a compensation of eight for a second group of the second of the S segments, where the means that generate the compensation 15 generate a compensation of four for a third group of the second of the S segments, where the means that generate the compensation generate a zero compensation for any remaining groups of the second of the S segments, where the means that generate the compensation generate a 20 zero compensation for a first group of a third of the S segments, where the means generating the compensation generate a compensation of eight for a second group of the third of the S segments, where the means that generate the compensation generate a four compensation for 25 other groups of the third of the S segments, wherein the means generating the compensation generate a compensation of four for a first group of a quarter of the S segments, and wherein the means generating the compensation generate a zero compensation for any remaining groups of the fourth of the S segments. The apparatus according to claim 16, characterized in that the means generating the cores is arranged to generate L cores, where L is given by the following equation: -.10 (-? L) -nodt-nD- l) = 1 where L is 0, 1, 2, ..., until the nuclei begin to repeat in L ----, *, where R = D, where the sequences of 15 address are given by the following equation: 'Mi fn, l = (n • R1-) mod (N-l) for n = 0, 1, 2, V-l wherein i varies from 0 to Lmax-1.4, wherein the unique address generator comprises; address account means to count from 0 to D-1, to provide a corresponding exit account from 0 to D-1, and to reset after reaching a D-1 account; means that generate a compensation to generate a compensation, wherein the compensation depends on the degree of extension of rotation of the D data elements; and, combination means to combine the compensation and the exit account, to generate the addresses.