MXPA98010752A - Arc fault detector with circuit interrupter - Google Patents

Abstract

Un dispositivo interruptor de circuito por falla de arco (AFCI) funciona para proporcionar protección de las fallas de arco potencialmente peligrosas. El detector de falla de arco se puede utilizar independiente o en combinación con dispositivos de interrupción de circuito, tales como IDCIs y ALCIs. El dispositivo AFCI detecta tanto las frecuencias de la línea de corriente alterna como las altas frecuencias asociadas con la formación de arco. Ambos valores promedio e instantáneo de la frecuencia de línea de corriente alterna y de las señales de arco de alta frecuencia se procesan para generar una señal de falla de arco. El mecanismo de disparo del dispositivo dispara sobre la presentación de una falla de arco o de una falla de tierra. El dispositivo permite que el detector de arco diferencie entre la formación de arco de alto nivel destructiva, y la formación de arco de bajo nivel, tal como el generado por los aparatos y equipos del hogar típicos. Esto sirve para disminuir la presentación de disparos falsos. El dispositivo también incluye un circuito de cronómetro, que permite al usuario deshabilitar temporalmente el detector de arco, e incluye un elemento de comunicación para permitir que el dispositivo comunique la presentación y localización de la falla de arco a una estación de monitoreo centralizada.

Description

ARC FAILURE DETECTOR WITH CIRCUIT BREAKER FIELD OF THE INVENTION The present invention relates to an apparatus method for the detection of arc fault, and more particularly relates to an apparatus and method both for an independent arc fault detector and for a combined arc fault detector. with a circuit breaker device.

BACKGROUND OF THE INVENTION Circuit breakers, fuses, and ground fault circuit interrupters (GFCIs), or devices commonly used to protect people from the property of dangerous electrical faults. However, fatalities and loss of property still occur, which are caused by electrical faults that go undetected by these protective devices. One of these types of electrical failure that typically happens if detected is that of arc faults. The arches are potentially dangerous, due to the high temperature contained inside them. Consequently, they have a potential to create damage, mostly through the initiation of fires. However, an arc will only trip a circuit breaker due to ground fault if it produces enough current leakage to the ground. In addition, an arc will trip a switch only if the current, which flows through the arc, exceeds the thermal / magnetic mechanism tripping parameters of the switch. Therefore, an additional type of protection device is needed to detect and interrupt arcs that do not meet this criteria. An arc detector, whose output is used to trigger a circuit breaker mechanism, is referred to as an arc fault circuit interrupter (AFCI). According to the Consumer Product Safety Commission (CPSC) in 1992, it was estimated that "there were 41,000 fires that involved household electrical wiring systems ... which resulted in 320 deaths, 1,600 injuries and $ 511 million in property losses. " The Consumer Product Safety Commission further stated that it can present an electrically caused fire if the electrical energy is unintentionally converted to thermal energy, and if the heat thus generated is transferred to such combustible material at such a rate, and for a time such that it causes the material to reach its ignition temperature ". The two main causes of intentional conversion of electrical energy into heat are excessive current and arc formation. Circuit breakers and fuses are currently available to mitigate the results of excessive current, but there is no commercial system to mitigate arc formation. A dangerous condition may develop, provided there is an extended arc formation, regardless of whether it involves industrial, commercial or residential power lines. However, mobile homes, and especially houses with outdated wiring systems, are particularly vulnerable to fires initiated due to electrical causes. The Consumer Products Safety Commission studies have shown that the frequency of fires due to wiring systems is disproportionately high in households over 40 years of age. The causes of arc formation are numerous, for example: insulation and old or worn wiring; mechanical and electrical stress caused by overuse, overcurrents or - lightning bolts; loose connections; and excessive mechanical damage to insulation and wires. Two types of arc are presented in residential and commercial buildings: contact arc and line arc. The contact arc (or series) is presented between two contacts in series with a load. Therefore the load controls the current flowing in the arc. The line arc (or parallel) occurs between the lines or from a line to the ground. Therefore, the arc is parallel to any present load, and the impedance of the source provides the only limit to the current flowing in the arc. It is important that any arc detection system can detect both the arc contact and line, act appropriately, depending on the severity of the arc. An example of the arc of contact is illustrated in Figure 1. The conductors 114, 116, comprising the cabil 110, are separated and surrounded by an insulator 112. A portion of the conductor 114 is broken, creating a gap in seri 118 in the conductor 114. Under certain conditions, the arc will present through this gap, producing a large amount of localized heat. The heat generated by the arc could be enough to break and carbonize the insulation near the arc 119. If the arc is allowed to continue, it will generate enough heat to start a fire. Figure 2 shows a schematic diagram illustrating an example of the line arc. The cable 120 comprises the electrical conductors 124, 126, covered by external insulation 122, and separated by the internal insulation 128. The deterioration or damage to the internal insulation in 121 may cause an arcing fault formation of line 123 between the two conductors 124, 126. The internal insulation could have been ced by a lightning bolt prior to the wiring system, or it could have been cut by mechanical action such as the leg of a metal chair that cut into an extension cabl. The potentially devastating results of arc formation are widely known, and a number of arc detection methods have been developed in the prior art. A large percentage of the prior art refers to the detection of high frequency signals generated in the alternating current line by the arcs. The Figure shows the broad spectrum noise 162 produced on the alternating current line by an arc. It is superimposed on line voltage of alternating current 164. An analysis of the arc waveform, using a frequency spectrum analyzer, shows that the overtones and onics of alt frequency contained inside the waveform, extends well inside the GHz range. A graph illustrating frequency spectrum analysis d of waveform 162 shown in Figure 3 is shown in Figure 4. A major problem associated with any type of arc detection is false triggering. The false trigger occurs when an arc detector produces a warning output, or disconnects a section of the cable from the source of voltage, when there is really no arc-forming hazard. The two main causes of a false dispar, are the normal arcing of the devices, and the input currents created by capacitive inductive devices. These two situations generate high frequency signals on the energy line, which are very similar to those generated by the dangerous arc formation. Therefore, to be viable commercial devices, the arc detectors must be able to distinguish the arc signals from the signals created by the normal use of the devices. There is a wide range of prior art in the field of arc detection. Some of the prior art refers to specialized cases of arc formation. For example, U.S. Patent No. 4,376,243 issued to Renn et al teaches a device that operates with direct current. U.S. Patent No. 4,658,322 issued Rivera teaches a device that detects the formation of arc inside an enclosed unit of electrical equipment. The United States Patent Number 4,878,14 issued to Nebon teaches a device that detects the lu produced by an arc between the contacts of a circuit breaker. In addition, there are several patents that relate to the detection of arcs in alternating current power lines, which disclose different methods for detecting high frequency arc signals. For exampleUS Pat. Nos. 5,185,684 5,206,596 both issued to Beihoff et al employ a complex detection element that separately detects the electric field and the magnetic field produced around a wire. U.S. Patent No. 5,590,012, issued to Dollar, teaches the measurement of high frequency current in a line derived around an inductor placed on the line, which may be a magnetic trip mechanism of a switch. In a second detection circuit, proposed by Dollar, the high-frequency voltaj signal is extracted from the line by means of a high-pass filter placed in parallel with any load. Different methods can be found in the prior art to give authenticity to arc formation, and to differentiate arc formation from other sources of noise. Much of the prior art involves a complicated processing and analysis of the signal. United States Patent Number 5,280,404, issued by Ragsdale, teaches the search for serial arcing by converting the arc signals into pulses and s counts the pulses. In addition, several patents detect the arc formation by taking the first derivative or second derivative of the detected signal. For example, U.S. Patent No. 5,244,006, issued to MacKenzie collaborators, and U.S. Patent Nos. 5,185,684 and 5,206,596, issued to Beihof et al., Disclose this device. Blades uses various methods for detecting arcs, as disclosed in United States Patents Numbers 5,223,795; 5,432,455, 5,434,509. The Blades device is based on the fact that the detected high frequency noise must include holes at each zero crossing, that is, half cycle, of the AC line. To differentiate the arcing from other sources of noise, the Blades device measures the randomness and / or broadband amplitude characteristics of the detected high frequency signal. The device taught by U.S. Patent No. 5,434,509, uses the edges of rapid elevation of the arc signals as a detection criterion, and detects short high-frequency bursts associated with the intermittent arcs. U.S. Patent No. 5,561,505 issued to Zuercher et al. Discloses a method for detecting arc formation by detecting the changes from cycle to cycle in the current of the alternating current line. The differences in the samples taken at the same point of the alternating current cycle are then processed to determine if arc formation is occurring.

COMPENDIUM OF THE INVENTION The arc detector of the present invention functions to monitor and detect the line voltage and the current present in the alternating current power line, to determine the arc presentation. Both the high frequency energy and the alternating current line frequency energy are used in the detection of arc faults. The detector output can be used to activate a circuit breaker mechanism, a sound and audio alarm and / or pair to alert a central monitoring station. The arc detector of the present invention can be implemented as a stand-alone device, or it can be implemented in combination with an existing circuit breaker device. The term "circuit breaker device" is defined as any electrical device used to interrupt the flow of current to a load, and includes, but is not limited to, such devices as Ground Fault Circuit Interrupters (GFCIs) Circuit Breakers by Immersion Detection (IDCIs) or apparatus leak circuit interrupters (ALCIs). A novel feature of the arc detector of the present invention is that it combines an arc detector, that is, an arc fault circuit interrupter (AFCI) with other types of circuit breaker devices, such as a circuit breaker per ground fault, or immersion detection circuit breaker, or device leakage circuit breaker to create a multipurpose device of AFCI / GFCI, AFCI / IFCI, AFCI / ALCI, respectively. In the case of a ground fault circuit interrupter, the arc detection circuit can be placed on board the same silicon chip typically used in today's ground fault circuit interrupter devices. Actually, some of the peaks of commonly used ground fault circuit interrupter circuits can be converted for multi-function operation. The arc fault circuit interrupter can be energized from the same power supply that provides power to the circuit breaker device. This combined approach results in reduced manufacturing costs. The mechanical parts of the circuit breaker device, such as the trip relay, and the mechanical contact enclosure mechanisms, now serve double purposes. In addition, adding the circuit breaker circuit due to an arc fault to an existing circuit breaker device is a logical improvement of current devices. In particular, it is logical to improve a ground fault circuit interrupter with a circuit breaker circuit due to arc failure, since a ground fault circuit interrupter can detect arcing in certain situations, including any condition in where an arc produces leakage current to earth. In the AFCI / GFCI device of the present invention, the waveform of the current present on the alternating current line is extracted by means of a toroidal current to the voltage transformer. The voltage that is generated through the secondary coils of the transformer is fed to two separate lines. In the first line, the content of the AC line frequency of 50 or 60 Hz of the transformer output is filtered from the input signal. This alternating current line frequency signal provides an indication of the amount of current flowing through the AC power line. In the second line, the high-frequency current of the transformer output s filters out the input signal. The high frequency signal indicates the level of arc present in the AC power line. Within each of the two lines, the signals s filtered by a second stage filter, and then they rectify. The two rectified signals are divided each to produce the peak and average levels for the AC line frequency and the high frequency signals The excessively high peaks on the AC line frequency or on the high frequency line, instantaneously causes the AFCI / GFCI relay mechanism to trip, disconnecting the load from the power source. The absolute average levels of the frequency of the alternating current line and of the high frequency signals are converted to a direct current potential, and s compared with a set of previously defined voltages. If the average high frequency signal is greater than the expected level of arc formation of a normal apparatus at the frequency level of the associated average alternating current line, then an output signal is generated. It then uses this output signal to trigger the device to produce an alarm, both controlled by a timer mechanism. A user can disable the AFCI function temporarily or permanently, so that the devices can be operated with normally high levels of arc formation, such as arc welders, if firing the arc detector. High frequency alternating current line frequency detection or high frequency signals causes the device to trigger immediately. This immediate shot can not be disabled by the chronometer mechanism described above. In addition, the protection mechanism for ground fault and excessive arc current, and the detection of alternating current line current, can not be disabled. This is so that a user is continuously protected from the potential hazards associated with these conditions. An advantage of the present invention is that the separation of the detection of line current from alternating current and the high frequency energy generated by the arc, provides a greater immunity to noise. The arc detection device detects the current flowing in the alternating current line through a wide range of frequencies. By dividing the two current signal components, and by establishing a maximum allowed level of high frequency component for a given level of AC line current, the arc detector provides greater noise immunity. In addition, the arc detector of the present invention simultaneously performs the detection of the peak average of the alternating current line current and the high frequency arc signal. The peak AC line current and the high frequency arcing signals are detected to provide an immediate response to large increases in either arc formation or alternating current line current. The arc detector will trip the relay in the instant when the peak AC line current signal or d the high frequency arc formation signal peak crosses a predetermined threshold. The arc detector also incorporates a fast tripping circuit that operates to open the relay when s detect an excessive average AC line current, and excessive high frequency arc formation levels. If the average alternating current line current or the average high frequency arcing signal rises above a level considered dangerous, the device will trip very quickly. The maximum permitted level for the average alternating current line current is approximately 1.5 times the current of the nominal alternating current line. The limit set for the average high frequency signal is an average arc level that is known to be dangerous. When the levels of the average AC line current and the high frequency signal are lower than their respective maxima, the arc detector uses different trigger levels for the arc formation, depending on the level of the average alternating current. let it flow In addition, the arc detector fires at a slower speed at these lower arc levels and therefore less dangerous. This slower firing response time provides noise immunity against noise and short-lived arcs, such as the arcs generated when a switch is levered. By incorporating different firing times, depending on the level of arc formation detected, the arc detector can extinguish dangerous arcs quickly, while providing a high immunity to noise for lower level arcs. The arc detector also incorporates an automatic bypass chronometer to allow arcing in another normally safe manner. Instead of including a fixed on / off switch, which would function to enable or completely disable the arc detector, the present invention incorporates a logic switch. This logic switch provides a user with the option to disable the arc detector for as long as the switch is off, or to disable the arc detector temporarily while using arc-forming apparatus. This allows the use of devices that normally generate high amounts of arcing, which would otherwise cause the arc detector to trip. When it is temporarily disabled, the arc detector automatically returns to the enabled state after the device has been disconnected. This scheme has the advantage that the device can not be accidentally disabled in a permanent way by the user. An important feature of this scheme is that the arch forming apparatus can be activated and deactivated within a given period of time without triggering the arc detector. In addition, the arc detector includes circuits for transmitting messages, which use any suitable communication element that signals the location of the arc fault. For example, these communication elements may comprise any energy carrier, radiofrequency, twisted pair, or infrared communication carrier technology. An example of line-of-energy carrier communications includes the Lon Works CEBus communications systems. By way of example only, the present invention incorporates a communications circuit, which uses a power line carrier signal, such as that generated by the CCS product line manufactured by Leviton Manufacturing Little Neck, New York. Using well-known energy line carrier techniques, the arc detector can communicate with other devices, such as a monitoring station. Each arc detector would have a unique address. Then a relation is established between the address assigned to the arc detector and its location. When an arc fault is detected, a signal is sent over the power lines to a monitoring station, which alerts the personnel, not only of presenting the arc fault, but also of its location. This is especially useful if the AFCI / GFCI device is installed at a remote location. This characteristic has applicability in commercial industrial places, where a central supervision of the arc fault is needed over a complex alternating current electrical wiring system. One skilled in the electrical art will appreciate that other types of communications such as those mentioned above can be used instead of the CCS communication system. Currently, alternating current power lines are not only used to supply AC line current, but they are also used as a communications medium, such as in the line of the CCS energy line carrier device from Leviton Manufacturing. devices compatible with CEBus, the devices compatible with Lon Works, the intercoms based on the carrier of the power line, the equipment d transmission / reception of television signals, the telephone communication devices, and so on. The arc detector of the present invention incorporates a filter circuit that allows the detection of arc faults, while communications are being presented on the AC power lines. The filter circuit works to remove frequencies below 500 KHz. At the other end of the frequency spectrum, although the arc generates frequency in the GHz scale, for simplicity, efficiency, reduced cost, the arc detector of the present invention limits the detection of high frequency signals approximately 20 MHz.

BRIEF DESCRIPTION OF THE DRAWINGS The invention is described herein, by way of example only, with reference to the accompanying drawings in which: Figure 1 is a schematic diagram illustrating an example of the arc of contact in a conductor carrying current . Figure 2 is a schematic diagram illustrating an example of the line arc ben two conducting conductors. Figure 3 is a graph illustrating broad spectrum noise due to the EMF voltage generated by an arc that propagates over the power line superimposed on the alternating current line voltaj. Figure 4 is a graph illustrating the analysis of the frequency spectrum of the waveform shown in Figure 3. Figure 5 is a schematic diagram illustrating an example of a ground fault circuit interrupter device of the prior art. . Figure 6 is a high-level block diagram illustrating the combination of the arc fault detector and the ground fault circuit interrupter device of the present invention. Figure 7 is a schematic diagram illustrating the portion of the AFCI / GFCI circuit of the arc fault detection device of the present invention in greater detail.

Figure 8 is a graph illustrating the voltage d output of the transformer against time to vary the current quantities. Figure 9 is a graph illustrating the voltage d output of the transformer against the time for 28 A d current, with the alternating current line voltage overlapped '. Figure 10 is a graph illustrating the substantially linear relationship ben the transformer output voltage and the input current. Figure 11 is a schematic diagram illustrating the portion of the high frequency circuit of the arc fault detection device of the present invention with greater detail. Figure 12 is a schematic diagram illustrating the portion of the alternating current frequency circuit circuit of the arc fault detection device of the present invention in greater detail. Figures 13A, 13B, and 13C are schematic diagrams illustrating the portion of the arc detection circuit of the arc fault detection device of the present invention in greater detail. Figure 14 is a graph illustrating the input current versus time for an incandescent load d 15A.

Figure 15 is a schematic diagram illustrating the portion of the chronometer circuit of the arc fault detection device of the present invention with more detail. Figure 16 is a schematic diagram illustrating the portion of the local / remote inhibition circuit of the arc fault detection device of the present invention in greater detail. Figure 17 is a schematic diagram illustrating an example of an immersion detection circuit breaker device of the prior art. Figure 18 is a schematic diagram illustrating the combination of the arc fault detector and the dip detection circuit breaker device of the present invention.

DETAILED DESCRIPTION OF THE INVENTION Ground fault circuit interrupters (GFCIs) are well known electrical devices in common use today. They are used to help protect against electric shock due to ground fault. A GFCI is basically a differential current detector that operates to trigger a contact mechanism when 5 mA or more of unbalanced current is detected ben the phase wire (hot wire) and the neutral wire (N) of an electrical power line of alternating current. It is assumed that the unbalanced current detected is that which is flowing through a human being accidentally touching the phase wire. The current flows through the human being to the earth, instead of returning through the differential transformer via neutral wire, thus creating the unbalance d current described above. It should be noted that, n only the current through a human being, but also from an apparatus with inherent leakage to earth of 5 mA or more would also trigger the GFCI and disconnect the current to the load. A schematic diagram showing an example of a ground fault circuit interrupter device of the prior art is shown in Figure 5. The typical prior art GFCI, generally referred to as 12, comprises two current transformers consisting of magnetic cores, 48, 50 and coils 52, 54 respectively, coupled to the integrated circuit 40, which may comprise the LM1851 manufactured by National Semiconductor. S places a relay coil 30 between the phase and an input to a full-wave bridge rectifier. The AC power from the phase 14 and neutral conductors 16 is full-wave rectified by means of a full-wave rectifier comprising the diodes 20, 22, 24, 26. S places a metal oxide varistor (MOV) 18 through the phase and the neutral for protection. The bridge output is coupled through the capacitor 28 and the silicon controlled rectifier (SCR) 32. The SCR gate is coupled to the ground via capacitor 38, and with the peak 1 of the integrated circuit 40. A diode is placed 70 through the coil 52, which is coupled to the peaks 2 and 3 by means of the resistor 62 and the capacitors 64, 60. The peak 3 is also coupled to ground by means of the capacitor 36. The coil 54 is coupled to the bolts and 5 of the integrated circuit 40 by means of capacitors 58 60. Peak 4 is also coupled to ground. The integrated circuit 's peak 6 is coupled to the peak 8 via resistor 44, and the peak 7 is coupled to the ground via capacitor 42. The peak 8 is also coupled to the capacitor 34 and resistor 46. The voltage on the Peak 8 serves as the 26 volt supply voltage for the GFCI circuit. - The line side, fas 4 and neutral 16 electrical conductors pass through the transformers to the phase and neutral conductors on the load side. . A relay, which consists of the switches 66, 68, associated with the phase and neutral conductors, respectively, operates to open the circuit in the event that a ground fault is detected. The switches 66, 68 are part of the launch double relay that includes the coil 30. The coil 30 in the relay is energized when the GFCI circuit activates the silicon controlled rectification (SCR) 32. In addition, the GFCI 1 comprises a test circuit comprised of momentary pressure button switch 49 connected in series with resistor 15. When switch 49 is pressed, a temporary simulated ground fault is created, i.e., a temporary differential current line d, from phase to neutral , in order to test the operation of the GFCI 12. A high-level block diagram illustrating the arc fault / circuit breaker device of the present invention is shown in Figure 6. For illustrative purposes only, the following description is within the context of a combination of a circuit breaker device for arc fault / ground fault circuit interrupter (AFCI / GFCI). It should be clear to one skilled in the art, however, that other types of circuit breaker devices such as IDCIs or ALCIs can be combined with the arc fault detector d in a similar manner. The AFCI / GFCI device, generally referenced at 180, and hereinafter referred to as the device, comprises the AFCI / GFCI 182 circuit, the alternating current line frequency circuit 200, and the high frequency circuit 188, the circuit detection circuit 198, the local / remote inhibition circuit 184, and timer circuit 186. The AFCI / GFCI circuit 18 generally comprises a standard GFCI device in addition to several components that are shared between the AFCI and GFCI portions of the device. The device is a four-terminal device comprising the phase and neutral conductors on the line side, as well as the d phase and neutral conductors on the load side. Normally, the device is coupled to an electrical wiring system or network, with the line and neutral terminals on the line side electrically connected to an AC power source. The phase and neutral terminals on the load side are connected to the electrical devices located downstream of the device. Each of the components of the device 180 s is described in more detail hereinafter starting with the AFCI / GFCI circuit. In Figure 7 a schematic diagram is shown, illustrating the portion of the AFCI / GFCI circuit of the arc fault detection device of the present invention in greater detail. The GFCI portion of the device is briefly described below. A more detailed description of a GFC circuit can be found in U.S. Patent No. 5,202,662, issued to Bienwald et al. A GFCI is an electrical device that works to detect hazardous ground conditions in consumer and industrial environments. The unbalanced current through the differential transformer 233 is detected by the circuit. If the unbalance of currents e greater than a specified threshold, which has been determined dangerous for personnel or machinery, the integrated circuit (IC) 225 triggers the SCR 224. In turn the SCR 22 activates the coil 218 of a switch of the relay circuit comprising the phase contacts 231 and the neutral contacts 232 thereby disconnecting the electric power source from the load. When the GFCI circuit detects the existence of a ground fault, the TRIG_GFCI signal line is activated. In this way, the circuit protects users from harmful or lethal electrical shock. The trigger circuit of SC 236 has three trigger inputs, TRIG_GFCI, TRIG_CRONOMETR and TRIG_ARC. Normally, the three trigger signals are in an inactive state. However, any or all of the three trigger inputs that become active will cause the SCR trigger circuit to generate a switching signal to activate the SCR 224. A second difference transformer 234 is provided inside the AFCI / GFCI circuit to detect a It has a low impedance between the neutral wire and the earth of the load. A low impedance neutral / earth connection allows the ground fault current to escape from the ground to the neutral wire, passing through the differential transformers. This reduces the sensitivity of the GFCI, and potentially allows fatal earth faults to occur without triggering the GFCI. If the impedance d of the neutral / ground connection becomes too low, integrated circuit 225 triggers SCR 224 by means of signal TRIG_GFCI, thus disconnecting both the phase and neutral of the load. As described above, the ground / neutral transformer 234 is used to detect ground-to-neutral faults, and is specifically designed for that purpose. In the present invention, this transformer is used to perform two functions in a simultaneous manner. To detect earth faults, this transformer is used in a differential mod. The sum of the currents in the two wires that pass through its center is zero in the absence of a ground fault or a ground / neutral fault. In particular, the AFCI / GFCI circuit, generally referenced 182, comprises two current transformers consisting of the magnetic cores 233, 234 the coils 235, 219, respectively, coupled with the integrated circuit 225, which may comprise the LM185 manufactured by National Semiconductor, or the RA9031 manufactured by Raytheon. The alternating current energy from the phase 14 and neutral conductors 16 is rectified complete wave by means of a full wave rectifier which comprises the diodes 211, 212, 213, 214. A varisto of metal oxide (MOV) 210 is placed through the phase and the neutr for protection. The bridge voltage output represented as VRECT is coupled through capacitor 215 and in series with diode 216. The cathode of the diode is coupled with a capacitor 217 and with SCR 224. The gate of the SCR is coupled with the output of a trigger circuit of SCR 236. The output of peak 1 of integrated circuit 225, forms one of the inputs to the trigger circuit of SCR 236. A diode 245 is placed through coil 235, which is coupled to peaks 2 and 3. by means of resistor 247 and capacitors 239, 249. Peak 3 is also coupled to ground by means of capacitor 251. Coil 219 is coupled to spikes 4 and 5 of integrated circuit 225 by capacitors 237, 238. Peak 4 is also coupled to ground. The integrated circuit peak 6 is coupled to the peak 8 by means of resistor 241, and the peak 7 is coupled to ground via capacitor 243. The peak 8 is also coupled to the capacitor 222 to the resistor 221. The voltage at the peak 8 serves as the 26 volt supply voltage for the GFCI circuit. The 2 volts are coupled to a resistor 259 and a zener diode 261 which operates to generate a lower supply voltage Vcc to be used by the internal circuit of the AFCI / GFCI. The line-side electrical conductors, fas 4 and neutral 16, pass through the transformers to the phase and neutral conductors on the load side. A relay, which consists of the switches 231, 232, associated with the phase and neutral conductors, respectively, operates to open the circuit in the event that a ground fault is detected. The switches 231, 232 are part of a double-release relay d including the coil 218. The coil 218 in the relay is energized when the circuit GFCI / GFCI activates the SC 224. In addition, the circuit comprises a test button comprised of the momentary pressure button switch 22 connected in series with a resistor 230. When depressed and switch 228, a temporary fa ground fault to neutral is created, in order to test the operation of the device It is believed that a novel feature of the present invention is the incorporation of the necessary circuit to detect arc faults in a circuit interruption device, such as a GFCI. The rest of this document describes the arc detection circuit (AFCI) with greater detail. The portions of the AFCI and GFCI circuit operate independently of each other, but they share several components. With reference to Figure 7, both circuits are energized from the line side of the alternating current power source, through the same power supply. The resistor 259 and the zener diode 261 are required in order to lower the voltage of the GFCI circuit to a level that can be used for the rest of the circuit. The output voltage Vc is provided to both portions of the AFCI and GFCI circuit Both AFCI and GFCI circuits operate to interrupt the AC power, opening two sets of contacts 231 232 by means of the drive of a relay coil 218. L coil The triggering of the relay is triggered by the triggering of the SCR 224 by means of the trigger circuit of SCR 236. Although either d AFCI or GFCI circuitry can trip the SCR 224, its trigger signals are isolated from one another. The SCR trigger circuit operates to provide a logic operation type O (or) to trigger the SCR 224, using well-known thyristor tripping techniques, when any of its three input triggers TRIG_GFCI, TRIG_CRONOMETER, TRIG-ARC is activated. The AFCI / GFCI circuit also comprises a toroidal current to the voltage transformer 229, which can be placed on the phase or neutral line of the alternating current source. In Figure 7, the transformer is shown with the phase line passing through it. Alternatively, the neutral conductor can pass through it. The turn ratio of the transformer 22 is calculated to generate a primary current to the secondary voltage ratio of about 10 A to a peak of 1 V. The transformer 229 is preferably constructed from a ferrite material that can detect a band. wide range of frequencies ranging from a few H to MHz. A wide-band transformer 22 is required in order to provide the AFCI detection circuit with the low and high frequencies that are needed for the device to detect arc faults. Tests performed by the inventors have shown that, at high currents, ie, greater than 1A, the transformer 229 generates a peak output voltage that is linearly proportional to the peak current flowing through it. The ratio of the input current to the output voltage of the transformer is illustrated in FIGS. 8, 9, and 10. FIG. 8 is a graph illustrating the transformer output voltage versus time for varying quantities of current. Figure 9 is a graph illustrating the output voltage of the transformer versus the time for 28 A d current, with the alternating current line voltage superimposed. Figure 10 is a graph illustrating the substantially linear relationship between the transformer output voltage and the input current. This ratio of the input current to the output of the transformer voltage remains true, whether the load is resistive, capacitive, inductive, or a combination of the three. Accordingly, the type of load connected to the device does not affect the arc detection in any way. With reference to Figure 6, the transformer output 229 is put into two separate circuits. The circuit is the high frequency circuit (HF) 188 comprising a high pass filter 190, the full wave rectifier 192, the amplifier 194, and the integrator 196. The second circuit is the AC line frequency circuit. 200 comprising the low pass filter 202, the full wave rectifier 204, the amplifier 206, and the integrator 208. The division of the output signal from the transformer 229 into two signals of different frequencies, allows the device to react to different combinations of alternating current and high frequency line frequency arc signals. This allows the AFCI circuit to react appropriately to many different overcurrent arc situations. A schematic diagram illustrating the high frequency circuit portion of the arc fault detection device of the present invention is shown in greater detail in Figure 11. The high-pass filter 190 comprises a passive high-pass filter (LC network), or amplifier, and a high-pass filter based on serially active operating amps. The capacitor 242 is selected to have a negligible impedance for frequencies above about 500 KHz, while the inductor 246 s selects to be an open circuit above 500 KHz. Consequently, high frequencies pass through the filter. At low input frequencies, the capacitor 242 has a high impedance, and the inductor 246 appears as a short virtual ground, thereby severely attenuating the low frequency signals. The resistor 240 helps to prevent the network L consisting of the capacitor 242 and the inductor 246 from resonating with the damping oscillations. Accordingly, network L functions as a high-pass filter, whose output is input to operational amplifier 250. The gain of operational amplifier 250, defined by resistors 248 and 254, is established to provide a suitable functional range of arc signals. high frequency for subsequent signal processing operations Resistor 252 provides temperature compensation allowing the detector to operate at higher temperatures than room temperature without losing accuracy. The operational amplifier 250 also functions as a buffer, producing a low impedance source for the series-connected filter built around the operational amplifier 264. This filter comprises a two-pole active high-pass Chebychev filter with a cutoff frequency of about 500 KHz. This filter provides an attenuation of the signals lower than 500 KHz, preventing this way that the communication signals of the energy line carrier present on the alternating current line (which could reach frequencies as high as 400 KH (interfere With the detection of arc faults, the filter is constructed from the capacitors 256, 258, the resistors 262, 260, and the operational amplifier 264. The resistor 266 is used for temperature compensation.The output of the Chebychev filter a full-wave rectifier 192 is inserted, which can rectify input voltages in the millivolt range E rectifier 192 comprises an operational amplifier 272 by which the positive input of the operational amplifier is maintained to ground by the resistor 270. The diodes 276, 278 provide the rectification of the signal Due to the feedback by means of the resistor 274, it does not reach a loss in the signal. Resistors 268, 27 define the gain of rectification stage 192. The output of the pulse-frequency direct current signal of the full-wave rectifier 192 is input to an amplifier 194 comprising the operational amplifier 282 and the resistor. 280. The amplifier 194 functions as a voltage follower or impedance matching damper, which provides a low resistance source for the arc current signal which is representative of the current level of the arc current on the alternating current line. . The arc current signal is the voltage of the signal processed in high frequency, which contains all the peaks and valleys of the original signal. If this voltage is too high, the device will trip the relay. The output of the amplifier 194 is inserted into the integrated 196, which functions to generate a signal representative of the level of the average peak arc current present in the alternating current line. The integrator preferably has an integration time of approximately 100 milliseconds The output of the damped signal from the full-wave rectifier 192 is smoothed and the resistors 288 are averaged by means of the diode 284., 286, and the capacitor 290. The resistor 28 and the capacitor 290 are large enough to smooth the rapid fluctuations of the ait frequency arc signal, and convert them to a slower direct current d level suitable for the detection circuit d arc 198 (Figure 6). The resulting averaged arc current signal is output by voltage / buffer follower 292. A schematic diagram illustrating the portion of the alternating current line circuit circuitry of the arc fault detection device is shown in Figure 12. of the present invention in greater detail. In contrast to the high frequency circuit 188 of FIG. 16, the alternating current line frequency circuit 200 of FIG. 1 performs low pass filtering. The low pass filter input LC network 202 comprising the capacitor 302 and inductor 300, functions as a low pass filter. The frequencies lower than 500 Hz pass a negligible attenuation. At these frequencies, the inductor 300 is virtually a short circuit, and the capacitor 302 has a high impedance. At frequencies greater than 500 Hz, the inductor 300 is of high impedance, and the capacitor 302 has a low impedance, thereby severely attenuating any high frequency content in the input signal. The resistor 240 (FIG. 11) also prevents this second network L from resonating as well. The output of the LC network is put into an amplifier constructed from the operational amplifier 308 and the resistors 304, 306, 310. The gain of the operational amplifier 308, defined by the resistors 304, 306, s set such that the circuit AC line frequency 200 provide one volt per 10A which flows over the AC power line. This precise ratio of the current to the voltage allows the circuit to detect precisely and reject the low level arc produced by the common devices connected to the AFCI / GFCI device. The resistor 310 provides a temperature compensation in a manner similar to the resistor 252 (FIG. 11). The circuit of the operational amplifier 308 also functions as a damper, producing a low impedance output source for the filter built around the operational amplifier 322.

The filter coupled in series with the operational amplifier circuit 308 is a Chebychev low-pass, active, two-pole filter with a cut-off frequency of about 500 Hz. The use of an active filter provides a much sharper cut of high frequencies. The low-pass filter is constructed from resistors 312, 316 320, the capacitors 314, 318, and the operational amplifier 322 The output of the Chebychev filter is inserted into a full-wave rectifier 204, which can rectify input voltages in the millivolt range. The rectifier 204 comprises an operational amplifier 330, by which the positive input of the operational amplifier to ground is maintained by means of the resistor 329. The diodes 328, 332 provide rectification of the signal. Due to the feedback via resistor 326, there is no loss in the signal. The resistors 324, 32 define the gain of the rectification stage 204. The low frequency direct current signal and pulses output by the full wave rectifier 204, s put an amplifier 206 comprising the operational amplifier 336 and the resistor 334 The amplifier 206 functions as a voltage follower or an impedance coupling damper, which provides a low resistance source for the AC line current signal which is representative of the peak level of the AC line current. on the power line that is monitoring the AFCI / GFCI device. The alternating current line signal is the voltage of the signal processed at low frequency, which contains all the peaks valleys of the original signal. If this voltage is too high, the device will trip the relay. The output of the amplifier 206 is inserted into the integrated 208, which operates to gete a signal representative of the level of the average pic AC line current. The integrator preferably has a integration time of approximately 100 milliseconds. The damped signal output from the full-wave rectifier 204 is smoothed and averaged over the mean of the diode 340, the resistors 338, 342, and the capacitor 344. The resistor 338 and capacitor 344 are large enough to smooth the fluctuations of the signal frequency of alternating current line, and converting them to a direct current level d slowest movement suitable for the detection circuit d arc 198 (Figure 6). The capacitor 344 is slowly discharged by the resistor 342. The resultant averaged arc current signal is output by the voltage / buffer follower 346. The resistors and capacitors in the averaging circuit 208 are preferably chosen to attenuate the geted signals by the input currents of typical household appliances, which contain, for example, electric motors, incandescent lamps, and power and switching supplies. The input currents geted by this apparatus produce a voltage peak of short duration which decays very rapidly after the apparatus is activated. Accordingly *, the AC line frequency circuit 200 produces two signals, the first signal being proportional to the alternating current line current flowing in the power line, and the second signal being proportional to the current of the line. average alternating current line flowing in the ey line. The alt frequency circuit 188 also produces two signals, the first signal being proportional to the peak current of the frequency components above 500 KHz (with the frequency plus alt limited by the physical characteristics of the components of the operating amplifiers used), and the second signal being proportional to the average current of the frequency components above 500 KHz. The four signals are used by the arc detection circuit 19 (Figure 6), to allow the AFCI / GF_C device to react appropriately to a wide range of dangerous conditions. The use of the four signals also allows the device to bypass the input currents and noise typically geted by household appliances, even if it reliably detects dangerous arc conditions.

Alternatively, it is possible to remove the initial passive LC type filtration or active filtration. (operational amplifiers), and still provide sufficient filtering of the alternating current line frequency signal, and of any high frequency arc signals for the device to work as intended. It would also be a consideration to ensure the attenuation of any signals in the frequency bands used for energy line carrier communications. In Figures 13A, 13B and 13C, schematic diagrams are shown illustrating the portion of the arc detection circuit of the arc fault detection device of the present invention in greater detail. The arc detection circuit works to generate two disparate signals called TRIG_ARC and TRIG_AVG. The generation of the first TRIG_ARC signal will be described first. With reference to Figure 13A, the arc-sensing circuit operates to detect when the alternating current line frequency current, or the peak frequency arc current, is above a predetermined threshold, which has been determined as insecure. The alternating current line frequency current pic from the alternating current line frequency circuit 200 (FIG. 12) is smoothed by resistor 350 _ and capacitor 352, before being inserted into comparator 358. The minus input of the comparator is the output of a voltage divider qu serves as a reference voltage. Resistor 354 and e vessel 356 form the voltage divider. This reference voltage is set to a value representing the highest permissible peak AC line current on the AC line. Preferably, the highest allowable peak AC line current is 10 A. When the peak voltage of the alternating current line is higher than the set threshold, the normally low output of the comparator 358 will go high. If the other inputs to gate OR (or) 360 were previously low, then comparator 358 going high, causes the TRIG-ARCA signal to go high. This, in turn, causes the SCR trigger circuit 236 (Figure 7) to trip the SCR, open the relay, disconnecting the power to the load. This circuit is particularly useful for detecting short-term dangerous arc, where an appreciable charge current is flowing through the arc and energy line, such as when an extension cable is cut across the sharp edge of a power paw. metal chair In a similar manner, the peak frequency current from the high frequency circuit 18 (FIG. 11) is smoothed by resistor 366 and capacitor 368, before being entered into comparator 370. The minus input of the comparator is the output of a voltage divider which serves as a reference voltage. Resistor 362 and e vessel 364 form the voltage divider. This reference voltage is stable at a value representing the highest peak high frequency arc current permissible on the AC line. When the peak voltage of the frequency is higher than the set threshold, the normally low output of the comparator 370 will go high. If the other inputs to gate OR (or) 360 were previously low, then comparator 370 going to high, causes the TRIG_ARC signal to go high. This, in turn, causes the SCR trigger circuit 236 (Figure 7) to trip the SCR, open the relay, disconnecting the power to the load. This circuit is particularly useful for detecting short-term dangerous arc, where an appreciable charge current is flowing through the arc and energy line, such as when an extension cable is cut across the sharp edge of a power paw. metal chair The comparator circuits of the alternating current line peak and peak frequency frequency d are preferably constructed in such a way that the relay in e AFCI / GFCI fires within about three cycles of alternating current, that is, 40 milliseconds, when s detect 100 A of arc and / or of overcurrent conditions d line of alternating current. This level of triggering speed detection is called Level 3 priority. The other two levels, Levels 2 and 1, are of low priority, and consequently, it takes more time before the relay releases. The rapid response associated with the arc and overcurrent situations of priority of Level 3, is achieved by using the output of peak voltages from the alternating current and high frequency d circuits, instead of the average voltages. This provides an instantaneous trip reaction to excessive inrush currents. And addition, it also provides an extra margin to detect very large arcs, since these have a large component of alternating current line frequency, and a sufficient amount of energy to start a fire very quickly. The novel approach to the detection of arc used in this invention provides a rapid response to a wide range of dangerous scenarios. The device uses the two comparators 358, 370 pair to quickly deactivate the AC power to the load in the following three different situations: (1) when the line has high arc levels, (2) when the line current of peak AC current exceeds the capacity of the line, and (3) when the line is overloaded due to excessive arc. The normal input currents associated with motors and incandescent bulbs, for example, although of a short duration, can be very high. In Figure 4 s shows a graph illustrating the magnitude of the input current versus time for an incandescent lamp. S connected a 15 A incandescent load to the AFCI / GFCI load side, and the input current was measured. A peak inlet current of approximately 13 OA was measured. This peak input would normally generate enough voltage to trigger the AFCI / GFCI. However, capacitors 352 and 36 (Figure 13A) generate a time delay. The values of the capacitors 352, 368 are selected to provide a time delay of approximately 25 milliseconds for the comparators 258, 370, respectively. As can be seen in the graph of Figure 14, after about 1 millisecond, the peak current has dropped below 80A. This time delay prevents false triggering by input currents, since comparators 358, 370 are set to fire within 40 milliseconds in a load current d 100 A. The next lower priority level, Level 2 is associated with the high average arc, that is, the average alternating current line frequency current or the average high frequency arc current greater than 1. times the nominal value of the * AFCI / GFCI. At this priority level, the comparator circuit of preference is such that the relay in the AFCI / GFCI device will trip within 10 milliseconds. Note that the user can not disable the arc detection at the priority of Levels 2 and 3, and it is desirable that the AFCI / GFCI device always trip in the presence of conditions that are determined to be dangerous. The circuit used to implement the Level 2 priority will now be described in more detail. With reference to Figure 13B, the average alternating current line current from the alternating current line frequency circuit is inputted to the most input of the comparator 408. A voltage reference source is inserted at the lower input of the comparator 408. The reference voltage is generated by means of vessel 375 and operational amplifier 376 which forms a voltage regulating circuit. The d voltage regulating circuit provides the adjustable reference voltage for a resistive divider network comprising the resistors 398, 400, 402, 404, 406. The values of the resistors are selected to create multiple reference levels of the line frequency current. of average alternating current, for example, 30, 20, 10, 5, and 2.5A. The reference voltage created in the negative input to the comparator 408 corresponds to an average alternating current of 30A over the alternating current line. Accordingly, if the level of the detected average AC line current is greater than 30A, the output of comparator 408 goes high, causing the output of gate OR (or) 422 to go high. The output of the gate OR (or) 422 is put into the gate OR (ó) 360, which works to produce the TRIG_ARC signal to the SCR trigger circuit. In a similar manner, a voltage reference source d is input to the negative input of the comparator 390. The reference voltage is generated by the vessel 37 and the operational amplifier 378, which forms a voltage regulator circuit. The voltage regulator circuit provides the adjustable reference voltage for a resistive re-divider comprising the resistors 380, 382, 384 386, 388. The values of the resistors are selected to create multiple reference levels of the arc current for example, dangerous, high, medium, and low. The reference voltage d created at the negative input to the comparator 39 corresponds to a dangerous arc level. Accordingly, if the level of the average high frequency current detected is above this level, the output of the comparator 390 goes high, causing the output of the gate OR (or) 422 s to go high. The output of gate OR (or) 422 is inserted into gate OR (ó) 360, which operates to produce the signal TRIG_ARC to the SCR trigger circuit. The two comparators 390, 408 are configured to produce a high output in the presence of unsafe conditions. They are connected through the OR gates (ó) to the SCR trigger circuit that controls the AFCI / GFCI relay. This provides a priority trip of level 2 with a trip time of approximately 100 milliseconds. This rapid trip can not be disabled or delayed by the user, as is the case with the detection of the priority of Level 1. The output of the comparator 390 goes high if the unsafe arc persists for approximately 100 milliseconds while the output of the comparator 408 goes high if the total average current exceeds 30A for a time d approximately 100 milliseconds, ie, six cycles of alternating current. An average alternating current line current of 30A indicates that the safe supply of AFCI / GFC through the current capacity is being exceeded by 50 to 100 percent. Note that typical GFCIs have a nominal value for 15 to 20A of alternating current feed through the current. When these circumstances occur, the energy to the load is deactivated. It was observed that the average AC line and the high frequency signals are used as inputs to reduce the sensitivity of the AFCI / GFCI trigger action to the current waveform or its frequency. Therefore, the type of arc detected or the type of load energized through the AFCI / GFCI does not affect the ability of the device to trip when dangerous conditions occur. The comparator 390 reacts to the high frequency currents while the comparator 408 reacts to the alternating current line frequency, ie, 50 or 60 Hz. The output of comparator 408 goes high when the average current exceeds 30A on the AC power line. In this way, the device provides an overcurrent protection against continuous overload, as well as protection against excessive peak currents. exceed 100A for more than two to three AC cycles. The arc detection circuit also comprises two banks of comparators, one associated with the average AC line current, and the other associated with the average high frequency arc stream. Tre comparators 410, 412, 414 have their negative inputs derived to different reference voltage levels generated by the resistor divider 398, 400, 402, 404. The positive input of each comparator is coupled to the voltage of the average AC line current. The values of the resistor are selected in such a way that the output of comparator 410 goes high when the line current of average alternating current exceeds 20A, and the output of comparator 412 goes high when the line current of alternating current average exceeds 10A, and comparator output 414 goes high when the average AC line current exceeds 5A. As described above, the output of comparator 408 will go to alt when the average alternating current line current exceeds the dangerous 30A level. The average AC line current signal is fed to the comparators 408, 410, 412, 414 through the diode 372. A capacitor 418 provides additional smoothing of the average AC line current signal, and the resistor 420 ensures that capacitor 418 is discharged when the average AC line current decreases. Additional feedback resistors can be added to the positive inputs of the comparators, to provide hysteresis, thus reducing oscillations. In a similar manner, the arc detection circuit comprises comparators 392, 394, 396 for detecting different levels of average arc current on the line. The negative inputs of each of the comparators are coupled to different leads in the voltage divider, which comprises the resistors 380, 382, 384, 386, 388. The values of the resistors of the voltage divider are calculated to switch the output of the comparator 396 to high, when the average arc current level exceeds a "low" level. A "low" arc level is defined as the minimum arc level required to start a fire. The output of comparator 394 goes high when the average arc current exceeds a "medium" level. The output of comparator 392 goes high when the average arc current level exceeds a "high" level. As described above, the output of comparator 390 goes high when the average arc current level exceeds a level considered "dangerous under any circumstances." A "dangerous" level is defined as the amount of arc that would result average arc current 30 A. The average arc current voltage signal s feeds the comparators 390, 392, 394, 396, through diode 374. The capacitor 446 provides additional smoothing of the average arc current signal , and resistor 448 provides a discharge line for capacitor 446. Additional feedback resistors can be added to the positive inputs of one of the comparators, to provide hysteresis thus reducing oscillations. d alternating current and in the high frequency circuit which provides the input to the arc detection circuit, creates a delay of time approximately 85 to 100 milliseconds The time delay prevents the relay from firing and disconnects the power during a current input, which always occurs when the inductive, capacitive or incandescent loads are activated (Figure 14). Alternatively, a purple trigger mechanism is provided for signals with a lower average arc. These signals have the priority of Level 1. Level 1 is the lowest priority, and the AFCI / GFCI will fire within 1 to 2 seconds at this arc level. In addition, the user has the option of delaying or preventing the trip due to the arch in Level 1, through the chronometer circuit described in more detail hereinafter. The user can also enable an audible warning device instead of triggering the AFCI / GFCI. Different levels of detection are provided by the two comparator configurations 390, 392, 394, 396, and 408, 410, 412, 414. The device can appropriately react at different levels of average AC line current and average arc current, by applying the output of the comparators to a logical circuit. In particular, comparators 392, 410 are associated with high level arc detection, comparators 394, 412 with medium level arc detection and comparators 396, 414 are associated with low level arc detection. These different arc levels produce a priority trigger of Level 1. Below a certain level of average arc current, an arc can be considered as not dangerous, because it has insufficient energy to start a fire. An example of a non-dangerous arc is a discharge of static electricity. The reference voltage provided to the comparator 396 by the voltage divider represents an average arc current level that contains the minimum amount of energy to start a fire. This is the lowest detection point, and has been determined experimentally by the analysis of many arc wave signatures. The reference voltage for comparator 414 d is set to 0.5 V. This voltage preference is calculated equal to the direct current voltage d of the average AC line current signal, when 5A of current flows on the load side of the AFCI / GFCI device. When the signal of the average arc current reaches the minimum level required to be dangerous, that is, the "low" level, the output of the comparator 396 becomes high. The output of comparator 396 is inserted into an input of gate AND (y) 444. The output of comparator 414 s reverses, gets into the second input of gate AND (and) 444. Therefore, the output of the gate AND (y) 444 is high only when a "low" arc level is detected, that is, minimum dangerous, and less than 5A flows in the load line. The reference voltage for comparator 412 d is set to one volt. This reference voltage d is calculated equal to the direct current voltage d of the average AC line current signal, when 10A of current flows over the load side of the AFCI / GFCI device. When the average arc current signal reaches the "medium" level, the output of the comparator 394 becomes high. The output of the comparator 394 is put into an AND gate (y) 426. The output of the comparator 412 is inverted and inserted into the second gate input AND (y) 426. Therefore, the output of the gate AND (y) 426 is high only when the "medium" arc level is detected, and less than 10A flows in the load line. The reference voltage for comparator 410 is preferably set at two volts. This reference voltage is calculated equal to the direct current voltage of the average AC line current signal when 20A of current flows on the load side of the AFCI / GFCI device. When the average arc current signal reaches the "high" level, the output of the comparator 392 goes high. The output of the comparator 392 is inserted into an AND gate (y) 424 input. The output of the comparator 410 is inverted and inserted into the second gate input AND (y) 424. Therefore, the output of the gate AND (y) 424 is high only when the "high" arc level is detected, and less than 20A flows in the load line. The following table summarizes the average arc required for the different priority trigger levels.

Note that the AC line current peak peak high frequency arc current greater than 10O will immediately trigger the device. This is a priority trigger of Level 3. The following Table only describes the average current firing levels.

Note that the arc detection circuit of the example of Figures 13A, 13B, and 13C is shown as comprising three levels of average arc current detection, ie, high, medium, and low, for illustrative purposes only. Higher or lower levels of average arc current detection are possible without departing from the scope of the invention. Alternatively, since direct current levels are involved that change relatively slowly, analog-to-digital converters could be used to digitize the average and high-frequency AC line signals for meters in a microcontroller. The microcontroller would suitably be programmed to generate an output dependent on the levels of the two input signals. The microcontroller could also perform a hysteresis function in the software for each level of detection. As described above, the output of one of the AND (y) gates becomes high only if the average detected arc current is greater than the allowed level for a particular level of line current of average AC. This also implies that, for each average AC line current level there is an average arc current level that is tolerated, for example, as a by-product of the particular load, such as vacuum cleaners, electric shavings, appliances d food processing, etcetera. These common devices have an amount of arc associated with their operation. The level of the arc signal produced by these devices is generally lower than the signal from an uncontrolled arc with the same current flow. Accordingly, because the arc detection circuit tolerates a specific amount of arc for each level d of the alternating current line, a false disparging of the device is prevented whenever these types of apparatus are used. The outputs of the AND (and) gates 424, 426, 44 are inserted into an OR gate (ó) 428. If any of the outputs of the AND gate (y) go to high, the output of the OR gate (or ) 428 goes high. The output of compuert OR (or) 428 is put into gate AND (y) 434. An additional comparator 416 is included in the arc detection circuit, to eliminate any fals trip due to noise on the alternating current line. The noise can be created by spikes generated by different sources of radio frequency, or electrostatic discharge, such as when someone walks on a dry nylon carpet touches the housing of a plug or extension cord. In addition, an apparatus such as an electric shaver can generate a substantial amount of arc noise, and yet consume a minimum current, thereby falsely firing the device. The comparator 416 causes s to ignore alterations of the above type, white noise, and light fading noise, etc., thereby increasing the noise immunity of the arc detector. The comparator 416 is in the lowest position on the totem post structure for the detection of the average AC line current. The reference voltage, placed at the negative input of the comparator, is established by the variable resistor 406. The comparator 41 operates to maintain the output of the gate AND (y) 43 low, when it is flowing less than a minimum current level to through the AFCI / GFCI. The output of the AN gate (y) 434 can only go to high if the average AC line current is above a minimum level In the example presented here, this level is arbitrarily set at 2.5A. Therefore, only arc faults that contain enough energy to start a fire will trigger the arc detector. As is well known, the electrical energy s represents P = I2R or VI, and therefore, as I approaches zero, the energy in an arc approaches zero Therefore, the energy becomes negligibly small, and can be considered a static arc. As an illustrative example, walking on a dry nylon carpet can produce static voltages as high as 50.00 volts, and nevertheless, the current only of about how many microamperes. Therefore, the total energy in the arc is in the range of mW, which is not enough to start a fire. The output of gate AND (y) 434 is input to the positive input of comparator 442 via resistor 43 and capacitor 432. Resistor 430 and capacitor 43 operate to generate a delay of 1 to 2 seconds. Small short live arcs that persist for more than 10 milliseconds, but are not continuous, usually not so dangerous. The delay of 1 to 2 seconds means that these intermittent arcs are ignored, for example, those caused by the opening and closing of the switches. The delay also provides greater immunity to noise from sources of short live noise or sporadic noise, such as d lighting controls. The output of comparator 442 goes high when the voltage on capacitor 432 exceeds the reference voltage set by divider 436, 438. The hysteresis e provided by resistor 443, which prevents it from oscillating and comparator. The comparator 442 also functions as a buffer for the following stages. The comparator output 442 is inserted into the chronometer circuit and the local / remote inhibition circuit. In addition, the comparator output 442 can optionally be input to an audible alarm 440, which may comprise a bell or other type of well-known audible alarm device. Optionally, a user-controlled switch may be connected to the output of comparator 442, to provide the option to activate the audible alarm, indicating an arc fault of priority of Level 1, or to trigger the device by means of chronometer circuit described later in the present. A problem associated with the AFCIs of the prior art is that they fire in an annoying manner when they use equipment or apparatus that produces heavy arc-type signals, for example, arc welders. The present invention comprises a chronometer circuit 186 (Figure 6 which functions to temporarily disable detection of arc faults for a period of time such as minutes or even hours.) The detection of any arc during the time the output is disabled. of the detector, extends the disabling period for a time equal to the total time the arc is detected, therefore if the arc detection is disabled for 1 hour and 1 minutes, and an arc is detected during that time , the detector becomes enabled 1 hour and 10 minutes later, thus, the arc detection can remain disabled for longer periods of time, thus allowing uninterrupted use by the user of the device equipment. shows in greater detail a schematic diagram illustrating the portion of the chronometer circuit of the arc fault detection device of the present invention. The function of the chronometer circuit 18 is to generate a low active INHIBIT signal, which enters with the TRIG_AVG signal output related to the priority of Nive 1, by means of the arc detection circuit. The INHIBIR signal is generated by a 506 timer, and is normally high. The INHIBIR signal enters with the signal of TRIG_AVG by means of the AND gate (y) 516, to generate the signal d TRIG_CRONOMETER. The TRIG_CRONOMETER signal is then inserted into SCR trigger circuit 236 (Figure 7). Since the exit of the stopwatch is normally high, the TRIG_AV signal is normally enabled, so that the relay can be triggered. The application of an active high pulse to the input d RESET of the stopwatch, starts the stopwatch work. When a pulse is applied to the reset input, the INHIBIT signal is lowered, until the chronometer count reaches a specified number of clock cycles. During the time the INHIBIT signal is low, the TRIG_CRONOMETER signal is disabled. After the stopwatch has been disabled, the INHIBIR signal returns to its active high state. The 50 or 60 Hz phase conductor of the alternating current line serves as the clock source for the chronometer 506. The chronometer comprises a zero detection element, well known in the art, for detecting crwave alternating current that forms the signal d clock entry timer. Inside the timer, the 50 or 60 Hz high-voltage sine wave is converted to a low-voltage square wave of the same frequency. The stopwatch also comprises a counter element, such as a plurality of Johnson counters. The internally generated square wave is used as the clock input for the counters. By means of a suitable selection of the counter element, any period of time can be arbitrarily generated by means of the chronometer. For example, with AC power of 60 Hz, and a counter that divides by 216,000, the timer output returns to a high state one hour after resetting. A gate (not shown) separates the clock generator from the counters inside the chronometer. This compuert is controlled by an input labeled as DISABLED CLOCK, which is locked internally. When the CLOCK DISABLE is high, the clock is prevented from activating the counters. Therefore, the stopwatch is set to "pause" until the CLOCK DISABLE is removed. When the CLOCK DISABLED input is returned to active low, the chronometer resumes the count from the point where it paused The chronometer also includes an entry RESTORE. An active high impulse at the entrance d RESET, forces the stopwatch output, that is, the INHIBIT signal, to low, and sets all counter records to zero. The preferred stopwatch is resettable tip, that is, it can be started from zero at any time, including during the count. A high continuous asset in the RESET input, will keep the counter at zero, and therefore, will keep the signal d INHIBIT permanently low. When the INHIBIT signal is high, the TIMER CLOCK DISABLED input is raised to high by the output of the OR gate (or) 502. This prevents the chronometer from counting additionally, and locks the stopwatch in an output state. high. As described above, the detection of a priority arc of Level 1 will extend the disabling period. Assuming that the INHIBIT signal is low that is, the stopwatch is counting, a TRIG_AV signal will produce a high signal at the output of the DISABLE CLOCK timer through the OR gate (or) 502. Therefore, the stopwatch makes a pause during the period of time when the TRIG_AVG signal is high. This means that the restoration of the TRIG_CRONOMETER signal is delayed by the amount of time in which the TRIG_AV signal is high. If the chronometer is not counting, that is, the INHIBIT signal is high, then the TRIG_AVG signal has no effect on the stopwatch. This method of delaying the chronometer is used to ensure that the TRIG_CRONOMETER signal is always rehabilitated even when the arc starts while the chronometer is counting. The priority arc of Level 1 is intermittently, since there is not enough energy to hold the arc for long periods. Therefore even when the priority arc of Level 1 starts while the timer is counting, the counter will still increase during arc holes, and arc detection will be enabled at some point after the arc is initiated. Therefore, the chronometer circuit significantly reduces the trip due to a standard arc generated by the equipment and devices, while ensuring that the GFCI / AFCI eventually trips in the presence of arcs. Note that arc formation is never disabled at Priority Levels 2 and 3. While the stopwatch is counting, the INHIBIT signal is low, thus disabling the TRIG_CRONOMETER signal. A light emitting diode (LED) 51 is connected to the output of the timer 506. The light emitting diode is also connected to the power supply Vcc by means of a current limiting resistor 510. When the INHIBIT signal is low the emitting diode light is turned on, indicating that arc detection has been temporarily disabled. When the INHIBIT signal is high, the light emitting diode is extinguished indicating that the arc detection is enabled.

Three signals are combined to form the signal RESETTING: INH_A, INH_B and INH_C. These three signals enter together through the gate OR (or) 508, to generate the input of the RESTORE signal to the RESET input of the 506 timer. Therefore, if INH_A, INH_B, or INH_C goes high, it will be reset the chronometer the three signals inserted to the OR (or) 508 s gate will now describe in greater detail. The timer can be reset by a user by pressing the momentary pushbutton switch 498 The INH_A signal, which is normally lowered through resistor 500 bonded to ground, becomes momentarily high active. An alternative is to group switch 498 with the mechanism of switch that provides the test pulse for the GFCI circuit. The arc detection is then disabled for a predetermined period of time, when the GFCI is tested. In other words, the GFCI test before an appliance such as a vacuum cleaner, is used in the home, to make sure that the device will not trigger when the vacuum cleaner is used. Arc detection is automatically enabled a stopwatch period after s disconnect the use of the arc generating device. As described above, the chronometer output is normally high, allowing detection of the arc. An alternative is that the INHIBIT signal goes to alt immediately when the energy is first applied to the AFCI device. An alternative is for the timer to reset when the power is applied. A third preferred alternative is that the INHIBIT signal is lowered for a few cycles of alternating current, for example 1 second, and then allowed to become active high. This produces greater immunity to noise, since the AFC circuit will ignore the transients associated with the applied energy. Moreover, the AFCI is not inhibited for a long period of time unnecessarily. In situations where arc-generating machinery is used throughout the day, such as in a factory with arc welding equipment, the detection of arc faults is only practical at night. Consequently, the AFCI would be disabled during the day and would be enabled at night. A photocell of cadmium selenide or 522 photoelectric cadmium sulfide is provided to inhibit the priority arc faults of Level 1, so that the device does not fire. The photocell 522 is connected to Vc by means of the resistor 520. During daylight hours the photocell resistance falls to a very low value creating a low at the input to the inverter 518. The inverter output INH_C becomes high, causing the RESET input of the stopwatch so that it goes high. The TRIG_AVG signal is unhabitable, so that it does not trigger the device. Conversely, at night or in the absence of light, the resistance of the photocell 522 rises to a high value, causing the input to the inverter 518 to go high. The output of the inverter becomes low, removing the INH_C signal by enabling the stopwatch and allowing it to fire and stop detector. Note that, in the absence of light, the resistance of a cadmium selenide photocell can be raised to 100 MO or more. A third source, INH_B, is also inserted for the RESET input to the OR gate (ó) 514. This INH_B signal is generated by the local / remote inhibition circuit that will now be described in greater detail. In Figure 16 s shows in more detail a schematic diagram illustrating the portion of the local / remote inhibition circuit of the arc fault detection device of the present invention. The local / remote inhibition circuit 18 comprises the circuit which also inhibits the TRIG_AVG signal so that the device does not fire. The local / remote inhibition circuit 184 can be constructed as an integral part of AFCI / GFCI device, or it can be built in its own external housing, and can be connected to the main mode by a plurality of wires. The local / remote inhibition circuit works to activate and deactivate the device by means of the momentary pressure button, to activate and deactivate the AFCI by means of an infrared receiver, to activate and deactivate the AFCI by means of a signal from any suitable communication element. , send a signal by means of any suitable communication element, indicating the presentation of an arc fault, to a remotely located receiver. The infrared (IR) reception is achieved through the infrared detector 470, which may comprise an infrared diode operating to pick up the pulse signal from an infrared transmitter 454. The transmitter may comprise a fixed transmitter, or, in the alternative, any remote control of television or stereo that emits infrared impulses modulated by a frequency in the scale of 30 to 45 KHz. A receiver diode in the infrared detector 470 changes its impedance upon receiving the infrared pulse energy. Capacitor 472 passes these pulses through it to resistor 474, while blocking the direct current. This limits the sensitivity of the device to any constant or slowly changing light level, for example, daylight. The pulsed direct current through the vessel 474, charges the capacitor 478 through the diode 476. The resulting direct current level is put into an optocoupler 482. The current flowing to the optocoupler input causes its output to high. The output of the optocoupler is inserted into an OR gate (ó) 490. A high output of the optocoupler causes the output of the OR gate (ó) to go high. The output of the gate OR (or) 490 is inserted into a lever circuit 492. The lever lever 492 operates in one of two alternative modes selected by the user. In the first mode, the levering circuit 492 operates to pass its output from low to high, and from high to low, on each transition from low to high of its input. In the second mode, the lever circuit 492 operates to produce a high active pulse on each low to high transition of its input. The output of the lever circuit 492 forms the signal INH_B, which is inserted into the OR gate (ó) 508 (Figure 15). In the first mode of the levering switch, the signal INH_B remains high, until another input to the levering circuit is presented. The arc detector is disabled, until the local / remote inhibition circuit releases the signal INH_B. In the second mode of the leverage switch, the INH_B pulse resets the timer, but is automatically enabled in AFCI after the previously determined time period. The state of the output of the local / remote inhibit circuit is indicated by the light emitting diode 496, which is connected to INH_B by means of the resistor 494. In the first mode of the leverage switch, the light emitting diode d indicates that the AFCI is being disabled by a remote element. In the second mode of the leverage switch, a flash of the light emitting diode 496 indicates that a reset pulse has been sent to the timer 506 (Figure 15). In addition, the circuit 184 also comprises a circuit to enable a user to reset the timer or permanently disable the AFCI / GFCI device from a remote location. One end of the momentary pressure button switch 484 is connected to ground, and the other end is connected to a debounce circuit 488. The input to the debounce circuit 488 is brought up by resistor 486 linked to V , ce 'The output of the des-bounce circuit is inserted to the OR gate (ó) 490. The rebreath circuit works to produce a low while the switch is open: 484. When the switch is closed, the output of the circuit de-bounce 488 goes high, causing the output of gate OR (or) 490 to go high, leaning the signal I H_B. The local / remote inhibition circuit 184 also comprises the ability to receive an on / off command, by means of a suitable communication element. For example, this communication element can comprise any energy line, radiofrequency, twisted pair or infrared line carrier communication technology. An example of power line carrier communications includes the Lon Works and CEBus communications systems. As an example only, the present invention comprises a power line carrier receiver 460, such as the CCS receiver manufactured by Leviton Manufacturing, Little Neck, New York, which operates to receive a signal transmitted over the power line, decode and interpreting the received command, and producing a signal to the optocoupled 464. The carrier signal of the CCS power line is modulated by a 121 KHz carrier. This signal is drawn from the alternating current line through the capacitor 450 and the coupling transformer 452. The capacitor 456 and the resistor 458 function to filter in high pass the input to the receiver 460. The output of the optocoupler 464 is put into the gate OR (or) 490. Accordingly, a high output of the optocoupler 464 causes the output INH_B of the lever circuit 492 to change state. In addition, the present invention comprises a communication element, for example, a power line carrier transmitter 462, for transmitting the arc fault information to a remotely located receiver, signaling the location of the fault. Other types of communications may be used to replace the power line carrier, without departing from the scope of the invention. A dedicated dashboard can be connected to remove the receiver where the arc fault information is monitored by the construction personnel. This characteristic is desirable in commercial industrial facilities, such as schools, supermarkets, etc., where the electrical system is centrally supervised. The TRIG_AVG signal from the arc detection circuit is inserted into the damper 468, whose output is smoothed by the capacitor 466. The output of the damper 468 is inserted into the transmitter 462, which operates to generate an output signal based on the state of TRIG_AVG. Although the arc may cease or may be intermittent, the capacitor 466 maintains sufficient charge to keep the transmitter 462 activated for sufficient time to transmit the required information through the alternating current line. The transmitter 462 comprises an energy transistor element for transferring the output of the transmitter onto the alternating current line by means of the phase and neutral terminals on the line side. Note that both the connection, phase line and neutral, and the indicator board, are located upstream of the AFCI / GFCI, so that they do not disconnect in the event that the device is triggered. In addition, it is noted that, even when the timer has been triggered, temporarily inhibiting the TRIG_AVG signal, nevertheless the presentation of an arc fault to the remote indicator is transmitted by means of the transmitter 462. It is desirable to have an indication of a failure of the transmitter. arc, even when generated from the equipment or devices. Alternatively, the signal TRIG_CRONOMETER can be inserted into transmitter 462, thus preventing the notification of arc faults while the signal INHIBIT is low. As discussed above, the arc detector of the present invention can be used as an independent arc fault detector, or combined with other types of circuit breaker devices in addition to a GFCI. When used as a stand-alone device, the AFCI / GFCI circuit of Figure 7 is modified to include only the circuit related to the arc fault. And in particular, the two related transformers GFCI 233, 234, and their related circuits, including the LM1851 IC 225, would be removed. The trigger circuit of SCR 236 will need only two inputs, namely TRIG_ARC and TRIG__CRONOMETER. The rest of the circuit would remain, that is, MOV, d-diode bridge, coil, power supply, relay switches, and so on. In addition to a GFCI, the arc detector may be combined with an Immersion Detection Circuit Interrupter (IDCI) device, which is explained in greater detail in U.S. Patent No. 4,709,293, issued to Gershon et al. , and titled SHOC HAZARD PROTECTION SYSTEM. This AFCI / IDCI combination device d will now be described in greater detail.

A description of the IDCI device of the prior art precedes a description of the AFCI / IDCI combination device. In Figure 17 a schematic diagram illustrating an IDCI of the prior art is shown. The circuit, generally referenced as 600, comprises a pair of immersive detection conductors 603, 620, which are placed in a non-conductive relationship within the electrical load, preferably in a place where water can enter. The circuit 600 comprises the SCR 612, capacitor 610, diode 614, capacitor 616, resistor 618, metal oxide varistor (MOV) 606, and relay coil 608. Relay 608 controls the opening of the normally closed relay contacts 602, 604 connected to the phase d and neutral conductors, respectively, of the alternating current line. In addition, circuit 600 comprises a power supply 605 connected between phase and neutral, which operates to generate Vcc to energize the circuit. A shock risk related to agu is keyed when both conductors by immersion detection 603, 620, are immersed in water. This causes the line voltage of alternating current to be connected to the gate of SCR 612. In response, the SCR activates and energizes coil 608, causing the switches 602, 604 to open, thereby disconnecting the AC power. from the electrical apparatus.

A schematic diagram illustrating the arc fault detector with the dip detection circuit breaker constructed in accordance with the present invention is shown in Figure 18. The circuit presented in Fig. 18 can be used in place of the AFCI / GFCI circuit of Fig. 7. The rest of the circuit, i.e. the local / remote inhibition circuit 184, the chronometer circuit 186, e high-frequency circuit 188, the alternating current line frequency circuit 200, and the arc detection circuit 198, as shown in Figure 6, remains the same.The circuit, generally referenced as 630, comprises a pair of conductors per detection of immersion 633 652, which are placed in a non-conducting relationship within the electric charge, preferably in a place where water can enter in. Circuit 630 comprises SCR 640, capacitor 637, diode 646, capacitor 648, the resistor 650 the MOV 636, and the relay coil 638. The relay 638 controls the opening of the normally closed relay contacts 632, 63 connected to the phase and neutral conductors respectively of the alternating current line. circus Figure 63 comprises a power supply 635 connected between neutral phase, which works to generate Vcc to energize the circuit. As in the prior art circuit of FIG. 17, a shock risk related to acu is detected when both conductors by immersion detection 633, 652 are immersed in water. This causes the AC line voltage 'to be connected to the gate of the SCR 640. In response, the SCR activates and energizes the coil 638, causing the switches 632, 634 to open, thereby disconnecting the current energy. alternating electrical device. The transformer 642 operates in a manner similar to the transformer 229 of the AFCI / GFCI circuit shown in Fig. 7. The transformer 642 generates a peak output voltage which is almost linearly proportional to the peak current flowing through it. The output of the transformer 642 forms the input to the high frequency circuit 188 and the alternating current line frequency circuit 200, as shown in FIGS. 11 and 12. The trigger circuit of SCR 644, which provides the gate signal for the SCR 640, works to isolate the different trigger signals from each other. The three inputs to the SCR 644 trigger circuit include TRIG_IDCI_, TRIG_ARC and TRIG_CRONOMETER. The trigger circuit of SC applies an OR function (ó) to the three inputs, by which, any of the three input signals that are active, will cause the SCR 640 to fire. In a manner similar to the GFCI and IDCI devices described above, one skilled in the electrical arts could modify a conventional ALCI to incorporate the arc fault detection circuit of the present invention. Although the invention has been described with respect to a limited number of embodiments, it will be appreciated that many variations, modifications, and other applications of the invention can be made.

Claims (52)

1. CLAIMS 1. An arc fault circuit interrupter (AFCI) device electrically connected to an electrical wiring system between a power source that includes phase and neutral conductors on the line side, and its load side including phase and neutral conductors comprising This device: a pair arc fault circuit element detecting the presentation of an arc fault that was present inside the electrical wiring system, operating this arc fault circuit element to generate an arc fault tripping signal in response to the detection of an arc fault; a trigger element for generating a switching signal upon receiving the arc fault trip signal; a switching element electrically connected in series between the phase and neutral conductors of the line side, and the phase and neutral conductors of the load side, the switching element being for disconnecting the source of electrical energy towards the phase and neutral conductors load side, in response to the switching signal.
2. 2. The device according to claim 1, further comprising a circuit breaker element for interrupting the flow of current to a load electrically connected to the device, in response to predetermined criteria. The device according to claim 2, wherein the circuit breaker element comprises a ground fault circuit interrupter element (GFCI), to detect the occurrence of a ground fault between the phase conductor and the ground, or between the neutral conductor and the ground, operating this circuit element for ground fault to generate a ground fault trip signal, and response to the detection of this ground fault. The device according to claim 2, wherein the circuit breaker element comprises a dip-sensing circuit interrupter element (IDCI). 5. - The device according to claim 2, wherein the circuit breaker element comprises a - circuit breaker element due to device leakage (ALCI). The device according to claim 1, wherein the arc fault circuit element comprises: a current measuring element for detecting the level of alternating current flowing through an electric load placed on the load side Of the device; a high frequency circuit element pair generating a peak high frequency signal, and an average high frequency signal, corresponding to the peak and average levels, respectively, of the high frequency current flowing through the load; an alternating current line frequency circuit element for generating a peak AC line frequency signal, and an average alternating current line frequency signal, corresponding to the peak and average levels, respectively, of the current Alternating current line frequency flowing through the load; and an arc detecting element for generating the arc fault trip signal according to the high peak frequency signal, the average high frequency signal, the peak ac line frequency signal, and the frequency signal of average alternating current line. The device according to claim 6, wherein the arc detection element comprises an element for generating the arc fault tripping signal, when the peak high frequency signal exceeds a previously determined first threshold, or the Peak AC line frequency signal exceeds a previously determined second threshold, providing the generation of this 'arc fault trip signal an immediate response to dangerous levels of arcing or current from the AC line. 8. The device according to claim 6, wherein the arc detection element comprises an element for generating the arc fault trip signal when the average high frequency signal exceeds a previously determined first threshold, or the average alternating current line frequency signal exceeds a second predetermined threshold, providing the generation of the arc fault firing signal an immediate response to the r dangerous levels of arcing or current of the alternating current line. The device according to claim 1, wherein the arc fault circuit element comprises an element for generating the arc fault tripping signal after a variable time delay that depends on the level of arc formation detected , or the AC line current level detected. The device according to claim 6, wherein the arc trigger circuit element comprises an element for generating the arc fault tripping signal based on a plurality of arc fault tripping levels, which depend on the magnitude of the average AC line current. The device according to claim 6, wherein the arc fault circuit element comprises an element for generating the arc fault tripping signal, based on a plurality of arc fault tripping levels, which depend of the level of the alternating current line current detected. 12. The device according to claim 1, which further comprises an element for simultaneously detecting the peak and average magnitude of the high frequency arc current and the alternating current line current, to provide an immediate response to dangerous levels in either arc formation or well in the current of the alternating current line. The device according to claim 1, which further comprises an element for partially disabling the arc detection for a finite period of time, providing the disabling of arc detection to a user, the ability to use an electrical device that exhibits arc formation, making this chronometer element possible for arc detection after the use of the electrical device has been discontinued. 14. The device according to the claim 1, which further comprises a communication element for communicating the generation of the switching signal. The device according to claim 1, which further comprises an element for receiving a disable command, and disabling arc detection in accordance with the same. 16. The device according to claim 1, further comprising an element for a user to manually activate and deactivate the arc detection. 17. The device according to claim 1, which also includes an element for disabling arc detection during daylight hours, and enabling arc detection during night hours. 18. The device according to claim 1, further comprising an element for disabling and enabling arc detection according to the signals received from a remote infrared (IR) transmitter. 19. An arc fault circuit interrupter (AFCI) device electrically connected to an electrical wiring system between an electrical power source that includes phase and neutral conductors on the line side, and a load side that includes phase conductors and neutral, this device comprising: an arc fault circuit element for detecting the presentation of an arc fault occurring within the electrical wiring system, operating this arc fault circuit element to generate a tripping signal Arc failure in response to the detection of an arc fault; a trigger element coupled to the arc fault circuit element, this element being triggered to generate a commutation signal upon receiving the arc fault tripping signal; a switching element electrically connected in series between the phase and neutral conductors of the line side, and the phase and neutral conductors of the load side, the switching element being for disconnecting the source of electrical energy towards the phase and neutral conductors on the load side, in response to the switching signal; and a timer * element for partially disabling the arc detection for a finite period of time, providing the disabling of the arc detection to a user the ability to use an electrical device that exhibits arcing, making this chronometer element possible Arc detection after the use of this electrical device has been discontinued. 20. An arc fault circuit interrupter (AFCI) device electrically connected to an electrical wiring system between a power source that includes line and phase neutral conductors, and a load side that includes phase conductors and neutral, this device comprising: an arc fault circuit element for measuring the level of the peak high frequency current and the peak alternating current line current current flowing through the device to an electrical load connected to the load side, operating this arc fault circuit element to generate an arc fault trip signal, when the peak high frequency current exceeds a previously determined first threshold, or when the current of the current line frequency alternating peak exceeds a second predetermined threshold; a trigger element for generating a switching signal upon receiving the arc fault tripping signal; and a switching element electrically connected in series between the phase and neutral conductors of the line side, and the phase and neutral conductors of the load side, the switching element being for disconnecting the source of electrical energy towards the phase conductors and neutral on the load side, in response to the switching signal. 21. An arc fault circuit interrupter (AFCI) device electrically connected to an electrical wiring system between a power source that includes phase and neutral conductors on the line side, and a load side that includes phase conductors and neutral, this device comprising: an arc fault circuit element for measuring the level of the average high frequency current and the average alternating current line frequency current flowing through the device to an electrical load connected to the side of load, operating this arc fault circuit element to generate an arc fault trip signal when the average high frequency current exceeds a previously determined first threshold, or when the average AC line frequency current exceeds a second previously determined threshold; a trigger element coupled with the arc fault circuit element, this element being triggered to generate a commutation signal upon receiving the arc fault tripping signal; and a switching element electrically connected in series between the phase and neutral conductors of the line side, and the phase and neutral conductors of the load side, the switching element being for disconnecting the source of electrical energy towards the phase conductors and load side neutral, in response to the switching signal. 22. An arc fault circuit interrupter (AFCI) device electrically connected to an electrical wiring system between a power source that includes phase and neutral conductors on the line side, and load side including phase conductors and neutral, this device comprising: an arc fault circuit element for measuring the level of the average high frequency current and the average alternating current line frequency current flowing through the device to an electrical load connected to the load side , operating this arc fault circuit element to generate an arc fault trip signal, using a plurality of trigger levels of the average high frequency current, based on the level d of the average alternating current line frequency a trigger element coupled with the arc fault circuit element, this element being triggered to generate a signal d and switching upon receiving the arc fault trip signal; and a switching element electrically connected in series between the phase and neutral conductors of the line side, and the phase and neutral conductors of the load side, the switching element being for disconnecting the source of electrical energy towards the phase conductors and load side neutral, in response to the switching signal. 23. The device according to claim 19, 20, 21, or 22, which further comprises a circuit interrupter element for interrupting the flow of current to an electrically connected load to the device, in response to predetermined criteria. 24. The device according to claim 23, wherein the circuit breaker element comprises a ground fault circuit interrupter element (GFCI), to detect the occurrence of a ground fault between the phase conductor and the ground, or between the neutral conductor and the ground, operating this circuit element for ground fault to generate a ground fault trip signal and response to ground fault detection. 25. The device according to claim 23, wherein the circuit breaker element comprises a circuit breaker element by immersion detection (IDCI). 26. The device according to claim 23, wherein the circuit breaker element comprises a circuit breaker element due to device leakage (ALCI). 27. The device according to claim 20, 21, or 22, which further comprises or element to partially disable the arc detection for a finite period of time, providing the disabling of the arc detection to a user, the capacity to use an electrical device that exhibits arc formation, enabling the chronometer element to detect arcing after the electrical device has been discontinued. 28. The device according to claims 20, 21, 22, which further comprises a communication element for communicating the generation of the switching signal. 29. The device according to claim 20, 21, or 22, which further comprises or element for receiving a disable command, disabling the arc detection in accordance therewith. 30. The device according to claim 20, 21, or 22, which further comprises or element for a user to manually activate and deactivate the arc detection. 31. The device according to claim 20, 21, or 22, which further comprises an element for disabling arc detection during daylight hours and for enabling arc detection during night hours. 32. The device according to claim 20, 21, or 22, which further comprises an element for disabling and enabling arc detection according to the signals received from a remote infrared (IR) transmission. 33. An arc fault circuit interrupter (AFCI) device electrically connected to an electrical wiring system between a power source that includes phase and neutral conductors on the line side, and its load side that includes phase conductors. and neutral, this device comprising: a current measuring element for detecting the level of current flowing through one of the phase or neutral conductors of the line side; a high frequency element for generating a high frequency signal corresponding to the high frequency current level detected by the current measuring element d; an alternating current frequency element for generating an alternating current line frequency signal corresponding to the level of the alternating current line frequency detected by the current measurement element; an arc detection element for generating an arc fault trip signal according to the high frequency signal and the alternating current line frequency signal; a trigger element for generating a switching signal upon receiving the arc fault tripping signal a switching element electrically connected in series between the phase and neutral line side conductors, and the phase and neutral conductors on the load side , the switching element being for disconnecting the electric power source to the load side phase and neutral conductors, in response to the switching signal; and a timer element for partially disabling the arc detection for a period of finite time, providing the disabling of the arc detection to a user the ability to use an electrical device that exhibits arc formation, making this chronometer element possible. Arc detection after s has discontinued the use of this electrical device. _ 34. An arc fault circuit interrupter (AFCI) device electrically connected to an electrical wiring system between a power source that includes phase and neutral conductors on the line side, and load side that includes phase conductors and neutral, this device comprising: a torque current measuring element detecting the level of current flowing through one of the phase or neutral conductors of the line side; a high frequency element for generating a high frequency signal corresponding to the high frequency current level detected by the current measuring element d; an alternating current frequency element for generating an alternating current line frequency signal corresponding to the level of the alternating current line frequency detected by the current measurement element; an arc detection element for generating an arc fault trip signal according to the high frequency signal and the alternating current line frequency signal; and a switching element electrically connected in series between the phase and neutral conductors of the line side, and the phase and neutral conductors of the load side, the switching element being for disconnecting the source of electrical energy towards the phase conductors and load side neutral, in response to the arc fault trip signal. 35. The device according to claim 34, which further comprises an element for partially disabling the arc detection during a period of finite time, providing the disabling of the arc detection to a user, the ability to use an electrical device. which exhibits arc formation, making this chronometer element possible for arc detection after the use of the electrical device has been discontinued. 36. The device according to claim 33 or 34, which further comprises a communication element for communicating the generation of the switching signal. 37. The device according to claim 33 or 34, which further comprises an element for receiving a disable command, and disabling the arc detection in accordance with the same. 38. The device according to claim 33 or 34, which further comprises an element for a user to manually activate and deactivate the arc detection. 39. The device according to claim 33 or 34, which further comprises an element for disabling arc detection during daylight hours, and enabling arc detection during night time hours. 40. The device according to claim 33 or 34, which further comprises an element for disabling and enabling the arc detection according to the signals received from an infrared transmitter (remote IR 41. The device according to the claims 33 or 34, which further comprises a circuit breaker element for interrupting the flow of current to a load electrically connected to the device, and response to previously determined criteria 42. The device according to claim 41, wherein the switching element The circuit consists of a ground fault circuit interrupter element (GFCI) to detect the presentation of a ground fault between the phase conductor and the ground, or between the neutral conductor and the ground, operating this circuit element due to earth fault. to generate a ground fault trip signal and response to ground fault detection. With claim 41, wherein the circuit breaker element comprises a circuit breaker element by immersion detection (IDCI). 44. The device according to claim 41, wherein the circuit breaker element comprises a circuit breaker element (ALCI). 45. In an arc fault circuit interrupter (AFCI) device connected to an electrical wiring system by means of phase and neutral conductors on the d-side and phase and neutral conductors on the load side, or method for detecting faults of arc and earth faults, the cua comprises the steps of:. detect the level of current flowing through one of the phase and neutral conductors of the d-line side; generate a high-frequency signal corresponding to the high-frequency current level detected; generating an alternating current line frequency signal corresponding to the current level of the detected alternating current line frequency; generate an arc fault trip signal according to the high frequency signal and the alternating current line frequency signal; generating a switching signal in response to the arc fault trip signal; and disconnect the power source to the phase and neutral conductors on the load side in response to the commutation signal. 46. The method according to claim 45 which further comprises the step of partially disabling the arc detection for a finite period of time providing the disabling of the arc detection to the user the ability to use an electrical device that exhibits training of arch, and enable the detection of arc after the use of the electrical device has been discontinued. 47. The method according to claim 45 which further comprises the step of communicating the generation d of the switching signal. 48. The method according to claim 45 which further comprises the step of receiving a disabling command, and disabling the arc detection in accordance therewith. 49. The method according to claim 45 which further comprises the step of providing the capability for a user to manually activate and deactivate the arc detection. 50. The method according to claim 45, which further comprises the step of disabling the arc detection during daylight hours, and enabling arc detection during the night hours. 51. The method according to claim 45, further comprising the step of disabling and enabling arc detection according to the signals received from a remote infrared (IR) transmitter. 52. The method according to claim 45, further comprising the steps of: detecting the presentation of a ground fault between the phase conductor and the earth, or between the neutral conductor and the ground; and generate a ground fault trip signal in response to detection of the ground fault.