MXPA98004239A - Phase modulation apparatus that effectively uses a storage unit in the form of or - Google Patents

Abstract

The present invention relates to a circuit that detects a ramp period that emits a signal Tc that indicates the start and end of each ramp period. The accumulators (106) and (107) of coordinates, respectively accumulate I alpha or Q alpha which take values of either +1 or -1 for data of two odd numbered bits and O for data of two bits numbered pairs of rectangular coordinates two-dimensional (Ialfa, Qalfa) and (Iá, Qá) cast alternately, corresponding to the symbol data. The data in the form of a response wave (or ascending / descending ramp waveform corresponding to the response waveform) of a digital low pass filter corresponding to the Tc signal and the outputs or outputs of the accumulators (106) and (107) which are the past history of the alpha I and Q alpha, are read alternately from a storage section (11

Description

PHASE MODULATION APPARATUS USING A WAVEFORM STORAGE UNIT EFFECTIVELY FIELD OF THE INVENTION This invention relates to a phase modulation apparatus for modulating the digital baseband signals with Phase Quadrature Displacement Manipulation (QPSK).

BACKGROUND OF THE INVENTION Currently, QPSK is widely used as a digital modulation method. For example, the RCR STD-28 standard for the Handyphone Personal System (PHS) stipulates that the displaced QPSK p / 4 should be used as a modulation method. The QPSK that includes the shifted QPSK p / 4 is a modulation method in which two data bits are transferred simultaneously when using the in-phase component (phase I) and the phase quadrature component (Q phase) of a carrier wave . Next, the description of the shifted QPSK p / 4 and the conventional shifted QPSK p / 4 modulation apparatus 600 is provided.

The displacement QPSK modulation apparatus p / 4 receives a baseband signal as serial data. The baseband signal is converted by means of a serial to parallel conversion into a symbol (Xk, Yk) which is a piece of data in parallel of two bits, where "k" represents a natural number, which indicates that "( X1 :, Y) "is the kth symbol. The symbol (X >:, Yj.) Is converted by a differential coding circuit into a quadrature signal (Ik. Qk) - This conversion is carried out based on the following formula: Formula 1 cos [? F (Xk, Yk)] - sin [? F Q "sin.?F (Xk, Yk)] cos [? F where? f (Xh, Yk) has the values shown in the following table: Table 1 The quadrature signal (It;, Qk) obtained in this way is passed through a low pass filter such that it has a limited band and to be converted into phase I and phase Q components. A modulation circuit provides the phase and quadrature phase components for a wireless circuit. Figure 1 shows symbols (Xk, Y) transformed over a two-dimensional I-Q coordinate. When focusing the movement of a signal point represented by a quadrature signal (ly,), it is found that the point of the signal becomes any of the signal points A-D and any of the E-H signal points alternately. As is evident from Figure 1, the signal points A-D are represented by a two-dimensional coordinate system represented by the vector Ia on the axis I and the vector Qa on the axis Q as the axes. Also, the E-H signal points are represented by a two-dimensional coordinate system represented by the vector Iß and the vector Qß as the axes, which are respectively equivalent to the vectors Ia and Qa rotated by p / 4. For example, suppose that a current baseband signal is a piece of information represented by the symbol point F. Then, "0" is given as its co-ordinate Ia, "0" as its coordinate Qa, "-i" as its coordinate Iß and "+1" as its coordinate Qß. Suppose that the coordinates of the kth symbol, using the four previous vectors are respectively Iu, Q, I, and Qk. Then, the quadrature coordinates of the k-th symbol I \ - and Q, are represented by Formulas 2 and 3 respectively. Formula 2 Formula 3 Thus, the signal I (t) of phase I and the signal Q (t) of phase Q emitted from the modulator circuit are represented by Formula 4 in which h (t) represents a response function in rectangular waveform used in the low pass filter. Formula 4 l (t) = S lk (t-kT) le-oo OO 1 OO = S IakH (t-kT) + - S IßIch (t-kT) 1 oo S Qßkh (t-kT) "2 * - Formula 5 oo oo 1 oo =? Q h (t-kT) + ~ S I» kh (t-kT) k- ~ -2 k- ~ 1 oo + - S Qflkh (t-kT) 2 k-- ~ Formulas 4 and 5 indicate that limiting the bands of quadrature signals I Qk can be achieved by limiting the bands of each term of formulas 2 and 3 Here, if it is assumed that in Figure 1, the symbol points AD are odd and the symbol points EH are even in order, the following formulas are given.

Formula 6 + l] Formula 7 0 (k = 2N + l) d Oßk ± 1 (k = 2N) Hence, I (t) and Q (t) are represented by the following formulas.

Formula 8 oo i oo K t) = h (t-2NT) 1 8 S Qfl 2Nh (t-2NT) V2 N "" ~ Formula 9 oo l oo Q (t) = S Qa2? + 1h. { t- (2N + l) T.}. + - N? 8 I fl 2 Nh (t-2NT) • v 2] _ oo As it is evident from the above formulas, of the symbols In, Q ", I, and Q which are four signal vectors I (t) and Q (t), I and Q can be represented by using only signals of odd symbols and Iß and Q | (; when using only signals of even symbols.) Figure 2 is a block diagram showing the construction of the conventional displacement modulation apparatus QPSK p / 4 The modulation apparatus QPSK p / 4 Displacement includes the input terminal 601, the symbol generator circuit 602, the transformation circuit 603, the synchronization generation circuit 605, coordinates accumulators 606, 607, 608 and 609, a first storage unit 610, a second storage unit 611, a third storage unit 612, a fourth storage unit 613, a subtracter 614, adders 615, 616 and 617, D / A converters 618 and 619, and output terminals 620 and 621. The circuit 603 of transformation n includes the differential coding circuit 604. The baseband signal to be modulated is introduced in series to the symbol generation circuit 602 by means of the input terminal 601. The symbol generation circuit 602 is obtained by means of a displacement recorder p / 4. The symbol generator circuit 602 receives a baseband signal with the clock timing CL1 provided by the synchronization generation circuit 605 and converts the received baseband signal by means of a serial to parallel conversion in a symbol. (Xk, Y), which is a parallel signal of two bits. The transformation circuit 603 receives the symbol (Xk, Yk) generated by the symbol generator circuit 602 with the synchronization of the clock CL2 provided by the synchronization generator circuit 605. The transformer circuit 603 operates, to generate a piece of 2-bit address data, a certain transformation based on the received symbol (Xy, Y) or a result of the differential coding. Transformation circuit 603 provides one bit of the two-bit address data piece for each of the accumulators 606 and 607 of coordinates with synchronization of the nons symbols and the other bit of the two-bit addressing data for each of the 608 and 609 coordinate accumulators with even symbol timing.

The differential coding circuit 604, if necessary, performs a differential coding using the received symbol (Xy, Yy) and the preceding symbol (X ^ -i, Y) with the synchronization of the clock CL2 provided by the circuit 605 of generation of timing. The timing generation circuit 605 generates timing signals for the entire modulation apparatus 600 QPSK p / 4 offset, based on a clock signal that has a frequency higher than that of the baseband signal. CLl is a clock signal that has the same frequency as that of the baseband signal. CL2 is a clock signal that has the same frequency as that of the symbol data. CL3 is a clock signal that has the same frequency as that of the symbol data and generates odd and even symbol timing. The timing generation circuit 605 generates elapsed time information of the periods of odd and even symbols and provides the information as a lower address for the first storage unit 610, the second storage unit 611, the third storage unit 612 and the > fourth storage unit 613. The accumulators of coordinates 606, 607, 608 and 609 are shift registers and convert in series and parallel to each of the addresses provided by the transformation circuit 603. The results by outputs of the 606 coordinate accumulators, 607, 608 and 609 are provided respectively for the first storage unit 610, the second storage unit 611, the third storage unit 612 and the fourth storage unit 613. The first storage unit 610 receives a result of the accumulator 606 of coordinates as a higher address and information of the elapsed time of the timing generation circuit 605 as a lower address. The first storage unit 610 pre-stores data in wave form corresponding to I coordinates (components I). The waveform data indicates the response waveforms of the low pass filter at time when ± is entered into the low pass filter with the odd symbol timing and a response waveform of the low pass filter when 0 is entered with the timing of the even symbol. Thus, the first storage unit 610 pre-stores a digital value corresponding to "SIa2N +? H,. {T (2N + 1T.)." In Formula 8. The second storage unit 611 receives a result or output of the accumulator 607 of coordinates as a higher address and information of the elapsed time of the timing generation circuit 605 as a lower or lower address The second storage unit 611 pre-stores the waveform data corresponding to the Q coordinates (Q components.) The waveform data indicates the waveforms of the low pass filter response at time when ± 1 is entered into the low pass filter with the timing of the odd symbol and a waveform in response when 0 is entered with the timing of the pair symbol Thus, the second storage unit 611 stores a digital value corresponding to "? Qa2N +? H {t- (2N + 1) T.}." In Formula 9. third unit 612 of storage receives an output or result from the accumulator 608 of coordinates as a higher address and information of the elapsed time of the timing generation circuit 605 as a lower or lower address. The third storage unit 612 pre-stores the waveform data corresponding to the I coordinates (I components) the waveform data • indicates 1 / V2 response waveforms of the low pass filter (in the present specification , square root of 2 is represented by 2) at the time when ± 1 is introduced to the low pass filter with the timing of the even symbol and a response waveform 1 / V2 when 0 is entered with the odd symbol timing. Thus, the third storage unit 612 stores a digital value corresponding to "S (l / V2) Iß2Nh (t-2NT)" in Formulas 8 and 9. The fourth storage unit 613 stores an output or result of the accumulator 609 of coordinates as a higher address and information of the elapsed time of the timing generation circuit 605 as a lower or lower address and stores the waveform data corresponding to the Q coordinates (Q components). The waveform data indicates response waveforms of the low pass filter at time when ± 1 is input to the low pass filter with the timing of the even symbol and a response waveform I /? / 2 when 0 is introduced with the odd symbol timing. Thus, the fourth storage unit 613 stores a digital value corresponding to "S (l / V2) Qp2Nh (t-2NT)" in Formulas 8 and 9. Subtractor 614 subtracts the result of the fourth storage unit 613 from the result of the third storage unit 612 to execute a subtraction of the third term of the second term in Formula 8. The addor 615 adds the results of the third and fourth storage units 613 and 614 to execute an addition of the second and third terms in Formula 9. Additionator 616 adds the output of the subtracter 614 and the result of the first storage unit 610, i.e., the first term of formula 8 and outputs the instantaneous value It) of the phase I signal in Formula 8. The adder 617 adds the result of the adder 615 and the result of the second storage unit 611, that is, the first term of Formula 9, and outputs the instantaneous value Q (t) of the phase Q signal in Formula 9. The D / A converter 618 converts the result of the additive 616 to the analog signal and outputs the analog signal via the output terminal 620 to a mixer that is not shown in the drawings. The mixer multiplies the result of the D / A converter 618 by the carrier wave. The D / A converter 619 converts the output of the adder 617 to the analog signal and outputs the analog signal via the output terminal 621 to another mixer that is not shown in the drawings. This mixer multiplies the result of the D / A converter 619 by means of the carrier wave which is introduced by means of a phase shifter. These two quadrature components of the carrier wave generated in this way are aggregated and emitted to a transmission circuit not shown in the drawings. As is clear from the foregoing description, a waveform corresponding to? IU h (t- (2N + 1) T}. ", Ie, the first term of Formula 8 and a response waveform corresponding to "? Qa2N +? H { T- (2N + 1) T.}.", That is, the first term in Formula 9, can be generated from the same data as the waveform. response wave corresponding to "S (1 / V2) Iph (t-2NT)", that is, the second term in Formulas 8 and 9 and a response waveform corresponding to "S (l /" v2) Q (! H (t-2NT) ", that is to say the term in formulas 8 and 9, can be generated from the same data in wave form This means that the first storage unit 610 and the second storage unit storage 611 of conventional QPSK modulation apparatus p / 4 stores the same filter data, it is the same with the third storage unit 612 and the fourth storage unit 613. In general, such storage units are obtained by ROM. However, increases in the number and capacity of the ROMs lead to an increase in the scale of circuits, which generates a problem in the cost and a disadvantage to obtain the circuits in LSI. Moreover, the transmission of the signal modulated with the previous construction with the burst transmission causes another problem in which the frequency band of the transmission signal expands due to a huge parasitic emission generated by a pronounced elevation of the transmission signal. A method for preventing the problem in which a certain ramp period is set or set before and after the transmission of the modulated signal is known, in such a way that the transmission signal rises and falls uniformly according to the envelopes in the ramp periods. This processing is known as ramp processing. In conventional ramp processing, the amplification factor of the transmission amplifier is increased or reduced uniformly, such that the level of the transmission signal falls and rises uniformly. However, it is difficult to change the amplification factor of the transmission amplifier, that is, to correctly change the level of the transmission signal according to the function selected as an optimum ramp waveform. Consequently, it has been difficult to carry out the ramp processing in an exact manner.

BRIEF DESCRIPTION OF THE INVENTION It is therefore an object of the present invention to provide a phase modulation apparatus which has a simple circuit construction by the effective use of storage units in the form of waves and which generates a modulated signal with which a transmission is possible. of exact burst. The above object is obtained by a phase modulation apparatus which includes: storage means for storing data in wave form including a plurality of waveforms used for the processing of elevation ramps, a plurality of phase waveforms used for the component I and the Q component of a plurality of transmission symbols and a plurality of waveforms used for the fall ramp processing; conversion means for converting each of the non-operational symbols for ramp-up processing, the plurality of transmission symbols, and the non-operational symbol for the fall-ramp processing in component I and the Q component in which the non-operational symbol for the ramp-up processing, the plurality of transmission symbols and the non-operational symbol for the ramp-down processing are provided in time series; means providing direction for alternately emitting during a symbol period the converted component I and component Q by the conversion means as the address of the storage means; separation means for extracting data from a waveform of the component I and a waveform of the component Q which are read alternately from the storage means and simultaneously emit the waveform of component I and the waveform of component Q; and combining means for combining the waveform of the component I and the result of the waveform of the component Q of the separation means in a symbol waveform. With such construction, the storage means can be used effectively as shown below. The ramp processing can be carried out very easily since the circuits for controlling the gain of a transmission amplifier are not required since the ramp-up waveforms and the ramp-down waveforms are read from the storage means respectively before and after the transmission data transmission section and the reading waveforms are combined in symbol wave forms by means of the separation elements and the combination elements. In addition, this construction has been successful in reducing the storage capacity since the same waveforms are used in the transmission section for the component I and the component Q when adjusting the means providing the direction and the separation means respectively before and after the storage media. The means providing the address of the prior phase modulator apparatus may include: means that generate timing to generate a first timing information which indicates which of a lifting ramp processing section, a transmission section and a processing section of drop ramp and a second timing information which indicates the period of the symbol used in each of the lift ramp processing section, the transmission section and the fall ramp processing section; selection means for alternately selecting, during a symbol period, the component I and the component Q converted by the conversion means according to the second timing information; and input means for inputting an address to the storage means, wherein the address includes a first partial address, which is the first timing information and a second partial address, which is an output of the selection means. The means providing address of the above phase modulation apparatus may include: a shift register I for accumulating the I components of a certain number of symbols converted by the conversion means or elements and emit the I components in parallel; and a shift register Q for accumulating the Q components of a certain number of symbols converted by means or conversion elements and outputting the components Q in parallel, wherein the selection means alternately selects a result or output of the shift register I and an output or output of the shift register Q. The separation means of the above phase modulation apparatus may include: first delay means for delaying the output or result of the waveform of component I of the storage means; and second delay means for delaying the output or result of the waveform of the Q component of the storage means, such that the second delay means are synchronized with the first delay means in the emission. Further, in a displacement QPSK modulation apparatus p / 4 obtaining the above object, the switching means alternately selects an output or result of the coordinate accumulation means I and an output or result of the coordinate accumulation means. Q according to a switching signal, which is faster than the time information and outputs an output or selected result. Also, a response waveform from a digital filter to a coordinate I input (or a corresponding waveform) and a response waveform from a digital filter to a Q coordinate input (or a waveform of corresponding ramp) can be generated in a similar process, based on the same response waveform of the digital filter. Thus, the lifting ramp means, the filter means and the falling ramp means can be used for the I coordinates and the Q coordinates. This means that the response waveforms of a digital filter at a coordinate input I and Q coordinates (or correspondingly ramp waveforms) can be emitted alternately with the frequency of the switching signal. The separation means separate the response waveforms from a digital filter to an I coordinate input and Q coordinates (or corresponding ramp waveforms) in two currents which respectively correspond to the I coordinates and the Q coordinates. Consequently, the displacement QPSK modulation apparatus p / 4 of the present invention has succeeded in reducing the number of storage units to half that of the conventional displacement modulation apparatus QPSK p / 4, which includes the means of filter for each of the I coordinate entries and Q coordinates to the filters. This indicates that the displacement QPSK p / 4 modulation apparatus of the present invention has such a construction as it reduces the number of circuits as a whole and makes it easier to obtain the entire apparatus on an LSI chip. Furthermore, it is possible to carry out the ramp processing between the sudden increase or burst elevation section and the fall section of the sudden increase or burst, since the reduction in the construction of the filter means allows the inclusion of the means which report the ramp period, the lift ramp means and the fall ramp means. This allows the present apparatus to accurately perform uninterrupted transmissions by having an embedded circuit for ramp processing, while the conventional shifting QPSK modulation apparatus p / 4 has this circuit externally.

Each of the lifting ramp means, the filter means and the falling ramp means of the present displacement modulation apparatus QPSK p / 4 may include an odd storage unit and an even storage unit, wherein the odd storage unit stores the data in the form of a digital filter response wave and also stores the data in the form of a burst rising ramp wave and data in the form of a burst falling ramp wave which correspond to each to the response waveform data of a digital filter, where the response waveform data of a digital filter is generated at a time when an I coordinate and a Q coordinate of an odd signal point are input to the digital filter when recognizing the notification signal of the ramp period, an output or result of the switching means and the time information as an address, wherein the unit of storage for storing the data in the form of a response wave of a digital filter and also stores the burst rise ramp waveform data and the burst fall rise waveform data which correspond to each to the response waveform data of a digital filter, where the response waveform data of a digital filter is generated at a time when an I coordinate and a Q coordinate of an even signal point are input. to the digital filter when recognizing the notification signal of the ramp period, an output or result of the switching means and the time information as an address. In comparison with a case where filter means of the conventional displacement QPSK modulation apparatus p / 4 are obtained by a storage unit that stores filter response waveforms for I-coordinate inputs, each storage unit of the present apparatus it requires a higher storage capacity than conventional filter media, since each storage unit stores the data of the ramp waveform. However, the present apparatus performs burst or uninterrupted flow transmissions, accurate by having an embedded circuit for ramp processing, while the QPSK modulation apparatus of conventional displacement has this circuit externally.

BRIEF DESCRIPTION OF THE DRAWINGS In the drawings: Figure 1 shows symbols (Xk, Y) represented in two-dimensional I-Q coordinates; Figure 2 is a block diagram showing the construction of conventional QPSK modulation apparatus p / 4; Figure 3 is a block diagram showing a partial construction of the QPSK modulation apparatus p / 4 displacement of the present state; Figure 4 shows the ramp period in a segment of a Time Division / Duplex Time Division multiple access (TDMA / TDD) and shows a generated ramp waveform; Figure 5 is a time diagram showing the timing signals generated by a circuit that generates timing; Figure 6 is a time diagram showing the timing of the operation of a switching circuit and a separation circuit; Figures 7A and 7B show the relationship between the data stored in the storage units and the waveform data, which are read from the storage units according to the two MSB addresses given as the address signal Te; Figure 8 shows a separation circuit; and Figure 9 shows observation configurations representing the waveforms emitted during two symbol periods (in which even and odd numbers are included) in a general transmission.

DESCRIPTION OF THE PREFERRED MODALITY Figure 3 is a block diagram showing the construction of the displacement QPSK p / 4 modulation apparatus 100 of the present embodiment. The QPSK modulation apparatus p / 4 of displacement which is obtained on an LIS chip, includes the ramp period detection circuit 101, the timing generation circuit 102, the input terminal 103, the symbol generating circuit 104, the transformation circuit 105, the coordinate accumulators 106, 107, 108 and 109 , the switching circuits 110 and 111, the storage units 112 and 113, the separation circuits 114 and 115, the subtractor 116, the add-ons 117, 118 and 119 and the D / A converters 120 and 121. The transformation circuit or representation 105 includes a differential coding circuit 105a. The mixers 122 and 123, the phase shifter 124 and the addiver 125 are external circuits connected to the displacement QPSK modulation apparatus p / 4. Figure 4 shows the ramp period in a segment of a multiple access time division / time division duplex (TDMA / TDD) frame and shows a generated ramp waveform. As described above, in the uninterrupted transmission of a modulated signal, the frequency band of the transmission signal expands due to an enormous parasitic emission generated by a pronounced elevation of the transmission signal. Accordingly, for a communication system that performs uninterrupted transmissions with a digital modulation method, such as QPSK p / 4 displacement, in general, a certain ramp period is set for each of the sudden increase elevation and the drop of the sudden increase, in such a way that the ramp processing on the transmission signal is carried out in the ramp periods. For example, as shown in segment (a) of Figure 4, each segment of TDMA / TDD frames for the PHS (Personal Portable Phone System) are allocated 625μsec in which 240 bits of data can be transmitted with 384KB / sec of physical transmission speed. The first 4 bits of each segment are used as ramp bits for the sudden increase or burst rise and the last 16 bits as protection or safety bits. The protection or security bits form a non-transmission section that is set to prevent transmission data from being affected by stray emissions or noise by other electric waves. It is determined that the receiver should not consider ramp bits and protection bits as substantial data. Also, the first four bits of the protection or safety bits are used as ramp bits for the drop of uninterrupted flow or sudden increase. The baseband signal is not input to the last 12 bits of the protection bits. Accordingly, at the end of the ramp-bit processing of the ramp bits for the drop of the sudden increase or uninterrupted flow, the modulation apparatus of QPSK p / 4 shift finishes the modulation process. The four bits in each of the sudden increase and fall rise are input through the input terminal 103 as a baseband signal representing non-operational data. The ramp waveform as shown in (c) MODULATION SIGNAL of Figure 4 is emitted based on the baseband signal. The ramp waveform rises and falls according to a uniform envelope. This ramp waveform is obtained by multiplying a delayed or unblocking signal as shown in (b) DELAYED SIGNAL of Figure 4 by a combined modulated signal according to the baseband signal. The baseband signal having substantial data is input during the 220-bit section (hereinafter referred to as "general transmission" interspersed by the ramp bits.) Circuit 101 detecting the ramp period receives the clock CK which is the same clock signal as that provided by the timing generation circuit 102 and receives the TXTRG transmission trigger signal, which indicates the beginning of the transmission of the modulated signal of an external element such as a TDMA circuit. The circuit 101 which detects the ramp period initiates the counting of the clock CK when the trigger signal of the TXTRG transmission is active. This allows a baseband signal representing substantial data to be input via the input terminal 103 to the displacement QPSK modulation apparatus p / 4 which allows the apparatus 100 to begin processing. The circuit 101 detecting the ramp period recognizes the start of the lift ramp processing when the count value of the clock CK becomes equal to the delay of the modulation processing of an input., that is, the response delay of the digital filter for an input, after the TXTRG transmission trigger signal is activated. The circuit 101 that detects the ramp period emits "01" as a direction signal Te to the storage units 112 and 113 while continuing with the count of the clock CK. The address signal Te being composed of two bits, is used as 2 MSB (Most Significant Bist) in the addresses of the storage units 112 and 113. The storage areas in the storage units 112 and 113 indicated by the two directions MSB "01" store the data in the form of a ramp wave for the elevation ramp processing corresponding to the two-dimensional coordinate data used in the elevation ramp processing. The circuit 101 that detects the ramp period recognizes the end of the lift ramp processing when the count value of the CK clock becomes equal to the time period between the time when the trigger signal of the TXTRG transmission becomes active and the time when the lift ramp processing ends. At the same time a baseband signal consisting of substantial data is input via the input terminal 103 to the apparatus 100 modulation of QPSK p / 4 displacement. The circuit 101, which detects the ramp period, outputs "00" as a direction signal Te to the storage units 112 and 113 while continuing to count the CK clock. The storage areas in the storage units 112 and 113 indicated by two MSB addresses "00" store the data in the form of a response wave of a low pass filter such as a Nyquist filter for processing to a data entry of coordinates of two dimensions which are obtained from a baseband signal of general transmission. Also, the circuit 101 that detects the ramp period recognizes the start of the fall ramp processing when the count value of the clock CK becomes equal to the time period between the time when the trigger signal of the TXTRG transmission becomes active. and the time when the fall ramp processing begins. A baseband signal consisting of certain non-operational data is input via terminal 103 to a QPSK modulation apparatus p / 4 of displacement. The circuit 101 which detects the ramp period, outputs "10" as a direction Te to the storage units 112 and 113 while continuing to count the clock CK. The storage areas in the storage units 112 and 113 indicated by two MSB addresses "10" store the data in the form of a ramp drop wave corresponding to the two-dimensional coordinate data for the fall ramp processing. The circuit 101 which detects the ramp period recognizes the end of the fall ramp processing when the count value of the clock CK becomes equal to the time period between the time when the trigger signal of the TXTRG transmission becomes active and the time when the fall ramp processing ends. This allows the displacement QPSK modulation apparatus p / 4 to complete the modulation process. The circuit 102 generating the timing generates the clocks T1-T6 as shown in Figure 5 based on the clock CK which is provided from an external element and is a clock or synchronization signal having a higher frequency than the clock. speed or bit rate of the baseband input signal. The TI clock (four bits in Figure 5) represents a count value of the CK clock signal between an odd symbol timing opportunity and immediately before the next odd symbol timing opportunity and is provided for the storage units 112 and 113. That is, the TI clock is information passed in time that indicates a time elapsed during two odd / even symbol periods. The clock T2 is a clock or synchronization signal having the same frequency as that of the input baseband signal. The clock T3 is a clock signal that has the same frequency as that of a symbol. The clock T4 is a clock signal having the same frequency as that of the two symbols. The clock T5 is a clock signal having a reverse phase of the clock T4. The clock T6 is a switching signal that ti-r-ne a switching speed twice the count of the clock TI which is elapsed time information. The input terminal 103 is used to input a baseband signal, i.e. serial data as a signal to be modulated, to the QPSK modulation apparatus p / 4 of displacement. The symbol generation circuit 104 is obtained by means of a shift register. The symbol generation circuit 104 receives a baseband signal with the timing < ! "TI clock provided by means of the circuit 102 that generates time delay and converts the baseband signal received in series and parallel to generate the symbol- (X, Y), which is composed of two successive bits in the signal of base band The transformation circuit 105 receives the symbol data generated by the symbol generation circuit 104 with the clock timing T3 having the same frequency as that of the symbol data, the clock T3 is provided by the timing generator circuit 102. The transformation circuit 105 performs a certain training based on the received symbol data or a coding result of the ifferential coding circuit 105a to generate a piece of coordinate data and or two-bit dimensions. that represent an address. Now, an example of two-dimensional coordinate data emitted from the transformation circuit 105 is described with reference to Figure 1. As mentioned above, a signal point represented by a quadrature signal (l and, Q1;) becomes any of the A-D signal points and any of the E-H signal points alternately. Also, the coordinates of the points AD are represented respectively "~ omc A (l, l), B (-l, l), C (-l, -l), and D (l, -1) in a coordinate of two dimensions represented by vector la and vector Qa ".mo axes. Also, the coordinates of the EH points are represented respectively as E (l, i), F (-1,1), G (-l, -l), and H (l, -1) in a two-dimensional coordinate represented by the vector Iß and the vector Qβ as the axes, Here, suppose that a baseband signal "1, 0, 1, 1, 0, 0, 0, 1, ..." is introduced to the terminal 103 of entry. Then, a symbol generator circuit 104 generates a sequence of two-bit symbols (XI, Yl) = (1, 0), (X2, Y2) = (1, i), (X3, Y3) = (0.0 ), (X4, Y4) = (0, 1) ... in sequence. The transformation circuit 105 obtains the coordinates of the signal points indicated by the symbols when using the signal point H shown in Figure 1 as a standard point. For example, it is found from Table 1 that the odd symbol (XI, Yl) indicates the signal point D which has a phase difference -p / 4 between itself and the point H. The signal point D is represented as D (l, -1) in a two-dimensional coordinate represented by the vector Ia and the vector Qa as the axes. Note that "-1" is represented as "0" since "-1" can not be represented by a bit. The transformation circuit 105 outputs two-dimensional coordinates D (1,0) as the transformation result for the symbol ÍX1, Y1). The first bit "1" of the two-dimensional coordinates D (1,!, Is output to the coordinate accumulator 106 and the second bit "0" to the coordinate accumulator 107.

If true, the next even symbol (X2, Y2) indicates the point F of sin .. i that has the phase difference -3p / 4 between itself and the point D. The coordinate values of the signal point F are represented as F (-1, J) in a two-dimensional coordinate represented by the vectors Iß and Qß as the axes. The transformation circuit 105 outputs the coordinates of two dimensions F (0,1) as the transformation result for the symbol (X 2, Y 2). The first bit "0" of the coordinates of two dimensions F (0,1) is output to the accumulator 108 of coordinates and the second bit "1" to the accumulator 109 of coordinates. Similarly, the next odd symbol (X3, Y3) indicates the point ': of signal having the phase difference p / 4 between itself and the point F. The transformation circuit 105 emits coordinate? two-dimensional C (0,0). The first bit v, 0"is output to the coordinate accumulator 106 and the second bit" 0"to the coordinate accumulator 107. The next even symbol (X4, Y4) indicates the signal point H which has the phase difference 3p / 4 between itself and the point C. The transformation circuit 105 outputs two-dimensional coordinates H (1.0) The first bit "i" is output to the coordinate accumulator 108 and the second bit "0" to the accumulator 109 of The differential coding circuit 105a, if necessary, performs differential coding on the symbol data received by the transformation circuit 105. More specifically, the differential coding circuit 105a obtains the symbol signal point (Xk). , Y? :) by storing in advance a conversion table corresponding to Table 1 and storing at least one signal point indicated by the preceding symbol (Xk-i, Y. :-?) • The coordinate accumulator 106, obtained by a registered r of shifts, accumulates Ia coordinates of one bit by one bit for each odd symbol timing opportunity and outputs a certain number of accumulated bits, for example, five bits of coordinates Ia as five higher bits that follow the two MSBs in the storage unit 112 to the switching circuit 110. According to these five higher bits, the data of the response waveform of the filter (or ramp waveform) corresponding to the coordinates Ia introduced with the timing of the odd symbol are read from the storage unit 112. The coordinate accumulator 107, obtained by a shift register, accumulates Qa coordinates of one bit per one bit for each odd-numbered timing opportunity and outputs a certain number of accumulated bits, for example, five coordinate bits Qa as the five higher bits following the two MSBs in the storage unit 112 to the switching circuit 110. According to these five higher bits, the data of the response waveform of the filter (or ramp waveform) corresponding to the coordinates Qa introduced with the timing of the odd symbol, are read from the storage unit 112. The coordinate accumulator 108, obtained by means of a displacement recorder, accumulates Iß coordinates of one bit per one bit for each timing opportunity of the odd symbol and outputs a certain number of accumulated bits, for example, five bits for Iß coordinates such as five higher bits following the two MSBs in the storage unit 113 to the switching circuit 111. According to these five higher bits, the data of the waveform (or ramp waveform) of the filter response 1 / β corresponding to the Iß coordinates inputted with the timing of the odd symbol, are read from the unit 113 storage. The coordinate accumulator 109, obtained by means of a shift recorder, accumulates Qβ coordinates of one bit by one bit for odd symbol timing opportunity and outputs a certain number of accumulated bits, for example, five bits of Qß coordinates as five bits more highs following the two MSBs in the storage unit 113 to the switching circuit 111. According to these five higher bits, the data of the waveform (or ramp waveform) of the filter response i / ß corresponding to the Qβ coordinates introduced with the timing of the odd symbol are read from the unit of storage 113.

The switching circuit 110 is obtained by a selector and the like. The switching circuit 110 outputs addresses entered from the co-ordinate accumulators 106 and 107 alternately to the storage unit 112, with the clock timing T6 before a current piece of elapsed time information is switched with the clock timing. YOU. Figure 6 shows the output or output of the switching circuit 110 and the clock T6 at the output. The switching circuit III is obtained as the switching circuit 110, by means of a selector and the like. Switching circuit 111 issues entered addresses from co-ordinate accumulators 108 and 109 alternately to storage unit 113 with clock timing T6 before a current piece of elapsed time information is switched with each other with clock timing TI . The storage unit 112 stores the address signal Te sent from the ramp-period detector circuit 101 as an address of two MSBs, stores the outputs or results of the coil accumulators 106 and 107 as bit addresses following the two MSB and stores the TI clock, that is, the elapsed time information sent from the timing generator circuit 102 as the following bits to all these bits.

Figures 7A and 7B show the relationship between the data stored in the storage units 112 and 113 and the waveform data which are read from the storage units 112 and 113 according to the addresses of two MSBs provided as the direction signal. In a storage aerea indicated by addresses of two MSB "00" in the storage unit 112, the waveform data of the general transmission corresponding to the coordinates Ia and Qa are stored. The waveform data of the general transmission is the data that shows the level (instantaneous value) of the response waveform of the low pass filter such as a Nyquist filter of course which is given by a coordinate Ia / Qa introduced. The storage unit 112 stores the data in wave form corresponding to the timing of the odd symbol, that is, the data in the form of a response wave, a filter to enter ± 1, which are the coordinates Ia and Qa of timing of odd symbol. Also, the storage unit 112 stores the waveform data corresponding to the timing of the even symbol, that is, the response waveform data from the low pass filter to the 0 input which are the coordinates Ia and Qa of timing of the pair symbol. In a storage area indicated by the address of two MBS "01" in the storage unit 112, the data of the waveform is stored in uninterrupted flow elevation. Note that each piece of data in ramp wave form stored in storage units 112 and 113 is gained by multiplying a window function representing (b) DELAY SIGNAL shown in Figure 4 by a filter response waveform corresponding to each of the coordinates Ia, Qa, Iß and Qß. That is, if it is assumed that g (t) represents the window function and I (t) g (t) and Q (t) g (t) respectively the instantaneous values of phase I and phase Q of the waveform of ramp, then the following formulas are given. Formula 10 oo I (t) g (t) = S Ia2K.-h. { t- (2N + l) T} g. { t- (2N + l) T} 1 oo + - SI?, "H (t-2NT) g (t-2NT) V2" - 1 oo S Qá2Nh (t-2NT) g (t-2NT) V2 N ~~ Formula 11 oo Q (t) g (t) = SQ 2N + 1h { t- (2N + l) T.} g { t- (2N + l) T.}. 1 oo + - - SI? 2N (t-2NT) g (t-2NT) "2 N" ~ 1 oo + - S Qfl2Nh (t-2NT) g (t-2NT) 2"~" The waveform of ramp in MODULATED SIGN (c) of the Figure 4 is obtained by combining (adding) the component in phase on the modulated carrier wave when amplifying I (t) g (t) of Formula 10 and the phase quadrature component in the modulated carrier wave when amplifying Q (t) g (t) of Formula 11., the storage area in the storage unit 112 indicated by the address of two MSB "01" stores the data in the form of a ramp wave for the elevation ramp processing corresponding to coordinates of two dimensions (Ia, Qa), this is, the data in ramp wave form for the elevation ramp processing corresponding to the first term of the formulas (10) and (11). For the uninterrupted flow elevation, the coordinates Ia and Qa can be only "+1" or "-1" with the timing of the odd symbol and "0" with the timing of the even symbol. This is the same as for the general transmission. Also, the storage area in the storage unit 112 indicated by the address of two MSB "10" stores the data in the form of a ramp wave for all the fall ramp processing corresponding to the coordinates of two dimensions (Ia, Qa ), that is, the data in the form of a ramp wave for the fall ramp processing corresponding to the first term of the formulas (10) and (11). For the fall ramp processing, the Iß and Qß coordinates can only be "0" with the odd symbol timing and "+1" or "-1" with the torque symbol timing. This is the same as for the general transmission. In a general transmission, the address "00" of two MSBs given as address signal Te and the next higher bits of the coordinate accumulators 106 and 107 divided in time division with the clock timing T6 are input to the unit 112 of storage. The highest bits of the coordinate accumulators 106 and 107 are updated with each timing opportunity of the odd symbol. In parallel with these pieces of data, a lower address such as the elapsed time information clock TI is input to the storage unit 112. The clock TI represents a counting value of the clock signal CK between a timing opportunity of the symbol odd and immediately before the next timing opportunity of the imp r symbol. The coordinate accumulator 106 outputs the accumulated coordinates Ia with each timing of the odd symbol to the storage unit 112 as, for example, five upper bits following the two MSBs. The LSB of the five highest bits is the coordinate of the current odd symbol timing opportunity and the other four bits are Ia coordinates of the previous odd timing opportunities, "-1" represented by "0". According to these five higher bits, the filter response waveform data corresponding to the current elapsed time information for the co-ordinate Ia of the timing opportunity of the current odd symbol are read from the storage unit 112, for example , with the odd timing of the T6 clock. The A '-The coordinate simulator 107 outputs the accumulated Qa coordinates with the timing of the odd symbol to the storage unit 112 such as, for example, five more bits after the two MSBs. Of the five upper bits, the LSB is the coordinate Qa of the opportunity of tP- porization the current odd symbol and the other four bits are coordinates Qa of the previous odd timing opportunities, "-1" is represented by "0" . According to the above five bits, the data in the form of the response wave of filter coresponding to the elapsed time information for the coordinate Qa of the timing opportunity of the current odd symbol, are read from the unit of the vessel. 112, for example, with the even timing of the T6 clock. No address is input to the storage unit 112 of the coordinate accumulators 106 and 107 with the tf-'it.porizaciór. a couple symbol. However, the time interval for the elapsed information indicates the even symbol timing. 'xc has been described -u. present, both -'cor.ier.adas Z u \ X¡. They are "C" with ia '••? iparize rum pair symbol. Accordingly, two cycles of the response waveform of the filter in each elapsed time with the "0" input are read alternately in time division of the storage unit 112 each time the lower address exceeds a certain value. The only difference between the lifting ramp processing and the general transmission is that the direction of two MSB mixes "01" given by the direction signal Te is input to the storage unit 112, the lifting ramp process is it performs in the same manner as the general transmission in terms of the rest of the processing, that is, higher bit addresses following the two MSBs are input from the coin accumulators 106 and 107 to the storage unit 112 and in parallel to the TI clock as a lower address. The coordinate accumulator 106 outputs Ia coordinates accumulated with the timing of the odd symbol to the storage unit 112 as, for example, five higher bits q? E follow the two MSBs. According to these five higher bits, the data in the form of a ramp wave in the uninterrupted flow elevation corresponding to the current elapsed time information for the co-ordinate Ia of the timing opportunity of the current odd symbol are read from the unit 112 of storage, for example, with the odd timing of the T6 clock.

The coordinate accumulator 107 outputs Qa coordinates accumulated with the odd symbol temptation to the storage unit 112 as, for example, five higher bits that follow the two MSBs. According to these five upper bits, the data in the form of a ramp wave in "the uninterrupted flow rise corresponding to the current elapsed time information for the coordinate Qa of the opportunity to set the current odd symbol are read from the uruu -l 112 to store me, for example, with the even tempopzation of the clock T6, both coordinates Ia and Qs are "0" with the torque symbolization, therefore, two classes of the data in wave form Ramp in the uninterrupted flow rise in each elapsed time with entry "0" are alternately read in time division of storage unit 1--2 each time the lower address exceeds a value or value. The difference between the ramp processing and the general transmission is that the address "10" of two MSBs given by the address signal Te is input to the storage unit 112. With the timing of the odd symbol, as the Higher directions, which are inputted from the accumulators 106 and 107 of coordinates alternately in ivinen of time, with the timing "in of the relay T6 and a given lower address as the TI of elapsed time information, are input to the storage unit 112, two pieces of the data in the form of a ramp wave in the fall of the uninterrupted flow respectively, corre sponding to the information of the actual elapsed time for the co-ordinate Ia of the timing opportunity of the current odd symbol and The current elapsed time information for the coordinate Qa are read alternately in time division of the unit 112 of storage with the timing of the clock T6. Both coordinates Ia and Qa are "0" with the timing of the even symbol. Therefore, in the same way as the general transmission and the uninterrupted flow elevation, two classes of data in the form of a ramp wave in the uninterrupted flow drop in each time elapsed with the input "0" are alternately read in time division of the storage unit 112 each time the lower address exceeds a certain value. The storage unit 113 receives the address signal Te, which is input to the storage units 112 and 113 simultaneously, as an address of the MSB. The storage unit 113 pre-stores the results or outputs of the coil accumulators 108 and 109, which are divided into time division with the clock timing T6, as bit addresses following the two MSBs and receives the clock. TI, that is, the information of the elapsed time sent from the timing generation circuit 102 as lower addresses. As shown in Figure 7A, the storage unit 113 has the same area assignment with addresses as the storage unit 112. That is, in a storage area indicated by two "00" addresses of two MSBs in the storage unit 112, the data is stored in a ci-? general transmission wave; in a storage area indicated by "01" addresses of two MSBs, the data in the form of a ramp wave in uninterrupted flow elevation; and in a storage area indicated by addresses "10" of des MSB, the data in the form of a ramp wave in the fall of the uninterrupted flow. The bits of each of the above waveform data correspond respectively Ii Iß and Qß coordinates which are introduced to the low pass filter. The storage unit 113 stores the following data classes in wave form for general transmission: data in response waveform l /? '2 of the low pass filter, such as a Nyquist root crate, at time when +1 , which are the values of the Iß and Qβ coordinates given with the even symbol timing, is introduced to the low pass filter; and data in the form of response wave 1 / ^ / 2 of the low pass filter at time when;, (= 1 which is the value of the coordinates T, and Q, given with the timing of the odd symbol, will be introduced Also, the idling unit 113 stores the following data on the ramp wave envelope for the uninterrupted flow: the ramp-wave data l / \ '2 for the first ramp-up process at time when either of ± 1, which are the coordinate values I (.and ,,) \) given with the timing of the even symbol, is entered at the low-pass angle.; and data in ramp wave form 1 / V2 for the processing <lifting ramp to time when 0, which is the value of the Iß and Qß coordinates given with the odd symbol timing, is input to the pass filter This means that the storage unit 113 stores the data in the form of a ramp wave that is equal to rs seconds and third terms in the formulas 10 and 11. In addition, the storage unit 113 stores the following data classes er -.orma -t = ramp wave for the fall of the interrupted flu: data ^ n form o wave ramp l / v2 for the pt "'ramp stop or drop to time when either of ± 1, which are the values of the co-wends Iß and," > ß given with the order of the even symbol, «and enter a pass filter ba o; and data in the form of ramp wave 1 / "V2 for the ramp processing of elevation to time when 0, < =.! what is the value of the coordinates Iß and Qß given with the - - r i odd symbol is introduced to the pass filter ba o In ura general transmission, the address signal Te is entered as the address "00" of two MSB to the storage unit 113, and the next higher bits divided into time division with the clock timing T6 are alternately inputted from the coordinate accumulators 108 and 109. The upper Dits of the coil accumulators 108 and 109 are updated with each timing opportunity of the even symbol. The lower ion as the TI information clock is transferred to the storage unit 113. Coordinate EJ-r-rir.10 emits accumulated I s coordinates ci, timing of the pair symbol a the unit 113 c e store, such as, for example, five higher bits following the two MSBs. The LSB of the five upper bits in the id-coordinate. Iß of the timing opportunity of the current pair symbol and the other four bits are the Iß coordinates of the previous pair timing opportunities, "-] _" represented by "0". According to these five higher bits, the data in the form of filter response wave 1 / "V2 corresponding to the information of the current elapsed time for the Iß co-ordinate of the timing opportunity of the current nt symbol is read as a unit 113 for storage, for example, with the odd feedback of the clock T6.The coordinate accumulator 109 outputs accumulated Q.sub.s with the timing of the even symbol to the storage unit 113, for example, 5 upper bits following the two MSBs. Of the five upper bits, the LSB is the coordinate Qß of the timing opportunity of the current pair symbol and the other four bits are Qβ coordinates of the timing opportunities previous pairs, - \ "is represented by" 0". According to these five higher bits, the data in response waveform cié filter 1 2 corresponding to the time information t ranscurr -.do current for the > The Q.sub.sign of the timing opportunity of the current pair symbol is read ie the storage unit 113, for example, with the clock setting of the T6 clock. With the odd-numbered timing, the address in the storage unit 113 is not updated since no address. the accumulators 108 and 109 of coordinates are introduced. Srr ^ bargo, the elapsed time information TI clock r. ce the ternponzation of the odd symbol. As described above, Iβ and Qβ coordinates are 0"with the time of the odd symbol.Therefore, two classes of the ia ** in the form of filter response wave 1 / V2 in each time elapsed with the input "0" are alternately read in time division of the storage unit 113 each time the lower address exceeds a certain value.The only difference between the lifting ramp processing and the general transmission is that the address " 01"of two MSBs given by the address signal Te is input to the storage unit 113. The lifting ramp processing is carried out in the same manner as the general transmission in terms of the rest of the processing, ie the addresses of the upper bits following the two MSBs are alternately entered from the storage accumulators 108 and 109 to the storage unit 113 and in parallel, the TI clock as lower addresses. consequently, two classes of the ramp waveform data 1 / ^ 2 of the current elapsed time information with input "0" corresponding to the Iß and Qβ coordinates are read alternately in time division with the clock timing T6 when the lower direction given by the TI clock is less than a certain value. Also, the data in ramp-up l / v2 of the information of the current elapsed time with the Iß co-ordinate input with the timing of the current even symbol is read, for example, with the odd timing of the clock T6. The data in ramp-wave form I / ?. 2 of the information of the current elapsed time with the coordinate Q.sub.β entered with the timing of the current pair symbol is read, for example, with the clockwise timing of the clock T6. The only difference between the drop ramp processing and the general transmission is that the "10" address of two MSBs given by the address signal Te is input to the storage unit 113. The drop ramp processing is carried out in the same manner as the general transmission and the lifting ramp processing for the remainder, that is, the addresses of the upper bits following the two MSBs are input from the accumulators 108. and 109 of coordinates to the storage unit 113 and in parallel, the TI clock as a lower address. Accordingly, the data in ramp wave form 1 / V2 in the uninterrupted flow drop of the current elapsed time information with "0" entered with the timing of the current odd symbol are read with the clock timing T6 when the address lower given by the TI clock is less than a certain value. The data in the form of ramp wave 1 / V2 in the drop of the uninterrupted flow of the information of the current elapsed time with the coordinate Iß input with the timing of the current pair symbol is read, for example, with the odd timing of the clock T6. The data in ramp wave form 1 / ^ 2 in the fall of the uninterrupted flow of time information «1 Current elapsed time with the Qβ coordinate entered with the timing of the current torque symbol is read, for example, with the even timing of the T6 clock. The separation circuit 114 separates the result or output of the storage unit 112 to the data in the form of a filter response wave (or ramp waveform) corresponding to the Ia coordinate and the data in the form of a response wave of filter (or ramp waveform) corresponding to the coordinate Qa with the timing of the clock T6 and output the two class i data simultaneously, for example with the clock cycle TI. More specifically, the separation circuit 114 receives the data in the form of a filter response wave corresponding to the coordinate Ia, for example with the odd timing of the clock T6 and outputs the data to the adder 118 with the following even timing of the same clock T6 Also, the separation circuit 114 receives and outputs the filter response waveform data corresponding to the coordinate Qa to the adder 119, for example, with the even timing of the clock T6. Figure 8 shows the separation circuit 114 in detail. The drawing includes the registers 114a-114c and the inverter 114d. Note that a clock having a synchronization cycle shorter than clock T6 can be used for registers 114a-114c to shorten the delay.

The separation circuit 115 separates the output of the storage unit 112 into the data in the form of a filter response wave 1 / V2 (or ramp waveforms) corresponding to the Iß coordinate and the data in the form of a response wave filter (or ramp waveform) l / \ 2 corresponding to the coordinate Qβ with clock timing T6 and output the two data classes simultaneously, for example, with the clock cycle TI. More specifically, the separation circuit 115 receives the filter response waveform l / 2 corresponding to the Iß coordinate, for example, with the odd timing of the clock T6 and outputs the data to the subtracter 116 and the addiver 117. with the next even timing of the same clock T6. Also, the separation circuit 115 receives and outputs the data in the form of the filter response wave I / V2 corresponding to the coordinate Qβ to the subtracter 116 and to the adder 117, for example with the even timing of the clock T6. The separation circuit 115 has the same construction as that shown in Figure 8. The subtractor 116 subtracts the data in the form of the filter response wave 1 / V2 corresponding to the Qβ coordinate of the data in the form of the response wave of the filter 1 /? 2 corresponding to the Iß coordinate, both kinds of data are emitted from the separation unit 115. That is, the subtractor 116 executes the subtraction of the third term of the second term in Formula 8.

The adder 117 adds two data classes that are emitted from the separation unit 115, that is, two data classes in the form of the filter response wave l / v2 corresponding to the coordinate iß and the coordinate Qß. That is, the add-on 117 executes the addition of the second and third terms in the formula 9. The add-on 118 adds the result or output of the subtractor 116 to the data in the form of a filter response wave (or ramp waveform) corresponding to the coordinate Ia, that is, one of the results or output of the separation unit 114 to emit the instantaneous value I (t) of the phase I signal given by Formula 8. The addor 119 adds the result or the output of the adder ll "7 to the data in the form of filter response wave (or ramp waveform) corresponding to the coordinate Qa, ie, the other of the outputs or results of the separation unit 114 to emit the instantaneous Q (t) value of phase signal Q given by Formula 9. Converting unit D / A converts digital data I (t) into an analogous signal, I (t) is the result or output of the additive 118 and represents the instantaneous value of phase I signal. conversion unit 121 converts the digital data Q (t) into an analogous signal, Q (t) is the result or output of the adder 119 and represents the instantaneous value of the phase signal Q. The above operations carried out by the subtracter 116 and the adders 117-119 generate the instantaneous value I (t) of phase I signal and the instantaneous value Q (t) of the phase Q signal which are used to generate the corresponding ramp waveforms in the rise and fall of the uninterrupted flow. Also, the above operations generate the instantaneous value I (t) of the phase I signal and the instantaneous value Q (t) of the phase signal Q which correspond to the response waveforms of the low pass filter in the general transmissions. Figure 9 shows observation configurations representing the output of waveforms of the D / A converters 120 and 121 during periods of two symbols (including even and odd) in a general transmission. In the drawings, the horizontal axis shows the elapsed time, the vertical axis, the output level of the filter response waveform h (t) of Phases I and Q. It is assumed that when the filter input is 1 and the interference between the codes is 0, the instantaneous value of the base point is 1. With the symbol timing even, the levels of the instantaneous values I (t) and Q (t) of the standard point are either +? 2 , - 2 and 0, since the first terms in formulas 8 and 9 can be "0" and at the same time the second and third terms can cancel each other out. When the second and third terms cancel each other, either either I (t) and Q (t), that is, the respective instantaneous values of the phases of I and Q, is level 0. For example, the instantaneous value I (t) of phase I is level 0 for signal point E or G in Figure 1. At the same time, the instantaneous value Q (t) of phase Q is level + v2 for signal point E , of level -v2 for the signal point G. With the odd symbol timing, each level of instantaneous values I (t) and Q (t) of the standard point is either +1 and -1 since the seconds and third terms are of level 0 and each of Ia and Qa of the first term is either +1 and -1. For example, the instantaneous values I (t) and Q (t) of the standard point are level 1 for the signal point A. The mixer 122 mixes the result or output of the D / A converter 120 and a carrier wave. The result or output of the mixer 122 is represented by I (t) cos2pfCt which is the result of multiplying I (t), the result or output of the D / A converter 120 by the carrier wave cos2pfCt. Mixer 123 mixes the result of the converter D / A 121 and a carrier wave introduced by means of the phase shifter p / 2 124. The output or result of the mixer 123 is represented by Q (t) sin2pfCt which is the result of multiplying Q (t), the output of the converter D / A 121, by the carrier wave sen2pfct that has the phase difference p / 2. The phase shifter p / 2 124 delays the phase of the carrier waves introduced by p / 2. Adder 125 multiplexes the results or outputs of mixers 122 and 123 and outputs the multiplexed value. The adder 125 emits the modulated signal against the I (t) cos2pfCt + Q (t) sin2pfCt which correspond to a response waveform of the low pass filter. The adder 125 emits a certain ramp waveform as shown in Figure 4 (c) MODULATED SIGNAL during the ramp period. As is clear from the foregoing description, this embodiment of the present invention has succeeded in reducing the number of storage units of four, such as storage units 610-613 in the conventional displacement modulation apparatus QPSK p / 4 to two when reading the waveform data stored in the storage units 112 and 113 with time division with the clock T6 corresponding to the I and Q coordinates. This reduces the number of circuits as a whole and makes it easier to obtain the apparatus 100 modulation of QPSK p / 4 displacement on an LSI chip. Also the reduction in the number of circuits makes it possible for the storage units 112 and 113 to store data in the form of a ramp wave in the elevation of the uninterrupted flow and the uninterrupted flow drop which allows the ramp processing in the elevation of the flow uninterrupted and the fall of the uninterrupted flow. In addition, it is possible to generate the ramp waveform more exactly with the same procedure as that used in the general transmissions by using the ramp wave data stored in the storage units 112 and 113. In this embodiment, the ramp-wave data are generated for each of the uninterrupted flow elevation and the uninterrupted flow drop and are stored in the storage units 112 and 113. For the uninterrupted flow elevation, a data configuration in the form Ramp wave generated based on a certain piece of inoperational data can be stored in each of the storage units 112 and 113, since the substantial data has not yet been entered and the data is not demodulated from the waveform of ramp. Also, for the uninterrupted flow drop, a configuration of the ramp wave data generated in advance can be stored in each of the storage units 112 and 113, such that the ramp wave falls uniformly in of wave response of filter in general transmission in waveform. This is because there is no need to consider interference response components which are generated by the previous inputs in the general transmission. Even for the uninterrupted flow drop, interference by the response components for the inputs in the overall transmission would be ignored if the ramp waveform were to be generated according to the response filter shape of the actual filter. However, in reality, the storage units 112 and 113 do not store such interference, but rather store the genuine waveform data which are read as response waveforms. Thus, the storage space not so much as that for storing the data in the form of a filter response wave in a general transmission is required even if the data in the form of a ramp wave for the rise and fall of the uninterrupted flow is stored. In this embodiment of the present invention, the data in the ramp wave form is stored for the uninterrupted flow rise and the uninterrupted flow drop. Nevertheless, the ramp waveform ciatos may not necessarily be stored for the uninterrupted flow and the uninterrupted flow. For example, storage units 112 and 113 can only store data in the form of a ramp wave at the uninterrupted flow elevation. Alternatively, a counter for counting the elapsed time, that is, with an inverted TI clock direction, can be adjusted in such a way that in the uninterrupted flow drop, the result of this counter is used as lower bits instead of the IT clock to read the ramp waveform of the uninterrupted flow elevation. Also, the ramp waveform of the modulated signal may be generated from the waveform data for the general transmissions with non-operational data input instead of being generated from the data in the form of a ramp wave. For example, the amplitude adjustment circuits, which consist of the shift registers can be adjusted or set at the output of the add-ons 118 and 119 or at the output of the storage units 112 and 113, so that in the uninterrupted flow elevations, the lower bits of an entered value are emitted at the beginning when the number of output bits increases as time elapses to generate the ramp waveform at the uninterrupted flow elevation. Simi- larly, for the uninterrupted flow drops, the number of output bits can be decreased as time elapses to generate the ramp waveform in the uninterrupted flow drop. In this embodiment of the present invention, the address signal Te is used as 2 MSB in the directions of the storage units 112 and 113. However, the direction signal Te may not necessarily be used as an address of two MSBs. The direction signal Te can be used as two bits that follow the two MSBs in the directions, the two s are the outputs of the switching circuits 110 and 111 since the data in the ramp wave form does not require as much data such as waveform data in general transmissions. In this embodiment of the present invention, each of the coordinate accumulators 106, 107, 108 and 109 accumulate, for example, 5 coordinate bits. However, they can accumulate seven, ten or another number of bits instead of five bits. That is, the number of bits accumulated by the accumulators can be determined based on the degree to which the response of the filter to the previous coordinate values affects the response of the filter to the last coordinate values as time elapses. Note that as the number of bits accumulated by the accumulators 106, 107, 108 and 109 increases, the accuracy of the response waveform of the filter is improved but the amount of data stored in the storage units 112 and 113 In this embodiment of the present invention, a case with displacement QPSK p / 4 is described. However, QPSK can be used instead of QPSK p / 4 offset. In that case, either of the two horizontal data flows shown in Figure 3 can be used to obtain such an operation.

POSSIBILITY OF INDUSTRIAL USE This invention is suitable for phase modulating apparatuses to allow storage units to store the waveform data of I and Q components of the symbol data in advance and generate the symbol waveform according to the data in the form of wave. This invention is also suitable for simplifying the circuits since the transmission amplifier does not need to perform a gain control since the reduction in the capacity of the storage unit allows the storage of the waveform data used in the processing ramp around the transmission of uninterrupted flow in the storage unit with other waveforms.

Claims (6)

1. A phase modulator apparatus, characterized in that it comprises: storage means for storing data in wave form including a waveform used for the elevation ramp processing, a plurality of phase waveforms used for component I and the component Q of a plurality of transmission symbols and a waveform used for the fall ramp processing; symbol generating means for generating in time series a non-operational symbol for lifting ramp processing, the plurality of transmission symbols and a non-operational symbol for the fall ramp processing; converting means for converting to each of the non-operational symbols for lifting ramp processing, the plurality of transmission symbols and the non-operational symbol for the falling ramp processing in component I and component Q, wherein the non-operational symbol for lifting ramp processing, the plurality of transmission symbols and the non-operational symbol for falling ramp processing are provided in time series; means providing direction to alternately provide, during a symbol period, the component I and the component Q converted by the conversion means as addresses of the storage means; separation means for extracting data from a waveform of the component I and a waveform of the component Q which are read alternately from the storage means and are simultaneously transmitted from the waveform of the component I and the waveform of the component Q; and combining means for combining the waveform of the component I and the waveform of the Q component emitted from the separation means to a symbol waveform, wherein the storage means include: an even storage unit for storing the waveform data corresponding to the even symbols, which alternately receive a component I and a component Q of the means that provide direction as an address in a period of even symbol and alternatively emit a waveform of component I for a symbol pair and a waveform of the Q component for an even symbol; and an odd storage unit for storing the waveform data corresponding to the odd symbols, the waveform data has a level 1 / V2 times that of the waveform data stored in the even storage unit, for receiving alternately a component I and a component Q of the means providing address as an address in an odd symbol period and for alternatively emitting a waveform of component I for an odd symbol and a waveform of component Q for a symbol odd.

2. The phase modulation apparatus according to claim 1, characterized in that the means providing direction comprises: timing means for generating a first timing information which indicates a lifting ramp processing section, a transmission section and a drop ramp processing section and a second timing information which indicates the period of the symbol used in each of the lift ramp processing sections, the transmission section and the fall ramp processing section; selection means to alternately select, during a symbol period, the component I and the component Q converted by means of conversion according to the second timing information; and input means for entering an address to the storage means, wherein the address includes a first partial address, which is the first timing information and a second partial address, which is an output or result of the selection means .

3, The phase modulator apparatus according to claim 2, characterized in that the address providing means further comprise: a shift register I for accumulating the I components of a certain number of symbols converted by the conversion means and issuing the components I in parallel; and a shift register Q for accumulating the Q components of a number of converted symbols by means of the conversion means and outputting the Q components in parallel, wherein the selection means alternately selects an output or shift recorder result I and an output of the displacement recorder Q.

4. The phase modulator apparatus according to claim 1, characterized in that the separation means comprise: first delay means for delaying the output or result of the waveform of the component I of the storage means; and second delay means for delaying the waveform of the Q component emitted from the storage means, such that the second delay means are synchronized with the first delay means at the output.

5. A displacement QPSK modulation apparatus p / 4 to uniquely assign a signal point on a two-dimensional coordinate, which has a perpendicular axis I and Q axis, for each set of two sequential bits in data serially input and generate a modulated signal corresponding to a response waveform which is emitted from a low pass digital filter at a time when an I coordinate and a Q coordinate at the signal point is input, the modulation apparatus QPSK / 4 offset is characterized in that it comprises: means of accumulation of coordinates I to • accumulate the coordinates I and emit the accumulated coordinates I; means of accumulating coordinates Q to accumulate the coordinates Q and emit the accumulated Q coordinates; ramp period notification means for issuing a ramp period notification signal which indicates a period of uninterrupted flow elevation for ramp processing, an uninterrupted flow transmission period during which transmission data representing the modulated signal and a period of uninterrupted flow decay for ramp processing; clock means for outputting the time information and a switching signal, wherein the time information, which has a higher frequency than the input data, indicates a certain elapsed time and the switching signal is faster than the information of time; switching means for alternately selecting an output of the coordinate storage means I and an output of the coordinate storage means Q according to the switching signal and outputting a selected output or result; lift ramp means for alternately emitting an uninterrupted flow ramp waveform for an input of the coordinate filter I and an uninterrupted flow ramp waveform for a Q coordinate filter input according to the ramp period notification signal, an output of the switching means and the time information; filter means for alternatively emitting a filter response waveform for an I / O coordinates coordinate and a filter response waveform for a Q coordinate input according to the ramp period notification signal, a output or result of the switching means and time information; dropping ramp means for alternately emitting a ramp waveform of uninterrupted flow for an input of the coordinate filter I and an uninterrupted ramp waveform for an input of the Q coordinate filter according to the signal of ramp period notification, an output of the switching means and time information; and separating means for separating each result of the lifting ramp means, the filter means and the falling ramp means in two currents, which respectively correspond to the coordinates I and to the coordinates Q.

6. The displacement QPSK modulator apparatus p / 4 according to claim 5, characterized in that the coordinate accumulation means I comprise: odd coordinate accumulation means I for accumulating the I coordinates of the odd signal points in the data serially input and output a sequence of I coordinates that include a certain number of accumulated I coordinates; and means of accumulating coordinates I pairs to accumulate the I coordinates of the even signal points in the serial data entered and emit a sequence of coordinates I that includes a certain number of accumulated I coordinates, where the means of accumulation of coordinates Q comprise: means of accumulation of odd Q coordinates to accumulate the Q coordinates of the odd signal points in the entered serial data and emit a sequence of coordinates Q that includes a certain number of accumulated Q coordinates; and means of accumulation of coordinates Q pairs to accumulate the coordinates Q in the introduced serial data and emit a sequence of coordinates Q that includes a certain number of accumulated Q coordinates, in which the switching means comprise: odd switching to alternately select an output or result of the odd coordinate I accumulation means and an output of the odd Q coordinate accumulation means according to the switching signal and output a selected result or output; and even switching means for alternately selecting a result of the co-accumulation means I pairs and an output of the co-accumulation means Q pairs according to the switching signal and outputting a selected output or result, wherein the means of the lifting ramp, the filter means and the falling ramp means include an 'odd storage unit and an even storage unit', wherein the odd storage unit stores the data in the form of a response wave of a digital filter and also stores the data in the form of ramp wave of uninterrupted flow and data in the form of ramp wave of uninterrupted flow which each correspond to the response waveform data of the digital filter , where the response waveform data of the digital filter correspond to an I coordinate and a Q coordinate which are determined by two bits in the odd input data which are indicated by the addresses, i.e., the ramp period notification signal, an output or result of the switching means and the time information, where the storage unit pair stores the waveform data of a digital filter and also stores the data in the form of an uninterrupted flow elevation ramp wave and the data in the uninterrupted flow falling ramp waveform which each correspond to the data in the form response wave of the digital filter, where the response waveform data of the digital filter correspond to a coordinate I and a coordinate Q which are determined by two bits in the even input data which are indicated by the addresses, i.e., the ramp period notification signal, an output or result of the switching means and the time information.