MXPA97006222A - Device for the switching of packages and channels of modulation triggers by codifica impulses - Google Patents

Abstract

Device for the switching of packets and channels of encoded pulse modulation frames, consisting of a statistical receiver block (11), a statistical transmitter block (12), a frame memory controller (10), a MIC switching matrix (14), an internal resource access controller (26) and a loop controller (13), all of these blocks constituting a switching circuit (2), which in number eight are incorporated in the device together with a microprocessor (1) ), eight frame memories (3), an internal communication bus (9), a statistical bus (7), a circuit switching bus (8), eight input / output drivers and eight bistables (

Description

DEVICE FOR THE SWITCHING OF PACKAGES AND CHANNELS OF MODULATION TRIGGERS FOR CODIFIED IMPULSES D E S C R I P C I O N OBJECT OF THE INVENTION The present specification relates to a patent application of invention relating to a device for the switching of packets and channels of pulse modulation frames encoded in a telephone switching system, whose evident purpose is to be configured as a device that, in addition to performing packet switching allows the retransmission of coded pulse modulation frames (hereinafter MIC), including the switching of MIC frames.

FIELD OF THE INVENTION This invention has its application in the field of telecommunications, and specifically in the field of switching systems for telephone services.

BACKGROUND OF THE INVENTION The different existing equipment on the market dedicated to packet switching and used in various data networks are known.

Also, within the transmission area, equipment for the retransmission of MIC frames is used.

However, on the part of the applicant there is no knowledge of the existence of any equipment that carries out the switching of frame channels.

In view of the future installation of the system (MORE), in order to modernize the analogue centers of the Telephone Network, it has been found necessary to have a device that, apart from carrying out packet switching, allows the retransmission of MIC frames, including the switching of MIC frame channels.

The obvious solution to the current problem in this area, would be to have a device that performs the switching of packets and channels of modulated frames by encoded pulses.

However, until now there is no knowledge of the existence of an invention that is endowed with the characteristics indicated as suitable.

DESCRIPTION OF THE INVENTION The device for the switching of packets and channels of coded pulse modulation frames that the invention proposes, constitutes in itself an obvious novelty within its field of action, since according to the use of the device recommended, it is solved in a satisfactory the problem in question, allowing functionality that is not currently contemplated in the state of the art.

More specifically, the device for switching packets and channels of coded pulse modulation frames object of the invention, is basically constituted by the following elements. Namely: - A microprocessor.

- A series of frame memories.

- An internal communication bus.

- A statistical bus.

- A circuit switching bus.

- A series of switching circuits.

- A series of input / output link drivers.

- A series of flip-flops.

The switching circuits integrated in the device for the switching of packets and channels of encoded pulse modulation frames are connected to each other by means of the statistical bus and the circuit switching bus, each of the communication circuits acceding. to a memory of external frames to it, as well as an input / output driver, working the said switching circuits together and being governed by the microprocessor.

The access of the microprocessor to the internal resources of the switching circuit for its initialization, programming or control is done through the internal communication bus.

The statistical bus is the physical support of packet switching, the related switching circuits being connected to said bus.

The statistical bus supports the transfer of frames from a switching circuit, through a flip-flop, to the driver of a statistical output link.

The circuit switching bus is the physical means by which the switching between the MIC receiver channels and the MIC transmitter channels of the switching circuits integral to the device for packet switching and encoded pulse modulation frame channels is performed.

The circuit-switched bus is configured as a multiplexed bus of data and addresses, and it is accessed by the switching circuits with their input / output lines.

To the driver, one for each switching circuit, the MIC links arrive and leave, as well as the statistical input link, acting as an interface for its connection to the switching circuit.

The connection of the switching circuit with the statistical output link is made through the statistical bus, which will access the driver through a flip-flop.

Each switching circuit is basically constituted by the following blocks. Namely: - Statistical receiver.

- Statistical transmitter.

- Frame memory controller.

- MIC switching matrix.

- Controller of access to internal resources.

- Loop controller.

The statistical receiver is responsible for identifying and storing the frames arriving through the statistical input link, connected to its switching circuit, and by controlling the frame memory controller, it will store the received frame in the frame memory.

First, the statistical receiver synchronizes the data received with the local clock, which will be of the same frequency as the clock frequency with which the data was sent, although it may have phase difference.

The microprocessor indicates to the statistical receiver when it must extract a frame and from which address of the frame memory it should store it.

The statistical receiver verifies the integrity of the received frame and indicates to the microprocessor the errors detected during the reception of the frame, and if the frame is correct, it decodes the header of the frame and informs the microprocessor of the completion of the reception of the frame. same, as well as the value of the frame header.

Once a frame has been received and processed, the statistical receiver is waiting for the microprocessor to indicate that it must extract another new frame.

The statistical transmitter, under the control of the frame memory controller, extracts the frames from the frame memory and sends them through one of the statistical output links, connected to the device for packet switching and pulse modulation frame channels. coded object of this invention.

The aforementioned transmission is carried out under the control of the microprocessor that indicates, to the statistical transmitter, from which address of the memory is the frame to be transmitted and by which of the statistical output links it must exit.

When the statistical transmitter receives a transmission command, VÓI copying the content of the frame memory in the statistical output link, until it finds an end of frame indication in the memory.

The statistical transmitter informs the microprocessor that it has finished sending the frame and is waiting for another new order to send it.

The statistical transmitter synchronizes the outgoing frame with the local clock.

The frame memory controller coordinates the accesses to the frame memory and the accesses can come from the statistical receiver when it needs to write a frame or the statistical transmitter when it needs to read a frame, or by the frame memory controller itself, when you need to refresh the frame memory.

The switching matrix MIC of each switching circuit is related to the matrices of the remaining switching circuits belonging to the device for switching packets and channels of coded pulse modulation frames object of this invention, to jointly perform the switching function of the MIC channels.

Each of the matrices controls a MIC input link and an MIC output link.

In order to carry out the switching, each of the MIC switching matrices indicates, sequentially, the others the address of the channel through which the data that must come through the channel that it controls has arrived.

The matrix responsible for the channel through which the data has entered will place them on the circuit-switching bus common to all the commutation matrices, so that the first matrix can read them.

It is controlled by the microprocessor, which programs a memory of the MIC switching matrix with the information of said assignment.

Under supervision of the same microprocessor, the information that comes out of each channel can be a replica of a progrble repeating pattern.

The internal resource access controller facilitates communications between the microprocessor and each of the blocks of the switching circuit, taking care that the signals have the appropriate timing and that the accesses are carried out in an orderly manner.

The loop controller allows the realization of closed loops between the statistical receiver and the statistical transmitter, as well as between the input and output of the MIC switching matrix.

This type of closed loops are very useful for conducting tests on the circuit and on the printed circuit board.

DESCRIPTION OF THE DRAWINGS To complement the description that is being made and in order to help a better understanding of the characteristics of the invention, this descriptive report is accompanied, as an integral part thereof, three sheets of drawings in which illustrative and not limiting, the following has been represented: Figure number 1. - Corresponds to a block diagram of the device for the switching of packets and channels of coded pulse modulation frames object of the invention.

Figure number 2.- Also shows in a block diagram, a switching circuit.

Figure number 3.- Corresponds finally to - a block diagram of the MIC switching matrix block.

PREFERRED EMBODIMENT OF THE INVENTION In view of these figures, it can be observed how the device for the switching of packets and channels of modulated pulse-encoded frames that is recommended, is constituted from a micro-processor (1), eight switching circuits (2), eight frame memories (3), an internal communication bus (9), a statistical bus (7), a circuit switching bus (8), eight input / output drivers (4) and eight flip-flops (5).

To the driver (4), one for each switching circuit, the statistical links and the MIC links arrive and leave, acting as an interface for their connection to the switching circuit (2).

The connection of the switching circuit (2) with the statistical output link is made through the statistical bus (7), which will access the driver (4) through the flip-flop (5).

The input of the statistical link to the switching circuit (2) is the input (6) and the input and output of the MIC links are respectively the input (24) and the output (25).

Following the figure number 2, a block diagram of the switching circuit (2) is observed, which basically consists of a statistical receiver (11), a statistical transmitter (12), a frame memory controller (10), a MIC switching matrix (14), an internal resource access controller (26) and a loop controller (13).

The statistical receiver (11) is responsible for identifying and storing the frames arriving through the statistical input link (6) through the multi-plexer (28), and communicating with the frame memory controller (10), for store the contents of the received frames in the frame memory.

First, the statistical receiver (11), synchronizes the data received with the local clock, detects the carrier and the flag of the beginning of the frame.

The microprocessor (1) indicates to the statistical receiver (11) when it must extract a frame and from what address it must store it in the frame memory (3).

The statistical receiver (11), under the control of the frame memory controller (10) and with the help of the ultiplexer (16), will store the received frame with all its fields, not checking its CRC.

Likewise, the statistical receiver (11) verifies the integrity of the received frames and indicates to the microprocessor (1) the errors detected during the reception thereof.

If the error detected by the statistical receiver on the received frames occurs before receiving the level header (3), it will suspend the reception of the frame and post the error, waiting for the microprocessor to indicate that it must extract another new plot If the error is detected after receiving the level header (3), it will suspend the reception of the frame, insert a flag sequence in the area of the frame, where the error condition is detected and store it in the frame memory (3), as if it were a correct plot, and will account for the error.

In the case that the received frame is correct, the statistical receiver (11) decodes the header of the frame, and informs the microprocessor (1) of the value of said header, as well as of the end of the frame, being then the Wait for the microprocessor (1) to indicate that it must extract another frame.

The access of the microprocessor (1) to the internal resources of the switching circuit (2) for its initialization, programming or control, is carried out through the internal switching bus (9).

The statistical transmitter (12) extracts, under the control of the frame memory controller (10), the frames of the frame memory (3) and sends them to the loop multiplexer (29), whose output is connected to the buffers of access to the statistical bus (7).

The microprocessor (1) indicates to the statistical transmitter (12) from which address of the frame memory the frame to be transmitted is found, and by which of the access buffers to the statistical bus (7) it must exit.

Upon receiving the transmission order, the transmitter (12) copies the content of the frame memory into the indicated output buffer, until finding the end of frame flag.

The statistical transmitter (12) informs through a register destined for this purpose of the completion of the transmission to the microprocessor (1).

The statistical transmitter (12) is responsible for synchronizing the outgoing frame with the local clock, as well as activating the corresponding buffer for accessing the statistical bus (7).

The statistical bus (7) is the physical support of the packet switching, the statistical transmitters (12) of the eight switching circuits (2) related to each other being connected to said bus.

The statistical bus (7) supports the transfer of frames from a switching circuit (2), through a flip-flop (5), to the driver (4) of a statistical output link.

The frame memory controller (10) controls the accesses made by both the statistical receiver (11) and the statistical transmitter (12) to the frame memory (3), as well as the refresh of it.

The frame memory controller (10) assigns the access times to the frame memory (3) and the accesses, except the refresh, are performed without interruption.

To avoid contention situations, between two operations followed by reading or writing should not take more than 3 '906 microseconds.

In a time never exceeding 3 '906 microsegun-dos, the three access operations are performed in the following order. Namely: A.- Writing.

B. - Reading.

C. - Soda.

The multiplexer (16) physically supports access to the frame memory (3), allowing the signals generated by the blocks that can access it to pass to said memory, and the multiplexer (16) is controlled by the memory controller of frames (10), according to the time intervals assigned to each block.

The switching matrix MIC (14) of each switching circuit (2) is related to the seven remaining matrices of the device for packet switching and encoded pulse modulation frame channels, to jointly perform the switching of the MIC channels .

Each of the switching matrixes MIC (14) of each switching circuit (2) performs control of an input link and an output link.

In order to carry out the switching, each of the MIC matrices (14) indicates sequentially and through the circuit switching bus (8) to the other matrices the direction of the channel through which the data that must come through the channel has arrived. that she controls.

The matrix MIC (14) responsible for the channel through which the data has arrived will put them on the circuit switching bus (8) so that they can be read by the first one.

The circuit switching bus (8) is the physical means by which the switching between the MIC receiver channels and the MIC transmitter channels of the eight switching circuits (2), integrating the device for packet switching and channeling of the frame modulation by encoded pulses.

The circuit switching bus (8) is a multiplexed data and address bus and accesses the eight switching circuits (2) with eight input / output lines.

The assignment of which data must be output in each of the MIC channels is controlled by the microprocessor (1), which programs a memory of the switching matrix MIC (14), with the information of said assignment.

Under supervision of the microprocessor (1), the information that comes out of each channel can be a replica of a programmable repeating pattern.

The internal resources access controller (26) facilitates communications between the microprocessor (1) and each of the blocks of the switching circuit (2).

The internal resources access controller (26) knows the element, either register or memory, where it is desired to access from the internal communication bus (9), as well as the type of operation to be performed.

The accesses are made at the moment they are requested from the internal communication bus (9).

The loop controller (13) controls the realization of loops between the statistical receiver (11) and the statistical transmitter (12), as well as between the statistical input (6) and output (7) links.

Continuing with figure number 3, the block diagram of the MIC switching matrix (14) can be observed.

The control of the accesses of the switching matrix MIC (14) to the circuit switching bus (8) is carried out by the control block (15), which knows the instant when the circuit switching bus can be accessed. (8) to carry out an operation.

The receiver block (27), synchronizes the frame that enters the input link (24) through the multiplexer (22), monitors and generates synchronism alarms, performs the reading of the sample of an incoming channel and stores it in the sample memory (17).

The sample memory (17) is a memory size 32 by 8, in which the receiver (27) writes the samples of the 32 channels of the MIC frame, and each memory position is associated with an incoming channel.

The channel allocation memory (20) associates each outgoing channel with a switching circuit (2) and its incoming channel.

Likewise, the channel assignment memory (20) will contain the condition of whether the data sample collected from the circuit switching bus (8) or the programmable pattern is sent by the outgoing channel.

The channel allocation memory (20) has a capacity of 32 by 9 and will be updated dynamically from the microprocessor (1) through the internal communication bus (9).

The transmitter (21) of the MIC switching matrix (14) is responsible for decomposing and transmitting the outgoing frame by the multiplexer (23) the MIC output link. (25), either the sample entered by the MIC input link or the programmable pattern.

The block (18), represented the data output buffer of the circuit switching bus (8) and the block (19) the address output buffer.

The loop controller (13) controls the realization of loops between the transmitter (21) and the receiver (27) of the MIC switching matrix (4), as well as between the receiving MIC link (24) and the transmitting MIC link ( 25).

It is not considered necessary to make this description more extensive so that any expert in the field understands the scope of the invention and the advantages derived therefrom.

The materials, shape, size and arrangement of the elements will be subject to variation, provided that this does not entail an alteration to the essence of the invention.

The terms in which this report has been described - they should always be taken in a broad and non-restrictive sense.

Claims (3)

R E I V I N D I C A C I O N S

1. - Device for the switching of packets and channels of encoded pulse modulation frames, consisting of a series of switching circuits (2), a microprocessor (1), a series of frame memories (3), output drivers (4), and flip-flops (5), characterized in that the switching circuits (2), are connected to each other by the statistical bus (7) and the circuit switching bus (8), each one accessing of said switching circuits (2), to an external frame memory (3) and to an input / output driver (4), working said switching circuits (2) together, and being governed by the microprocessor (1), being interconnected through the internal communication bus (9).

2. - Device for the switching of packets and channels of coded pulse modulation frames, according to the first claim, characterized in that the switching circuit (2) is constituted by a statistical receiver block (11), a statistical transmitter block (12) , a frame memory controller block (10), a MIC switching matrix block (14), an internal resource access controller block (15), and a loop controller block (13), connecting within a device switching of packets and channels of encoded pulse modulation frames, to other switching circuits (2), identical according to a channel allocation table established by the microprocessor (1) and carrying out the switching of channels of MIC frames by means of the request, by the switching circuit (2), which must emit, from a channel to the switching circuit (2) -. that received the information that must be sent, outputting any of the output links to any input link or sending a repeatable programmable pattern, under the coordination of the internal resources controller (26) that facilitates microprocessor communications ( 1) with the various blocks of each switching circuit (2).

3. - Device for the switching of packets and channels of coded pulse modulation frames, according to the first and second claims, characterized in that it establishes loops in the data paths between the block (11), statistical receiver, and the block (12), statistical transmitter, as well as between the output and input channels of the block (14) MIC switching matrix. - SUMMARY - Device for the switching of packets and channels of encoded pulse modulation frames, consisting of a statistical receiver block (11), a statistical transmitter block (12), a frame memory controller (10), a MIC switching matrix (14), an internal resource access controller (26) and a loop controller (13), all of these blocks constituting a switching circuit (2), which in the number of eight are incorporated in the device together with a microprocessor ( 1), eight frame memories (3), an internal communication bus (9), a statistical bus (7), a circuit switching bus (8), eight input / output drivers and eight flip-flops (5).