MXPA97004596A - Bidirectional radio system with frequency in crystal - Google Patents

Abstract

The present invention relates to a device for decoding a coded analog signal that suffers from an amplitude modulation to determine described output values, where the discrete output values include a first non-zero value and a null value, comprising: A first device for comparing a first component of the coded analog signal with a threshold value, and if the first component is greater than the threshold value then the first device to match sets a first discrete output value equal to the first non-zero value, and if the first component of the coded analog signal is smaller than the threshold value then the first device for comparing sets of discrete output values equal to one of a set of discrete values, where the set of discrete values includes a null value; and a first device for modify the threshold value by adding a first error signal multiplied by a first reduction factor, if e The first of the discrete output values is the null value, then the first device to modify sets of the first error signal is equal to 0, and if the first of the discrete output values is the first non-zero value, then the first device for modifying sets of the first error signal equal to a difference between the first component of the coded analog signal and twice the umbr value

Description

SYSTEM. OF BIDIRECTIONAL RADIO WITH SYNCHRONIZED FREQUENCY BACKGROUND OF THE INVENTION The present invention relates in general to bidirectional radio communication systems, and in particular to bidirectional radio communication systems where a transceiver transmits frequency reference information to other transponders, where the communication system of radio provides and a load control or use control of props. In a typical two-way radio communication system, a base station operating on a frequency transmits to a remote station and the remote station transmits back to the base station on a related frequency. The relationship between the transmission frequencies of base stations and remote stations is determined by the license rules of the Federal Communications Commission (FCC) copies. For example, in the multi-address system band, the base station and the remote frequencies are separated by 24 megahertz. A dual radio communications system becomes problematic when high performance communications are required with a large number of stations spread over a large geographic area. A transmitter of the base station in communication with several remote stations will have a performance determined by the efficiency of the bandwidth, measured in bits per second per hertz. High bandwidth efficiency transceivers are prohibitively expensive in systems that require many remote transducers. In addition, if a powerful base station transmits over a large area, there will be regions with poor reception, ie dead spots, due to geographical irregularities. Alternatively, performance can be increased by transmitting a plurality of channels within a band approved by the FCC. This is known as frequency division multiplexing. The cost of this approach is generally the increase in frequency accuracy required by radio transmitters. Frequency division multiplexing offers the additional advantage that frequencies can be spatially reused; transmission regions (cells) that use the same channel frequency pair are separated by cells using different channel frequency pairs, thereby minimizing interference. The performance of these systems is equal to the product of the bandwidth efficiency, the number of cells in the system and the bandwidth of the channels. Precise frequency control is conventionally achieved by using quartz crystal resonators. With careful manufacturing techniques and control of temperature effects, a precision of a few parts per million can be obtained. Another conventional frequency control technique uses feedback loops. For example, a tranceptor in conjunction with another tranceptor with a precise channel can generate highly accurate signals using two oscillators. First the signal is heterofinia with an intermediate frequency, and then a precise local oscillator in the intermediate frequency heterodynes, the signal of intermediate frequency to the base band, where the frequency and phase errors of the intermediate frequency can be measured. This error is returned to feed the first oscillator to correct its frequency. With current technology, reduced frequency spacings can only be achieved by using an external source for a high stability frequency reference, such as WWV, GPS or LORAN. The additional cost of including this refined capacity in each radio within a system is prohibitive for many applications, where the low cost of two-way radio communication can produce substantial economic benefits. An object of the present invention is to provide a high performance bi-directional radio communication system between at least one base station and a large number of remote stations. In particular, an object of the present invention is to provide a low cost method of generating radio signals at remote stations with a frequency accuracy necessary to provide frequency division multiplexing. Another object of the present invention is to provide a low cost method of generating a high precision transmission channel in a remote station using both the information contained in the reception channel and information in the modulation of the channel, particularly the signal clock . Another objective of the present invention is to provide a radio communication system, where high data throughput at low cost is achieved by frequency synchronization, frequency division multiplexing and time division multiplexing. Another object of the present invention is to provide a receiver for decoding short frequency increments of data from a plurality of transmitters. Another object of the present invention is to provide a low increment data demodulator with a recoding threshold that can be adapted. Another object of the present invention is to provide a tranceptor with an accurate transmission frequency that does not use a closed path of analog phase closing oscillators.

Another objective of the present invention is to provide a radio system with a precise transmission frequency that only uses one frequency control loop. Another object of the present invention is to provide a radio system with an accurate transmission frequency that uses a closed frequency control circuit and shares a rotator between the transmission and reception sides of the circuit. Another objective of the present invention is to simplify the circuits of a receiver with clock and channel frequency recovery. In particular, it is an object of the present invention to simplify the circuits of a receiver with clock and channel frequency recovery and by providing a reception circuit which is coupled with transmission circuit to produce transmission channel stabilization, providing an independent clock and a channel frequency recovery of the received signal, and providing a closed phase closure circuit in the baseband, rather than the intermediate frequency level. Additional objectives and advantages of the invention will be specified in the following description, and this will be partly obvious from the description or may be learned by practicing the invention. The objects and advantages of the invention may be obtained by means of instrumentalities and combinations particularly specified in the claims.

SUMMARY OF THE INVENTION The present invention is directed to bidirectional communication systems, wherein a tranceptor of the base station transmits signals with a highly accurate clock over a highly accurate channel frequency, and a remote station tranceptor receives the signals of the station. base and extracts the clock and channel frequency information from the received signals. The remote station uses the extracted information to stabilize the channel frequency of the remote station. The radio system of the present invention provides high performance bidirectional communications between a large number, possibly thousands, of remote stations receiving information and a plurality of base stations. The system maximizes the data throughput by transmitting over a plurality of frequency (frequency division multiplexing) channels within, for example, a 12.5 kilohertz bandwidth of the FCC. The communication region is divided into cells, where a base station by neighboring cells and cells uses different channel frequencies. Each base station transmits a continuous flow of signals. The signals give instructions to remote stations inside the cell to respond with various types of information. The transmissions of the remote station are multiplexed with time division, that is, the rhythm of the responses of the remote station are specified by the signals received by the remote stations. The base station is adapted to decode very short increments of response data transmitted from the remote stations. The present invention produces the frequency accuracy required for frequency division multiplexing, while incurring the cost of better accuracy at base stations. This is achieved by using the combination of the channel frequency of the base station and the frequency included in the modulation of the base station, specifically the digital signal clock, to accurately generate the transmission frequency of the remote station from the transmission signal of the base station. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are incorporated in and constitute a part of the specification, schematically illustrate a preferred embodiment of the invention and, together with the above-specified general description of the detailed description of the preferred embodiment given below, it works to explain the principles of the present invention. Figure 1 is a exemplary geographic diagram and schematics of the communication system of the present invention. Figure 2 is a graph of frequency versus power of the power spectrum of the four frequency channels within the power spectrum of 12.5 kHz approved by the FCC for radio transmissions. Figure 3 is a schematic flow chart of the base tranceptor circuits of the present invention. Figure 4 is a schematic flow diagram of the remote transceiver circuits of the present invention. Figure 5 is a schematic flow chart of the continuous data demodulation circuits of the remote transceiver. Fig. 6 is a schematic flow chart of the base wave tranceptor data waveform demodulation circuits. Figure 7 is a schematic flow diagram of a wave increment modulator with threshold value that is adaptive. Fig. 8 is a schematic flow chart of a first alternative mode of bidirectional radio frequency synchronized transceiver. Fig. 9 is a schematic flow diagram of a second alternative mode of synchronized frequency bidirectional radio tranceptor.

Figure 10 is a schematic flow diagram of an alternative embodiment of the continuous data demodulator where the rotator can be placed in the transmission and reception portions of the tranceptor circuit of Figure 9. DETAILED DESCRIPTION OF THE PREFERRED MODALITY Overview The present invention is will describe in terms of the preferred embodiment. The preferred embodiment is a device and method for bidirectional radio communications of synchronized frequency. In Figure 1 a schematic geographic diagram of the bidirectional radio system of the present invention is shown. The master system 40 is the central control system and information processor. The master system 40 can communicate via telephone lines 42 with several base stations 44, collecting information acquired by the base station 44 and sending base instructions 44. The instructions specify what type of information should be collected, and when. These base stations transmit a continuous radio frequency signal 48 to several remote stations 46 in accordance with the instructions received from the master system 40. The remote stations 46 are possibly located in a very dense geographical region. Each remote station 46 communicates with one or more location units (not shown). Place units can, for example, control the consumption of electrical energy in homes, the status of anti-theft alarms, or control the functions of electrical devices within homes. Each base station 44, and the group of remote stations 46 with which the base station 44 communicates, comprises a cell 50. The remote stations 46 transmit information they collect in brief "increments" of radio communication to the base station 44 within of the cells 50 in the times specified by the base station 44. The communications of the base station 44 / remote station 46 consist of two modes: in the fast instructions mode, the transmissions of the base station 48 instruct the remote stations 44 within the cells 50 to report base 44 by radio communication if it has information ready to be transmitted. Once the base station 44 determined which remote stations 46 have data that can be transmitted, the transmissions from the base station 48 instruct the remote stations 46 with information to respond. Each transmission of the base station 44 specifies which remote stations 44 were the ones that received the transmission, what type of information of the remote receiving stations 46 should be transmitted, how far the remote stations 46 must wait before transmitting, and how long it should be transmitted. be the response of the remote station 46.

The format of the communications between the base station 44 and the remote station 46 is described in U.S. Patent No. 4,972,507, issued November 20, 1990, which is incorporated herein by reference. To minimize radio interference between the cells 50, the base stations 44 and remote stations 46 of neighboring cells 50 transmit at different frequencies. The more frequency of transmission is used in the system, the greater the space between the cells that uses the same frequency, and the less interference there is between cells. Because the present invention provides accuracy of frequency and stability of remote parking channels at low cost, the communication system of the present invention utilizes a multiplicity of channel frequencies that are closer than those conventionally used. For example, as shown in Figure 2, the present embodiment uses 4 channels 90, 92, 94 and 96 within a bandwidth of 12.5 kHz conventionally reserved by the FCC to a single channel. It should be understood that the amplitude of the FCC band and the number of channels per band may vary and the bandwidth of 12.5 kHz and 4 channels discussed herein are by way of example only. Channels 92 and 94 are out of phase by +/- 1041.67 Hz, and channels 90 and 96 are out of phase by +/- 3125 Hz of the center frequency, and the power peak of each channel is 6 decibels below the maximum allowed (0 dB). It is well known in the art that 9QPR coding of a signal provides a bandwidth efficiency of 2 bits per second per hertz. In the 9QPR data encoding the sine components are encoded as the cosine (or in phase and quadrature) of a channel. See Digital Transmission Systems, by David R. Smith, Van Nostrand Reinhold Co., New York, New York 1995, section 6.4, pages 251-254, which describe in detail 'the 9QPR coding, and is incorporated herein by reference. The frequency space of approximately 2083 Hz between channels 90, 92, 94 and 96, allows a transmission of 2400 bits per second in each channel, with guard bands of almost 1000 Hz between bands. The envelope 98 extending between the points (-6.25 KHz, -10 dB), (-2.5 KHz, or dB), (2.5 kHz, or dB) and (6.25 kHz, -10 dB) describes the allowed power distribution by the FCC for radio signals within a bandwidth of 12.5 kHz. Clearly, the sum of the power distribution of these four channels 90, 92, 94 and 96 falls within the limits of the FCC criteria. BASE transceiver CIRCUITS Figure 3 shows a mode of the base tranceptor 52 of the present invention. The base station tranceptor 52 communicates by radio with the remote station transceivers 46 within the cells 50, and by telephone line 42 with a master system 40. The processor 103 of the tranceptor 52 processes information 101 of the remote stations 46, as it will be discovered below, and transmitted on the telephone line 42 to the master system 40. The processor 103 also receives instructions from the master system 40 via telephone line 42 and translates these instructions into a continuous stream of digital data 100 and which is also transmitted to the remote stations 46, which will also be described below. The digital data stream 100 is sent to an encoder 104 which performs differential coding of the bitstream to prevent the propagation of errors in the data stream. The even and nons bits of the data stream 100 are separated into two separate data streams 106 and 107 and sent to the digital filters 108. The digital filters 108 perform a pulse formation to reduce the spectral amplitude of the transmitted signal, of this mode increasing the bandwidth efficiency of the filtered signals 114 and 115. The clock 110 generates a high-precision clock signal 111 which sets the data flow rate again from the encoder 104 to the digital filters 108 to a total of 2400 bps, that is 1200 bps for the even and odd bit streams.

The base station 44 has a channel frequency synthesizer 112 which produces a sinusoidal channel signal 113 of, for example, 952 MHz from a high precision reference frequency source. The current technology allows the generation of a channel signal 113 with a frequency stability of a part of 109 per day and an accuracy of approximately 5 parts in 109. The filtered signals 114 and 115 are transmitted from the digital filters 108 to a quadrature modulator 118 where the 1200 bps signal 114 is modulated to the sine component of the channel signal 113, and the 1200 bps signal 115 is modulated in the cosine component of the channel signal 113 to produce a modulated signal of 9QPR 120 with bandwidth efficiency of 2 bps per hertz. The signal of 120 is amplified by the transmission amplifier 122 and the amplified signal 123 is sent to the diplexer 124. The output signals of the channels of the diplexer 123 to the antenna 126 for transmission to the remote stations 46, and the channels of incoming radio communications of the antenna 126, i.e., of the remote stations, to the output of diplexer 128. In accordance with the FCC specifications for the radio spectrum, multiple access systems are relegated to frequencies close to 952 MHz, and the transmission / reception frequency pairs are separated by 24 MHz. The incoming signals to base transceiver 52 at, for example, 928 MHz are received by antenna 126, and directed by diplexer 124 towards the output of diplexer 128. The diplexer output 128 is amplified by the reception amplifier 130, and transmitted to a superheterodination mixer 132. There the signal 134 becomes heterodyne with the signal of the channel 113 generated by the channel synthesizer 112 to produce an intermediate frequency signal 136 in a 24 MHz channel. The 24 MHz 136 signal passes through a selective filtering of gain in an intermediate frequency (IF) amplifier 138, and the sine and cosine components 140 and 141 of the output of the amplifier IF 139 are separated by the separator 146 and heterodinized by the heterodynes 140 and 143 with the phase and quadrature signals of 24 MHz 144 and 145 generated by the synthesized oscillator 148. The signals of 24 MHz 144 and 145 are generated from the clock signal 111 by the synthesized oscillator 148 which increases the clock frequency by a factor of 2xl04. The heterodynes 142 and 143 output the baseband signals 150 and 151. The analog baseband signals 150 and 151 are then converted to digital form and digitally filtered by digital filters 154 and transmitted to an increment demodulator 156. The increment scrambler 156 is designed to provide decoding of short data increments. In this preferred embodiment, the demodulator 158 can handle data transmissions that can be as short as 3 bist whose length can be up to 6 bits (3 symbols). To enable this rapid decoding without losing information, the first symbol transmitted via a remote station 46 to the tranceptor 52 is a reference symbol of known amplitude and phase. The increment demodulator 156 is shown in greater detail in FIG. 6. The explosion demodulator 156 allows error-free decoding of short data pulses by making the phase and amplitude scaled by the phase and amplitude of the signal. initial reference signal. The quadrature encoded signals of the baseband 400 and 401 are converted in quadrature (or rectangular) form to polar form in a rectangular to polar converter 404. In the polar form, the signal has an amplitude component 406 and a component of phase 407. During a time interval of reference symbols, the amplitude and phase of the first symbol are linked by the scale monitor 409 and the deflection monitor 411. The amplitude of the first symbol 408 is then transmitted to the multiplier 405 which makes a scale of all subsequent amplitude symbols 406 in the increment. Similarly, the phase of the first symbol 412 is sent to the summing circuit 413 to scale the phase of all subsequent symbols 407 in the increment. This ensures that the random phases of the baseband signals 400 and 401 are compensated and the data coding thresholds are appropriately aligned at the scale outputs 410 and 414. Since the different remote radio channel frequencies 46 may vary by In small quantities, a frequency error compensator is also needed in the increment demodulator 156. This is instrumented by a phase detector 426 which determines the signal phase 420 and transmits a phase information signal 422 to a phase estimator. ramp 416. The ramp phase estimator 416 generates a ramp voltage 421 that increases linearly in amplitude with respect to time at a rate proportional to the super frequency error in the baseband signals 400 and 401. The summing circuit 408 sum the phase signal 414 and the voltage of 421 to scale the phase, thereby effectively correcting any frequency errors at output 420 The phase amplitude signal 410 and 420 are reconverted to rectangular signals 430 and 431 in the polar to rectangular converter 428. The data recovery can then be performed in the data recovery circuit 434 and the recovered data 276 is transmitted to the processor A preferred mode of the data recovery circuit 434 of Figure 6 is shown in detail in Figure 7. This data recovery circuit 434 additional devices to compensate for a change in amplitude of the received packet, since the propagation path will sometimes be such that the initial scaling factor determined by the 409 scale monitor will not be accurate at the end of the increment. The data recovery circuit 434 evaluates the incoming analog signals 430 and 431 to determine their digital values by comparing the values of the analog signals 430 and 431 with the encoder thresholds. For 9QPR modulation, the symbol values are nominally +1, 0, and -1, and the encoding thresholds must be +0.5 and -0.5. If a signal has a value between +0.5 and -0.5, it interprets as 0 if the signal has a value at +0.5 is interpreted as 1 and if the signal has a value less than -0.5 it is interpreted as -1. However, if the received signal has an unexpected loss of amplitude, then it is quite possible that the non-zero values are misinterpreted as having a value of 0. The erroneous scales of the scale monitor 409 may therefore cause data recovery errors. because the encoder thresholds are no longer appropriate. The data recovery circuit 434 of FIG. 7, accordingly, is adjusted and the threshold values adapted according to the amplitude of each bit of the received signal. The threshold is started at a THRESHC value for the first bit of the packet, and the scale monitor 409 scales the first part of the signal so that THRESH0 is at a midpoint between the values of a +1 and 0 bit. Conforma continues the packet and possibly change the amplitude due to the decrease the values shown I and Q possibly change, and the value THRESH is updated by the following procedure the digital values and i-éclrao the digital values écimos I0ut (1) and Qout (1) are determined by the analogous input values Iinli) and Qin. { i) of the phase and quadrature signal components by the phase and quadrature encoders 520 and 522 respectively, using the thresh-i threshold value (i-l) provided on line 545. If the signal in phase i emiim I; L) has a value greater than the threshold value (il) écirao THRESHi_ ?, the encoder in phase 520 interprets Im'11 as +1 (that is, it provides a value Iout * 1 'of +1), if the signal in phase i ecímaGR. (i) has a value less than the negative of the threshold value (iD éécciimmoo (-1? THRESHi_1) the encoder in phase 520 interprets Iin (1) as -1, and if the signal in phase i ecíma Iin (i) has a value greater than the negative of the threshold value (ii) écirno (-1 x THRESHi-i) and less than the threshold value (ii) écim ° THRESHi-i, the encoder in phase 520 interprets Iin as 0. Similarly, if the signal of quadrature i ecima Qin (i) has a value greater than the threshold value (ii) écip * ° THRESHi-i, the quadrature encoder 522 interprets Qinli) as +1, if the quadrature signal Qin í) has a lower value than the negative of the threshold value (-1 x THRESHi-i), the quadrature encoder of 522 interprets Qln (1) as -1, and if the quadrature signal Qin (il has a value greater than the negative value of the threshold value (- 1 x THRESHi-i) and less than the threshold value THRESHi_ ?, the quadrature encoder 522 interprets Qin (il as 0.) For each bit of the signal, double the threshold value (il) is subtracted. m ° THRESHi-a of line 545 of the absolute values of the quadrature components in phase i ekimos lin (1) 0 and Qin (i) on lines 430 and 431 in the quadrature and phase comparison units 510 and 512, respectively. The outputs of the quadrature and phase comparison units 510 and 512 are routed to the phase and quadrature switches 516 and 518. The value 0 is also directed to the phase and quadrature switches 516 and 518 on line 515. The choice of the inputs to the switches 516 and 518 are dependent on the output values in phase and quadrature Iout (i) Qout111. If Iout11 'has a value of 0, the output 0 on line 515 is output on line 523 of the switch in phase 516. However, if Iout' 'has no value of 0, then the output of the comparison unit in phase 510 is the output of the switch in phase 516. Similarly, if Qout (il has a value of 0, output 0 on line 515 is the output on line 524 of quadrature switch 518 and if Qout * 11 does not have a value of 0, then the output of the quadrature comparison unit 512 is the output of the phase switch 518. The outputs on the lines 523 and 524 are summed in the summing circuit 525, and the sum is multiplied by a factor of reduction R to a multiplier 530 to produce a reduced sum on line 531. In the preferred embodiment, the reduction factor R has a value of 1/32. (Provides a preferred range of values for the reduction factor R). The reduced sum on line 531 is then added to the value { ii) the middle of the threshold THRESHi-i in a second adder 535, where the value (i-l) écim ° of the threshold is stored by the delay unit 540. Mathematically, the tenth value of the threshold THRESHi is given by THRESHi = THRESHi-! + R * Iout (i | * (Iin (i) - 2 * THRESHI_1) + R * Qout (il * (Qin (i> - 2 * THRESHi-i) where R is the multiplication factor in the 530 multiplier unit Remote tranceptor circuit The remote tranceptor 54 shown in figure 4 relieves data 205 acquired in the units of place (which does not appear) to a base station 44 by radio transmissions.The receiver 54 receives data 205 from the units of place and processes the information to form data packets 200 of the instruction stream 276 transmitted by a base station 44, as described below: The data packets 200 are first sent to an encoder 204. Like the encoder 104 in the base station tranceptor 52, this encoder 204 separates the data packets 200 into even and odd bits and performs differential coding on the data streams The resulting even and nons data streams 206 and 207 respectively, are digitally transmittable 208 stop r forms the signal spectrum.

A clock signal 211 of the clock 210 controls the processing rate of the encoder 204 and the digital filters 208. The even and nonspecific data streams 214 and 215 of the digital filters 208 are then modulated by a quadrature modulator 208 to produce a 9QPR signal. on channel 213 generated by a channel synthesizer 212. Through the feedback mechanism described below, the synthesizer 212 has a precisely controlled frequency of, in this case, 928 MHz. A transmission amplifier 222 is activated by an increment port 223 when the remote station 46 transmits data to a base station 44. The amplified signal 225 of the amplifier 222 is directed through diplex 224 to an antenna 226 for transmitting it to the base station 44. The input signals of the base station 44 are received by the antenna 226 and, transmitted by the diplexer 224 to a reception amplifier 230 and heterodyned in a mixed super heteronizer 232 with the locally generated channel 213 to convert it to the input signal 234 to an intermediate frequency signal 236. Since the reception frequency is 952 MHz and assuming that the output of the channel 213 of the synthesizer 212 is exactly 928 MHz, the channel of the intermediate frequency signal 236 is 24 Mhz. But any error in the output of 213 of the sinter 212 causes a deviation in the frequency of the intermediate frequency output 236 of 24 Mhz. The signal of. intermediate frequency 236 is then amplified by the intermediate frequency amplifier (IF 238). The phase and quadrature components 240 and 241 are separated from the amplified frequency signal 239 by the separator 246, and are heteronized by the mixers 242 and 246 with quadrature and 24 MHz 244 and 245 signals generated by the oscillator. of glass-controlled voltage (VCXO) 248 to produce baseband signals 250 and 251. Signals 250 and 251 are then directed to analog filters 254 which process signals 250 and 251 to provide a better band pulse and rejection form of out-of-band signals to produce filtered baseband signals 266 and 267. The data recovery of the filtered baseband signals 266 and 267 is performed by the continuous data demodulator 258. Ideally, the intermediate frequency signal 236 is modulated in a channel of exactly 24 Mhz, the VCXO generates sinusoids 244 and 245 at exactly 24 MHz, therefore the base band signals 250 and 251 have a channel of fr frequency 0. The frequency and phase of the baseband signals 250 and 251, and consequently the frequency and phase errors of the channel synthesizer 212 or VCXO 248 are measured by the continuous data demodulator 258 using conventional radio reception techniques. digital radio, or the channel recovery technique described below. The frequency error information 260 can be fed back to the channel synthesizer 212 to correct its frequency and minimize the aforementioned error in this way by effecting a closed phase closed circuit. For a high channel accuracy 213 of the channel synthesizer 212, it is necessary that the signals 244 and 245 of the VCXO 248 are also accurate, because any errors at the outputs 244 and 245 of the VCXO 248 can not be distinguished from the continuous data demodulator 258 of the errors of the remote channel synthesizer frequency 212.

The 24 MHz signals of 244 and 245 of the VCXO are synthesized from the recovered clock signal of 1200 Hz 264 generated by the continuous data remodulator 258. Since the copied clock signal generated in the base station transmitter 44 has a high precision, the 24 MHz 244 and 245 signals on the remote radio 46 also have high accuracy. Then the frequency error signal 260 generated by the continuous data demodulator 258 is an accurate representation of the channel frequency synthesizer error 212, and correcting this error causes the channel frequency synthesizer 212 to be accurate in frequency. The continuous data demodulator circuit 258 is shown in detail in FIG. 5. The signals 266 and 267 of the analog filters 254 are converted to digital in the two A / D converters 284 and 285, and the resulting digital signals 280 and 281 are multiplied by two multipliers 288 and 289 for producing amplified signals 290 and 291. Signals 290 and 291 are digitally filtered in digital filters 292 and 293 to reject out-band interference. The filtered signals 296 and 297 are transmitted A and B, respectively, of a rotator 300. The rotator 300 determines the amount of spurious mixtures of the phase and quadrature components in the signals 296 and 297 and reverses this mixing. The outputs A 'and B' of the rotator 300 consist of the mixtures: A '= A eos 0 + B without 0, and B' = -A without 0 + B eos 0, where 0 is the angle of rotation. A coast phase detector 306 determines the amount of the quadrature signal 302 (or equivalently the signal in phase in the signal 303). The ramp estimator 310 generates a phase error signal 311 which controls the amount of rotation 0 performed by the rotator 300 so that the signals 302 and 303 are converted into the phase and quadrature components, respectively, of the transmission. The ramp estimator also generates the frequency error signal 260 which is directed to the channel synthesizer 212 (see Figure 4) to stabilize the channel frequency 213, but not necessarily to the accuracy of the phase closure. The rotator 300 achieves the effect of closing the phase locally within the continuous data demodulator 258 and allows the synthesizer control to relax to only achieve a frequency closure. The continuous data demodulator 258 uses an automatic gain control algorithm to maintain a constant signal level over 24 dB of signal level variations. The amplitude estimator 312 calculates the sum of the squares of the signals 302 and 303 of the rotator 300 to generate an estimate of amplitude 313. The magnitude of the estimate 313 is instructed to invert the gain controls of the multipliers 288 and 289, of this mode stabilizing the amplitude of the signals 290 and 291. A preliminary estimate of the clock phase of the signals 302 and 303 are achieved by matching the signal 313 in an approximate clock estimator 316. The output 318 of the estimator 316 can be shown as that which has a peak in the sampling times of data having the appropriate clock phase, and therefore can be used as a rough estimate of the clock signal 111. A more accurate estimation of the clock frequency and phase are achieved in the fine clock estimator 320 when processing the magnitude of signals 302 and 303 at the nominal zero crossing times estimated by the approximate clock estimator 316. This generates to an error signal 264 that can be used to tune the VCXO 248, thereby setting it to 24 MHz. Since the calculation of the clock phase is independent of the channel phase and the frequency, synchronization can be achieved. clock before channel frequency synchronization is achieved. The decoding of the signals 302 and 303 is performed in the data recovery circuit 322 to produce the recovered data 276. The recovered data 276 is directed to the remote station processor 203 as shown in Figure 4. The recovered data 276 specify that .. information must be received at the remote station 46 from the location units, or transmitted to the base station 44. An alternative mode of a radio transceiver 544 according to the present invention appears in Figure 8. The tranceptor 544 operates as described in the first preferred embodiment 54 of Figure 4, except that in this tranceptor 544 the channel error signal 260 is sent to the inserted rotator 274. on the transmission side of the tranceptor 544, in place of the channel synthesizer 212, to effect the phase corrections by adding phase shift, and frequency corrections by continuously adding phase shifts that increase or decrease, towards the transmitted signal instead of the channel 213. In particular, this tranceptor 544 differs from the tranceptor 54 of figure 4 in that the transmission rotator 274 is positioned between the digital filters 208 and the quadrature modulator 218. The data signals of the baseband 214in and 215in are input of the rotator of transmission 274 provided by the digital filters 208, and the outputs 214out and 215out of the rotator of the transmission 274 are directed s to the quadrature modulator 218. The amount of rotation 0 produced by the transmission rotator 274 is controlled by the control signal 272 produced by the transmission phase ramp generator 270 based on the error signal 260 provided. by the continuous data demodulator 258 to produce translated signals of frequency 214out A1 and 215out B 'consisting of the mixtures: A' = A eos 0 + B without 0, and B '= -A without 0 + B eos 0, Where A and B are the baseband inputs 214in and 215in to the transmission rotator 274. By producing a frequency translation of the baseband signals 214in and 215in, the transmission signal 225 has a channel with an accurate channel frequency, although there is no phase closure or frequency closing in the circuit. Another alternative embodiment of a radio tranceptor 545 according to the present invention appears in Figure 9. The tranceptor 545 operates as described in the first preferred embodiment 54 of Figure 4, except that this tranceptor 545 combines a relatively close frequency closure of the channel synthesizer 212 using an error signal 260, with a rotation of baseband data signals 214in and 215in using a rotator 280 controlled by the control signal 311 of the ramp estimator 310 in the continuous data demodulator 258. (The output of the signal 311 of the continuous data demodulator 258 is not shown in Figure 5). In particular, this tranceptor 545 differs from the tranceptor 54 of Figure 4 in that the transmit rotator 280 is placed between the digital filters 208 and the quadrature modulator 218. The baseband data signals 214in and 215in enter the rotator. Transmission 280 and are provided by the digital filters 208, and the translated frequency signals 214out and 215out are output from the transmission rotator 280 and directed towards the quadrature modulator 218. The amount of rotation 0 produced by the transmission rotator 280 are controlled by a control signal 311 produced by the ramp generated from the reception side 310. As before, the translated frequency signals 214out A 'and 215out B' exit the transmission rotator 280 and consist of the mixtures: A '= A cos0 + B without 0, and B1 = -A sin0 + B eos 0, where A and B are the baseband data signals 214in and 215in and which are input for the transmission rotator. In the tranceptor 545 of FIG. 9, the frequency of the signal 213 produced by the channel 212 is corrected each time the frequency error exceeds a certain threshold amount of frequency, while the control signal 311 continuously controls the rotator of the signal. Transmission 280, and you only need to correct frequency errors up to the amount of frequency threshold. In this case, the closed feedback loop includes the conveyor synthesizer 212 and the continuous data demodulator 258 has a very low bandwidth, and therefore is easy and inexpensive for instruments. An advantage of this tranceptor 545 over tranceptor 544 of FIG. 8, is that a single phase ramp generator is needed since the ramp estimator 310 on the receiving side of the circuit also controls the transmitted signals 214out and 215out. In another alternative embodiment, the tranceptor only operates in a half-duplex mode (i.e., the transmission in the reception can not include simultaneously) and the transmit and receive sides of the circuit share the same rotator control signal 311 and the rotator 280. During the reception of the alternative continuous data demodulator 558 shown in Fig. 10 it functions as the continuous data demodulator 258 described above, except that the rotator is now marked by the reference number 280. During transmission, the system operates as described in relation to the tranceptor 545 of Fig. 9. The continuous data demodulator 558 of the alternative mode is detailed in Fig. 10.

During reception, switches 510, 515, 517, 525 and 527 are in positions Rx, and circuit 558 operates as described above in relation to figure 5, since the output of coast detector phase 306 is .. connected to the input of the ramp estimator 310, and the inputs A and B of the receiving rotator 280 are connected to the lines 296 and 297 of the digital filters 292 and 293, and the outputs A1 and B 'of the receiving rotator 280 are connected to lines 302 and 303 to data recovery circuit 322, Coasts phase detector 306, amplitude estimator 312 and fine clock estimator 320. During transmission, switches 510, 515, 517, 525 and 527 are in the Tx positions, and the circuit 558 operates as described above in relation to Figure 9, since the inputs A and B of the receiving rotator 280 are connected to the data transmission signals of the baseband 214in and 215in d e the transmission digital filters 208, and the outputs A 'and B1 of the reception rotator 280 are connected to the lines 214out and 215out with the quadrature modulator 218. However, in the transit mode, the switch 510 which controls the input to the ramp estimator 310 is open, so that the ramp estimator maintains the values of the control signal 311 and the channel error signal of 260 used during the previous reception. As in the case of Figure 9, the closed feedback path including the channel synthesizer 212 and the continuous data demodulator 258 has a very low bandwidth, and therefore its instrumentation is easy and inexpensive. With this embodiment of the continuous data demodulator 558, the total hardware costs are minimized, since the rotator 280 and the ramp estimator 310 are used on the transmission and reception sides of the tranceptor. In summary, a device for a bidirectional radio system of synchronized frequencies was described. It will be seen that the embodiment presented herein, consistent with the objectives of the invention for a two-way synchronized frequency radio system, provide a high-performance, low-cost radio system using multiplexing of frequency domains, multiplexing of time domain, frequency synchronization and spatial reuse of frequencies. The frequency synchronization of the remote stations 46 is provided by extracting the precise clock rate 111 and the channel frequency 113 from the base station 44, and using this information in the phase-closing circuits. In an alternative embodiment an increment scrambler continually updates the decoding threshold based on a comparison of the signal amplitude and the updated value of the decoding threshold. In another alternative embodiment, the channel synthesizer is not part of a closed path of the phase closure, but the transmitted signal rotated by a phase ramp proportional to a frequency error to provide a precise channel frequency. In yet another alternative embodiment, only one phase closure is instrumented, and again the transmitted signal is rotated by a phase ramp proportional to a frequency error to provide a precise channel frequency. In this alternative embodiment, separate rotators can be used on the transmission and reception sides of the circuit, or a single rotator can be placed between the transmission and reception sides of the circuit for half-duplex operation. While the above description contains many specificities, it should not be construed as limitations on the scope of the invention, but rather as examples of the preferred embodiments. Many variations are possible. For example: the increment demodulation adapter threshold unit can be adapted to demodulate a coded two-state signal where the high state has a signal value above the threshold, and the low state has a signal value below the threshold; the increment demodulation adapter threshold unit could be adapted to demodulate a single coded three state signal simply by using the upper half of the circuit of Figure 7; the increment demodulation adaptation threshold unit could be adapted to demodulate a signal with more than three states by making all thresholds multiples of the fundamental threshold value, or by independently updating multiple thresholds; there could be separate thresholds for the in-phase and quadrature components; the reduction factors for the quadrature components could be different; the multiplication factor R in the incremental demodulation adapter threshold unit could have a different value 1/32; communications between the master system 40 and the base stations 46 could be assigned more than four channels, or less, for each bandwidth of 12.5 KHz; the tranceptor circuits of the base station 44 and the remote station 46 could use other coding, filtering and modulation techniques; and the instruction formats could take many other forms. The modulation of channels 113 and 213 are not necessarily 9QPR, quadrature modulation or digital modulation, but could be of any type of modulation. The present invention was described in terms of a preferred embodiment. However, the invention is not limited to the modality shown and described. Rather, the scope of the invention is defined by the appended claims.

Claims (8)

1. CLAIMS 1. A device for decoding a coded analog signal that suffers from an amplitude modulation to determine described output values, where the discrete output values include a first non-zero value and a null value, comprising: A first device for comparing a first component of the analog signal coded with a threshold value, and if the first component is greater than the threshold value then the first device for comparison sets a first discrete output value equal to the first non-zero value, and if the first component of the coded analog signal is smaller than the threshold value then the first device for comparing sets of discrete output values equal to one of a set of discrete values, where the set of discrete values includes a null value; and a first device for modifying the threshold value by adding a first error signal multiplied by a first reduction factor, if the first of the discrete output values is the null value, then the first device for modifying sets of the first signal of error is equal to 0, and if the first of the discrete output values is the first non-zero value, then the first device to modify sets of the first error signal equal to a difference between the first component of the coded analog signal and twice the threshold value. The device of claim 1, wherein the first set of discrete values includes a second non-zero value equal to the negative of the first non-zero value, and if the first component of the first analog signal is less than the negative to the threshold value, then the first device for comparing sets of the first of the discrete output values is equal to the second non-zero value, and if the first component of the coded analog signal is greater than the negative of the threshold value and smaller than the threshold value, then the first device for comparing sets of the first of the discrete output value is equal to the null value, and if the first of the discrete output values is equal to the second non-zero value, then the first device to modify sets of the first error signal is equal to a difference between the absolute value of the first component of the coded analog signal twice the threshold value. The device of claim 2 further comprising: a second device for comparing a second component of the coded analog signal with the threshold value, and if the second component is greater than the threshold value, then the second device for comparing sets of a second sets a second of the discrete output values equal to a first non-zero value, if the second component of the coded analog signal is less than the negative of the threshold value, then the second device for comparing sets causes the second of the discrete output values is equal to the second non-zero value, and if the second component of the coded analog signal is greater than the negative of the threshold value and smaller than the threshold value, then the second device for comparing sets causes the second of the discrete output values equal the null value; and a second device for modifying the threshold value by adding a second error signal multiplied by a second reduction factor, if the second of the discrete output values is the null value, then the second device for modifying sets causes the second signal of error is equal to 0, and if the second of the values of discrete outputs is equal to the first non-zero value, then the second device to modify sets of the second error signal is equal to the difference between the second component of the signal coded analog and twice the threshold value, and if the second of the discrete output values is the second non-zero value, then the second device to modify sets of the second error signal is equal to a difference between an absolute value of the second component of the coded analog signal and twice the threshold value. 4. The device that generate 244 and 245 sinusoids at exactly 24 MHz, therefore the baseband signals 250 and 251 have a frequency channel 0. The frequency and phase of the baseband signals 250 and 251, and consequently the frequency and phase errors of the channel synthesizer 212 or VCXO 248 they are measured by the continuous data demodulator 258 using conventional digital radio reception techniques, or the channel recovery technique described below. The frequency error information 260 can be fed back to the channel synthesizer 212 to correct its frequency and minimize the aforementioned error in this way by effecting a closed phase closed circuit. For a high precision channel 213 of the channel synthesizer 212, it is necessary that the signals 244 and 245 of the VCXO 248 are also accurate, because any error in the outputs 244 and 245 of the VCXO 248 can not be distinguished from the continuous data demodulator 258 from the errors of the remote channel synthesizer 212 frequency. The 24 MHz signals of 244 and 245 of the VCXO are synthesized from the recovered clock signal of 1200 Hz 264 generated by the continuous data remodulator 258. Since the copied clock signal generated in the base station transmitter 44 has a high precision, the signals 24 MHz 244 and 245 on the remote radio 46 also have high accuracy. Then the frequency error signal 260 generated by the continuous data demodulator 258 is an accurate representation of the channel frequency synthesizer error 212, and correcting this error causes the channel frequency synthesizer 212 to be accurate in frequency. The continuous data demodulator circuit 258 is shown in detail in FIG. 5. The signals 266 and 267 of the analog filters 254 are converted to digital in the two A / D converters 284 and 285, and the resulting digital signals 280 and 281 are multiplied by two multipliers 288 and 289 for producing amplified signals 290 and 291. Signals 290 and 291 are digitally filtered in digital filters 292 and 293 to reject out-band interference. The filtered signals 296 and 297 are transmitted A and B, respectively, of a rotator 300. The rotator 300 determines the amount of spurious mixtures of the phase and quadrature components in the signals 296 and 297 and reverses this mixing. The outputs A 'and B' of the rotator 300 consist of the mixtures: A '= A eos 0 + B without 0, and B' = -A without 0 + B eos 0, where 0 is the angle of rotation. A coast phase detector 306 determines the amount of the quadrature signal 302 (or equivalently the signal in phase in the signal 303). The ramp estimator 310 generates a phase error signal 311 which controls the amount of rotation 0 performed by the rotator 300 so that the signals 302 and 303 are converted into the phase and quadrature components, respectively, of the transmission. The ramp estimator also generates the frequency error signal 260 which is directed to the channel synthesizer 212 (see Figure 4) to stabilize the channel frequency 213, but not necessarily to the accuracy of the phase closure. The rotator 300 achieves the effect of closing the phase locally within the continuous data demodulator 258 and allows the synthesizer control to relax to only achieve a frequency closure. The continuous data demodulator 258 uses an automatic gain control algorithm to maintain a constant signal level over 24 dB of signal level variations. The amplitude estimator 312 calculates the sum of the squares of the signals 302 and 303 of the rotator 300 to generate an estimate of amplitude 313. The magnitude of the estimate 313 is instructed to invert the gain controls of the multipliers 288 and 289, of this mode stabilizing the amplitude of the signals 290 and 291. A preliminary estimate of the clock phase of the signals 302 and 303 are achieved by matching the signal 313 in an approximate clock estimator 316. The output 318 of the estimator 316 can be shown as that which has a peak in the sampling times of data having the appropriate clock phase, and therefore can be used as a rough estimate of the clock signal 111. A more accurate estimation of the clock frequency and phase are achieved in the fine clock estimator 320 when processing the magnitude of signals 302 and 303 at the nominal zero crossing times estimated by the approximate clock estimator 316. This generates to an error signal 264 that can be used to fine tune the VCXO 248, thereby putting it accurately to 24 MHz. Since the calculation of the clock phase is independent of the channel phase and the frequency, synchronization can be achieved. clock before channel frequency synchronization is achieved. The decoding of the signals 302 and 303 is performed in the data recovery circuit 322 to produce the recovered data 276. The recovered data 276 is directed to the remote station processor 203 as shown in Figure 4. The recovered data 276 specify what information should be received at the remote station 46 of the location units, or transmit to the base station 44. An alternative embodiment of a radio tranceptor 544 in accordance with the present invention appears in Figure 8. The tranceptor 544 operates as described in the first preferred embodiment 54 of Figure 4, except that in this tranceptor 544 the channel error signal 260 is sent to the rotator 274 inserted in the transmission side of the tranceptor 544, instead of the channel synthesizer 212, to effect the phase corrections by adding phase shift, and frequency corrections by adding continuously increasing or decreasing phase shifts towards the transmitted signal instead of the channel 213. In particular, this tranceptor 544 differs from the tranceptor 54 of FIG. 4 in that the transmission rotator 274 is positioned between the digital filters 208 and the quadrature modulator 218. The data signals of the baseband 214in and 215in are input of the transmission rotator 274 provided by the filter s 208, and the outputs 214out and 215out of the transmission rotator 274 are directed to the quadrature modulator 218. The amount of rotation 0 produced by the transmission rotator 274 is controlled by the control signal 272 produced by the generator. transmission phase ramp 270 based on the error signal 260 provided by the continuous data demodulator 258 to produce translated signals of frequency 214out A "and 215out B 'consisting of the mixtures: A' = A eos 0 + B sin 0, and B '= -A without 0 + B eos 0, where A and B are the baseband inputs 214in and 215in towards the transmission rotator 274. By producing a frequency translation of the baseband signals 214in and 215in , the transmission signal 225 has a channel with an accurate channel frequency, although there is no phase closure or frequency closure in the circuit. Another alternative embodiment of a radio tranceptor 545 according to the present invention appears in Figure 9. The tranceptor 545 operates as described in the first preferred embodiment 54 of Figure 4, except that this tranceptor 545 combines a relatively close frequency closure of the channel synthesizer 212 using an error signal 260, with a rotation of baseband data signals 214in and 215in using a rotator 280 controlled by the control signal 311 of the ramp estimator 310 in the continuous data demodulator 258. (The output of the signal 311 of the continuous data demodulator 258 is not shown in Figure 5). In particular, this tranceptor 545 differs from the tranceptor 54 of Figure 4 in that the transmission rotator 280 is positioned between the digital filters 208 and the quadrature modulator 218. The baseband data signals 214in and 215in enter the transmission rotator. 280 and are provided by the digital filters 208, and the translated frequency signals 214out and 215out are output from the transmit rotator 280 and directed towards the quadrature modulator. 218. The amount of rotation 0 produced by the transmit rotator 280 is controlled by a control signal 311 produced by the ramp generated from the receiving side 310. As before, the translated frequency signals 214out A 'and 215out B' exit the rotator Transmission 280 and consist of the mixtures: A '= A cos0 + B sin 0, and B' = -A sin0 + B cos 0, where A and B are the baseband data signals 214in and 215in and which are input for the rotator of transmission. In the tranceptor 545 of FIG. 9, the frequency of the signal 213 produced by the channel 212 is corrected each time the frequency error exceeds a certain threshold amount of frequency, while the control signal 311 continuously controls the rotator of the signal. Transmission 280, and you only need to correct frequency errors up to the amount of frequency threshold. In this case, the closed feedback loop includes the conveyor synthesizer 212 and the continuous data demodulator 258 has a very low bandwidth, and therefore is easy and inexpensive for instruments. An advantage of this tranceptor 545 over the tranceptor 544 of FIG. 8 is that a single phase ramp generator is needed since the ramp estimator 310 on the circuit receiving side also controls the transmitted signals 214out and 215out. In another alternative mode, the tranceptor only operates in a half-duplex mode (ie, the transmission at the reception can not include simultaneously) and the transmit and receive sides of the circuit share the same rotator control signal 311 and the rotator 280. During the reception of the alternative continuous data demodulator 558 shown in Fig. 10 it functions as the continuous data demodulator 258 described above, except that the rotator is now marked by the reference number 280. During transmission, the system operates as described in relation to the tranceptor 545 of Figure 9. The continuous data demodulator 558 of the alternative mode is detailed in Figure 10. During reception, the switches 510, 515, 517, 525 and 527 are in the positions Rx, and circuit 558 operates as described above in relation to FIG. 5, since the output of the coast phase detector 306 is a., connected to the input of the ramp estimator 310, and the inputs A and B of the receiving rotator 280 are connected to the lines 296 and 297 of the digital filters 292 and 293, and the outputs A 'and B1 of the rotator of reception 280 are connected to lines 302 and 303 to data recovery circuit 322, Costas phase detector 306, amplitude estimator 312 and fine clock estimator 320. During transmission, switches 510, 515, 517, 525 and 527 are in the Tx positions, and the circuit 558 operates as described above in relation to FIG. 9, since the inputs A and B of the receiving rotator 280 are connected to the data transmission signals of the baseband 214in and 215in of the digital transmission filters 208, and outputs A1 and B * of the reception rotator 280 are connected to the lines 214out and 215out with the quadrature modulator 218. However, in the transit mode, the 510 switch that controls the input to the ramp estimator 310 is open, so that the ramp estimator maintains the values of the control signal 311 and the channel error signal of 260 used during the previous reception. As in the case of Figure 9, the closed feedback path including the channel synthesizer 212 and the continuous data demodulator 258 has a very low bandwidth, and therefore its instrumentation is easy and inexpensive. With this embodiment of the continuous data demodulator 558, the total hardware costs are minimized, since the rotator 280 and the ramp estimator 310 are used on the transmission and reception sides of the tranceptor. In summary, a device for a bidirectional radio system of synchronized frequencies was described. It will be seen that the modality presented in this, consistent with the objectives of the invention for a synchronized frequency bidirectional radio system, provide a high-performance, low-cost radio system using frequency domain multiplexing, time domain multiplexing, frequency synchronization and spatial reuse of frequencies. The frequency synchronization of the remote stations 46 is provided by extracting the precise clock rate 111 and the channel frequency 113 from the base station 44, and using this information in the phase-closing circuits. In an alternative embodiment an increment scrambler continually updates the decoding threshold based on a comparison of the signal amplitude and the updated value of the decoding threshold. In another alternative embodiment, the channel synthesizer is not part of a closed path of the phase closure, but the transmitted signal rotated by a phase ramp proportional to a frequency error to provide a precise channel frequency. In yet another alternative embodiment, only one phase closure is instrumented, and again the transmitted signal is rotated by a phase ramp proportional to a frequency error to provide a precise channel frequency. In this alternative embodiment, separate rotators can be used on the transmission and reception sides of the circuit, or a single rotator can be placed between the transmission and reception sides of the circuit for half-duplex operation. While the above description contains many specificities, it should not be construed as limitations on the scope of the invention, but rather as examples of the preferred embodiments. Many variations are possible. For example: the incremental demodulation adapter threshold unit may be adapted to demodulate a coded two-state signal where the high state has a signal value above the threshold, and the low state has a signal value below the threshold; the increment demodulation adapter threshold unit could be adapted to demodulate a single coded three state signal simply by using the upper half of the circuit of Figure 7; the increment demodulation adaptation threshold unit could be adapted to demodulate a signal with more than three states by making all thresholds multiples of the fundamental threshold value, or by independently updating multiple thresholds; there could be separate thresholds for the in-phase and quadrature components; the reduction factors for the quadrature components could be different; the multiplication factor R in the incremental demodulation adapter threshold unit could have a different value 1/32; communications between the master system 40 and the base stations 46 could be assigned more than four channels, or less, for each bandwidth of 12.5 KHz; the tranceptor circuits of the base station 44 and the remote station 46 could use other coding, filtering and modulation techniques; and the instruction formats could take many other forms. The modulation of channels 113 and 213 are not necessarily 9QPR, quadrature modulation or digital modulation, but could be of any type of modulation. The present invention was described in terms of a preferred embodiment. However, the invention is not limited to the modality shown and described. Rather, the scope of the invention is defined by the appended claims. CLAIMS 1. A device for decoding a coded analog signal that suffers from an amplitude modulation to determine described output values, where the discrete output values include a first non-zero value and a null value, comprising: A first device for comparing a first component of the analog signal coded with a threshold value, and if the first component is greater than the threshold value then the first device for comparison sets a first discrete output value equal to the first non-zero value, and if the first component of the coded analog signal is smaller than the threshold value then the first device for comparing sets of discrete output values equal to one of a set of discrete values, where the set of discrete values includes a null value; and a first device for modifying the threshold value by adding a first error signal multiplied by a first reduction factor, if the first of the discrete output values is the null value, then the first device for modifying sets of the first signal of error is equal to 0, and if the first of the discrete output values is the first non-zero value, then the first device to modify sets of the first error signal equals a difference between the first component of the coded analog signal and twice the threshold value. The device of claim 1, wherein the first set of discrete values includes a second non-zero value equal to the negative of the first non-zero value, and if the first component gives the first analog signal is less than the negative to the threshold value, then the first device for comparing sets of the first of the discrete output values is equal to the second non-zero value, and if the first component of the coded analog signal is greater than the negative of the threshold value and smaller than the threshold value, then the first device for comparing sets of the first of the discrete output value is equal to the null value, and if the first of the discrete output values is equal to the second non-zero value, then the first device to modify sets of the first error signal is equal to a difference between the absolute value of the first component of the coded analog signal twice the threshold value. The device of claim 2 further comprising: a second device for comparing a second component of the coded analog signal with the threshold value, and if the second component is greater than the threshold value, then the second device for comparing sets of a second sets a second of the discrete output values equal to a first non-zero value, if the second component of the coded analog signal is less than the negative of the threshold value, then the second device for comparing sets causes the second of the discrete output values is equal to the second non-zero value, and if the second component of the coded analog signal is greater than the negative of the threshold value and smaller than the threshold value, then the second device for comparing sets causes the second of the discrete output values equal the null value; and a second device for modifying the threshold value by adding a second error signal multiplied by a second reduction factor, if the second of the discrete output values is the null value, then the second device for modifying sets causes the second signal of error is equal to 0, and if the second of the values of discrete outputs is equal to the first non-zero value, then the second device to modify sets of the second error signal is equal to the difference between the second component of the signal coded analog and twice the threshold value, and if the second of the discrete output values is the second non-zero value, then the second device to modify sets of the second error signal is equal to a difference between an absolute value of the second component of the coded analog signal and twice the threshold value. 4. The device of claim 3, where the first reduction factor is equal to the second reduction factor. The device of claim 1, further comprising a device for multiplying a non-multiplied signal to provide the coded analog signal by calculating an amplitude and a phase of a reference segment of the non-multiplied signal to generate an amplitude of multiplication and a multiplication phase, and multiply the amplitude of the phase of the signal not multiplied by the amplitude of multiplication and the phase of multiplication, respectively. A bidirectional radio communication system comprising at least one communication cell, where the cell has a base station and at least one remote station, where the remote station receives an instruction signal in a precise clock rate at a frequency Precise base channel from the base station, where the remote station transmits a response signal with a baseband response data signal with a remote clock rate to the base station, where the remote station is. : a first frequency synthesizer that generates a frequency of remote channels. A first frequency heterodyne, where the first heterodyne heterodinizes the remote channel frequency and the instruction signal to generate an intermediate frequency signal a second frequency synthesizer that generates a second intermediate frequency sinusoid, where the intermediate frequency sinusoid is stabilized during a first frequency stabilizing signal a second heterodyne of frequencies, where the second heterodyne heterodyns the intermediate frequency sinusoid and the intermediate frequency signal is generated to receive a baseband signal. A first recovery circuit, where the recovery circuit determines an error frequency to provide with the difference between the precise base channel frequency and the remote channel frequency; a second recovery circuit, wherein the second recovery circuit generates the first frequency stabilization signal and the remote clock rate from the clock rate of the base; a rotator for rotating the baseband response data signal by a rate proportional to the error frequency to provide a translated frequency signal; and a modulator for modulating the signal translated from frequencies to the channel frequency to provide the response signal. The bidirectional radio communication system of claim 6, wherein the first frequency synthesizer uses the error frequency from the first recovery circuit in a closed frequency control path. 8. A bidirectional radio communication system comprised of at least one communication cell, wherein the cell has a base station and at least one remote station, wherein the remote station operates in a half-duplex mode, where the station The remote receives an instruction signal with a precise clock rate at a precise channel frequency from the base station during reception, where the base station transmits a baseband response signal with a remote clock rate to the base station during a transmission, wherein the remote station is comprised of: a first frequency synthesizer that generates a remote channel frequency, and which uses a frequency error signal in a closed frequency control path; a first frequency heterodyne, where the first heterodyne heterodyns the remote channel frequency and the instruction signal to generate an intermediate frequency signal; a second frequency synthesizer that generates an intermediate frequency sinusoid, where the intermediate frequency sinusoid is stabilized by a signal by a first frequency stabilization signal; a second heterodyne of frequencies, wherein the second heterodyne heterodinizes the intermediate frequency sinusoid and the intermediate frequency signal to generate a received baseband signal; a first recovery circuit, wherein the first recovery circuit includes a rotator for translating frequency of an input signal into a rotator input to provide a translated rotator output signal translated into a rotator output, a phase detector to produce a phase detector output proportional to the phase of the phase detector input, a ramp estimator to provide a rotator control signal to the rotator and produce the frequency error signal, the frequency error signal is related to a difference between the precise base channel frequency and the remote channel frequency, a rotator input switch to direct the received baseband signal to the rotator input during reception, and to instruct the signal to response to the baseband for the entry of the rotator during transmission, a rotator output switch to give instructions to the output rotator to direct the output of the rotator to the phase detector input and the clock estimate input during reception, and direct the output of the rotator to a modulator to modulate the rotator output to the channel frequency to provide a response signal during transmission, a ramp estimator input switch to connect the phase detector output to the ramp estimator input during reception, and disconnect the ramp estimator input during transmission so that the signal Rotator control and frequency error signal are not modified and a clock estimator to determine an estimate of the clock rate of the base from the clock estimator input; and a second recovery circuit, wherein the second recovery circuit generates the first frequency stabilization signal and the remote clock rate from the estimation of the base clock rate.