MXPA96006433A - A method and apparatus for generating variable speed synchronization signals - Google Patents

Abstract

The present invention relates to a programmable synchronization system for selectively providing synchronization signals at different speeds, such as for incorporation into a video signal decompression system, including an oscillator (401) and a programmable counter (405). The programmable counter is conditioned to count pulses of the oscillator by alternating modules in predetermined sequences to generate the synchronization signals. The desired synchronization speed is effectively the average of the counter output that results from counting through the altern modules

Description

A METHOD AND APPARATUS FOR GENERATING IS ALARM OF VARIABLE SPEED SYNCHRONIZATION The present invention relates to the generation of synchronization signals having different frequencies, a particular example of which provides different frame synchronization rates for the visual display of different modes of video signal transported in compressed MPEG form. In this MPEG it refers to compression standards supported by the Motion Picture Experts Group of the International Standardization Organization or ISO. The invention will be described in the environment of an MPEG video signal receiver, but should not be considered limited to use with video signals or MPEG signal processing systems. MPEG standards for compressed video signal are extremely flexible in that video signals having different modes of visual display can be compressed and transmitted. For example, source signals with different frame rates can be compressed and it is expected that compatible receivers will be able to visually reproduce and display the respective signal at the appropriate frame rate. In particular, the Grand Alliance High Definition Television system currently undergoing examination by the FCC accommodates compressed video signals according to the MPEG that have frame rates of 29.97002997 ... Hz or 30.000000 Hz. The compressed signal includes a data field indicating the frame rate of the received signal, and the receivers operating in accordance with the Grand Alliance, which respond to this data field are reconfigured in an adaptive manner to visually display the received signal at the indicated frame rate. The compressed MPEG signal of the system level incorporates synchronization signals in the form of time stamps. These time stamps are related to a clock signal from the 27 MHz video signal compressor system. One of these time stamps, designated Presentation Time Stamp or PTS (presentation time stamp), is presented at the video level of the compressed signal, it is synchronized with the occurrence of frames of the signal being compressed and is determinant of the precise time in which a decompressed frame is going to be displayed by the respective receivers. A second time stamp, designated the System Clock Reference or SCR (reference of the system clock) is incorporated into the system level of the compressed signal. At the system level the compressed video signal is segmented into discrete packets. The system clock references are included in one of these packages, where the system clock references are indicators of the precise time in which the associated packet is formed / transmitted. The respective receivers use the clock references of the system to synchronize a system clock in the receiver with the system clock in the compression apparatus. The clock synchronization of the receiver system with the system clock of the compression apparatus minimizes the amount of memory required in the respective receivers to damp the speed of the received signal. The decompression apparatus nominally uses the receiver system clock to decode the compressed signal. Since the watch of the receiver system is synchronized with the system clock of the compression apparatus to which the presentation time stamps are referenced, the display of the decoded signals can also be synchronized via the watch of the receiving system. However there are drawbacks in using a signal clock reference in the transmission signal receivers. For example, transmitted data may be lost or corrupted frequently, and error concealment processes must be performed on the decompressed signal. These processes tend to interrupt the normal flow of the decoded data and possibly prevent the normal visual display of frames according to the associated display time stamps. As well, different deployment characteristics can be implemented, such as the frozen table, which interrupts the proper association of the presentation time stamps with the system clock. The present invention includes a programmable synchronization system for selectively providing synchronization signals at different speeds. In a particular embodiment the programmable synchronization system is incorporated into a video signal decompression system having a first synchronization system for developing a system clock signal and a second synchronization system for providing synchronization signals for the video display of the video signals. In a specific embodiment, a synchronization system for selectively providing synchronization signals at different speeds includes an oscillator and a programmable counter. The programmable counter is conditioned to count pulses alternately from the oscillator by means of a first and a second divider, to generate the synchronization signals. The desired synchronization speed is effectively the average of the counter output that results from counting by the alternating divisors.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram of a video signal receiver compatible with MPEG, embodying the invention. Figure 2 is a block diagram of a clock generator of the receiver system for the receiver of Figure 1. Figure 3 is a block diagram of a programmable generator for providing synchronization signals for visual display of video signals , which incorporates the invention. Figures 4, 7 and 8 are block diagrams of alternative programmable synchronization generators for providing synchronization signals for the video display of the video signals, which the invention incorporates. Figures 5 and 6 are block diagrams of alternative programmable dividers that can be implemented in the apparatus of Figure 4. Figure 9 is a flow chart illustrating the programming of the programmable counter for generating vertical synchronization signals in the apparatus of Figure 8. With reference to Figure 1, the compressed video signal transmitted, for example a signal compatible with MPEG is detected on an antenna 10 and applied to a tuner-demodulator 11. The tuner-demodulator 11 may include equalization circuits and an analog-to-digital converter. The tuner-demodulator, under the control of a system controller 16, tunes to a desired channel, detects and demodulates a desired frequency carrier and provides a digital baseband signal to a forward error correction circuit 12. circuit 12 may include Reed-Solomon error correction and a lattice decoding circuit to correct errors induced in the transmission in the received signal. The corrected error signal is applied to a reverse transport processor 13. The reverse transport processor performs several functions including separating the desired compressed signal packets from a packet stream that is time-biased, extracting payloads from selected packets, cryptically decoding payloads of signals encoded in cryptic codes, sorting selected signals in buffer memory and generating the clock of the receiving system. A detailed description of the exemplary reverse transport processor circuit can be found in U.S. Patent No. 5,459,789. The separated compressed audio signal is applied to an audio signal decompressor 15, the separated compressed video signal is applied to a video decompressor 14, and the separate data signal, such as a program guide, is applied to the controller of system 16, which may include a microprocessor. The decompressor of the video signal includes the circuit that cooperates with the decompression memory 17 to decompress the received video signal. The decompressed video signal is loaded into a portion of the memory 17 where it is available for visual display at the appropriate frame rate. In this example the decompressor 14 also includes a visual display clock generator in accordance with the present invention. The visual display clock generator provides pixel speed signals, horizontal line speed signals and field / frame speed signals. The pixel speed signals are used to at least read the decompressed signal from the visual display memory, and can be used in the decompression process itself. The line and field / frame speed signals are applied to the deflection circuit 20 which generates signals for application to the visual display apparatus (not shown). The decompressed video signal of the memory 17 is applied to a signal translator 18 which includes circuits for reformatting the signal for visual display. For example, the translator may contain an apparatus to convert the video signal in 4: 2: 0 format to the 4: 2: 2 format, and convert the non-interlaced signal into an interlaced signal, and so on. The translated signal provided from element 18 is in Y, R-Y and B-Y format. These signals are applied to a color matrix 19 that generates digital signals R, G and B, and may include contrast, brightness and color correction controls. The digital signals R, G and B are applied to the analog digital circuit 21 which converts the respective R, G and B signals into the analog form for application in the visual display controller circuit (not shown). Figure 2 illustrates a clock generator of the exemplary receiver system 25. In this embodiment, data from the forward error correction circuit 12 is coupled to a reverse transport processor 32, and a reference clock detector of the system clock 31. The reverse transport processor 32 separates the header data from the transport packet from the payloads of the respective transport packet. The reverse transport processor 32, which responds to the transport header data, applies payloads of video signals (designated here as service data 1) for, for example, the video decompression apparatus 14, and auxiliary data. . { designated as service data 2) for the appropriate auxiliary data processing elements such as the system controller 16, for example. References of the system clock that are typically included in the auxiliary data are routed to and stored in a memory element, 34. The clock reference packet detector of the system 31, which may be a coupled filter arranged to recognize flags appropriate in the headers of the transport packet, produces a control impulse in the occurrence of transport packets containing a system clock reference. The control pulse is applied to a holding circuit 35, which, responding to the control pulse, stores the value of the account currently displayed on the local counter 36. The local counter 36 is arranged to count the pulses provided, for example , by the voltage controlled oscillator 37. The counter 36 is arranged to count by module the same number as a counter counter in the signal encoding apparatus (not shown) which produces the system clock reference contained in the transport. The voltage controlled oscillator 37 produces the clock signal from the receiver system, which is typically at 27 MHz. This oscillator is controlled by a filtered low pass error signal provided by a clock controller 39. The error signal may be generated in the following way. Let us denote the arrival of the system clock reference at time n as SCRn and designate the account value stored at the same time in latch circuit 35 as Ln. The clock controller reads the successive values of the system clock references and the holding circuits and forms an error signal E proportional to the differences E == > | SCRn - SCRj! ^ | - i Ln - Ln-1 | The error signal E, is used to condition the voltage controlled oscillator 37 to exhibit a frequency that tends to cancel the error signal E. The error signal produced by the clock controller 39 may be in the form of a modulated signal of pulse width, and the low pass filter 38 can be made in analog components. In an alternative arrangement, the counter 36 may be initialized, at the beginning, to display an account value equal to the first clock reference of the detected system. After this, an error signal proportional to the differences (SCRn - Ln) can be generated. However, this arrangement requires a significantly more complicated counter circuit, as well as a routing circuit to apply the first clock reference of the system to the counter. For either arrangement, the free running frequency of the voltage controlled oscillator must be quite close to the system clock frequency in the encoder / compressor. In Figure 2, a second clock generator 26 is included. The clock generator 26 cooperates with a voltage controlled crystal oscillator (VCXO), as shown in the apparatus of Figure 4, to generate a display clock of pixels. The operation of the clock generator 26 is similar to the operation of the clock generator 25, and therefore its operation will not be described in detail. Referring to Figure 3 which illustrates a first example of the visual display clock generator incorporated in the video decompressor 14. Although the display clock generator is separate from the system clock, it is convenient to synchronize with the clock. system clock. This is done in Figure 3 by locking the clock phase of the visual display with the clock of the 27 MHz receiver system. In Figure 3 the different synchronization speeds (frames) are produced by dividing the clock of the system that is locked in phase with the clock generator of the visual display by different factors. This division is carried out by means of a programmable divider 301, which under the control of the decompressor controller divides the system clock between a value N. The value N is selected depending on the desired frame rate. For example, if the desired visual display frame rate is 30.000000 Hz, the selected value of N is 1000. Alternatively, if the desired visual display frame rate is 29.97002997 ... Hz, the selected N value is 1001. The divided system clock signal is applied to a first input terminal of a phase comparator 302 included in a locked phase cycle consisting of a cycle filter 303, a voltage controlled oscillator 304 and a circuit that divides between M 305. The phase lock cycle is of conventional design and those skilled in the signal processing art will understand its operation. The output frequency of the voltage controlled oscillator (VCO) 304 and the value of the factor M in the circuit that divides between M, 305, will be determined by the desired clock frequency of pixels. For example, if the clock frequency of pixels is chosen at 74.25 MHz, the M value will be 2750. To generate the appropriate frame synchronization signal, the clock frequency of pixels is applied to another divider in circuit 306. Assuming 2200 pixels per line, the 74.25 MHz clock is divided by 2200 to generate a line speed signal of 33,750 KHz. Finally assuming 1125 lines per frame, the line speed signal is applied to the second count down circuit, in circuit 306, to divide the line speed signal between 1125 to generate the frame rate signal. The circuit of Figure 3 generates acceptable signals of pixel clock and selectable frame rate.

However, the combination of the phase detector 302 and the cycle filter 303 undesirably operates with error signals of relatively low frequency in relation to the pixel clock frequency. A preferred embodiment, which overcomes this disadvantage is illustrated in Figure 4. The system of Figure 4 generates a pixel clock signal that is not subject to significant voltage controlled oscillator error signals. In Figure 4, the pixel clock is generated by a VCXO 401 voltage controlled crystal oscillator. The output frequency of the crystal controlled voltage oscillator (illustratively shown as 81 MHz) can be 81 MHz, 74.25 MHz, 27 MHz, etc. and is a decision of the application of the system. Because the oscillator is based on crystal, the frequency of the pixel clock is very stable and the frequency deviation is quite small. A system requirement of a Grand Alliance receiver, for example, is that the pixel clock frequency does not vary by more than 1 part in 1000 regardless of whether the frame rate is 29.97002997 ... Hz or 30.00 Hz. This stability is easily satisfied by a voltage controlled crystal oscillator, such as the voltage controlled crystal oscillator 401. In the arrangement of Figure 4, the clocks of the visual display are indirectly locked in phase with the system clock. That is, the output of the voltage controlled crystal oscillator 401 is locked in phase with the clock of the encoder or compressor system via the clock references of the system in a manner similar to the clock apparatus of the receiving system for phase locked for the clock of the compressor system. This is carried out in the cycle including the circuit dividing between three, 403, and the clock reference processor of system 26 (of Figure 2). The pixel speed clock output by the voltage controlled crystal oscillator 401 is coupled to a dividing circuit, 404. Assuming 1920 active pixels per line or 2400 total pixels per line, the divider 404 is arranged to divide the clock of pixel speed between 1200 to provide a line speed signal twice. This signal is applied to a circuit that divides between two to generate a horizontal synchronization signal. The line speed signal twice is also coupled to a programmable divider 405. Assuming 1125 lines per frame, the programmable divider 405 is set to divide the speed signal twice between, for example, 1125, to produce a speed signal Field or vertical 60 Hz. The output of the divider 405 is coupled to a circuit that divides between two, 407, to generate the frame rate synchronization signal. It is not possible to divide the line speed signal twice (or the line speed signal) by a whole number to generate a frame rate signal of 29.97002997 ... Hz, corresponding to the vertical signal of 59.94005994 Hz. In order to generate the vertical velocity signal of 59.94005994 ... Hz, the division factor applied to the programmable divider 405 is periodically changed between 1125 and 1127 lines per frame. If the divisor 1125 is represented by "0" and the divisor 1127 is represented by "1", and the divisors applied to the programmable divider 405 are presented in a repetition sequence of 16 frames according to the. pattern 0000000111111111, the average field speed (vertical speed) will be exactly 59.95005994 ... Hz. The repetition sequence of 16 frames can be rearranged according to the pattern 1010101101010101, that is, 1010101101010101.1010101101010101.1010101101010101 (where "." is included only to indicate demarcation between sequences) to produce an effective instantaneous vertical velocity of 59.95005994 ... Hz. When this alternating divider pattern is applied to the counter 405, the circuit dividing between two 407 provides a frame rate synchronization signal of 29.97002997 ... Hz. If interlaced signals are going to be produced, vertical or field speed signals are needed, these signals are generated as described above. Note, in the above description, that the divisors applied to the divider 405 tilt at a frame rate, not the field speed. The dividers tilt at frame rate to ensure that the extra lines presented in the squares produced by the 1127 division are divided between odd and even fields. If the respective decompressor is arranged to produce only non-interlaced signal, the divider 404 can be conditioned to count down by 2400 instead of 1200. In this case, both circuits dividing between two, 406 and 407 are unnecessary. The programmable divider 405 directly will provide the frame rate signals. Figure 5 illustrates exemplary programmable divider circuits which can be swung between several dividers. A binary counter 501 is synchronized by the horizontal speed signal twice and restored by the frame rate signal. (For simplicity, it is assumed that all circuits in Figure 5 are activated by edge). The parallel output signals provided by the binary counter are applied to a plurality of decoders 502-504. The respective decoders provide an output pulse when the counter 501 reaches an account value corresponding to a respective divider associated with the respective decoder. For example, the decoder 1 may correspond to a division between 1125. In this case, the decoder 1 will produce an impulse in the event that the counter 501 produces an account value of 1125, which indicates the occurrence of 1125 pulses of the signal of watch 2H. The outputs of the respective decoders 502-504 are applied to the respective input terminals of a multiplexer 505. The output of the multiplexer 505 is the signal of the vertical speed. The multiplexer 505 is conditioned to couple different decoders to its output according to a dividers tilting pattern. The tilt pattern is selected by the decompressor controller (or system controller) by controlling an additional multiplexer 507. A plurality of tilt patterns are loaded into a plurality of shift registers 508-510, each of which contains a pattern exclusive. The tilt patterns in the respective shift registers are a sequence of control signals for controlling the multiplexer 505. These control signals are shifted out of the shift register selected by the output frame rate signal and are applied to the respective ones Multiplexer 507 input terminals. These patterns are recirculated into the respective registers via a feedback connection to produce repetitive tilt patterns. The multiplexer 507 selects a shift register according to the desired frame rate (tilt pattern). A tilt pattern may provide a multiplexer control signal 505 for continuously coupling a decoder to its output, or for sequentially coupling (at the frame rate) two or more of the decoder output connections to the output of the multiplexer 505. For the system described with respect to Figure 4, the apparatus of Figure 5 may have the plurality of decoders reduced to two, one representing the divisor 1125 and one representing the divisor 1127. Furthermore, only a single tilt pattern register is needed. Programmable counters of the shape illustrated in Figure 5 become heavy if a wide variety of dividers and a wide variety of tilting patterns are desired. Figure 6 illustrates another form of programmable counter which has greater versatility. In Figure 6, a programmable down counter 606 is programmed by values corresponding to respective splitters, via a multiplexer 604. The multiplexer 604 is tilted at frame rate by a tilting pattern loaded in a tilt register 605. The respective ones Programming values are contained in the respective latch circuits 601-603 having their respective output connections coupled to the multiplexer 604. The desired programming values and tilt patterns are loaded into latch circuits 601-603 and register 605 either through the system or the decompression controller. The decompression controller, which responds to the compressed video signal, will detect the frame rate of the current video signal. The system, which responds to the detected frame rate, will section the appropriate tilt pattern and dividers stored in the system memory (not shown) and apply them to the appropriate retention circuits 601-603 and register 605. The record then it will be energized to operate the multiplexer 604 to condition the counter 606 to count according to the desired alternating splitter sequence. Figure 7 is a programmable timing signal generator which is a hybrid of the circuits of Figure 3 and Figure 4. This circuit includes a voltage-controlled crystal oscillator that is synchronized directly with the clock of the receiving system. MHz, instead of indirectly as in the circuit of Figure 4. The operation of the rest of the modality of Figure 7 is similar to the operation of elements designated with equal numbers in the circuit of Figure 4. The concept of alternating values of counts or divisors can be extended to provide other frame rates not producible by divisions between integers. However, to generate interlaced frame synchronization signals of video signals the dividers will preferably be odd numbers due to the odd number of lines per interlaced frame. Instead of tilting between 1125 and 1127, tilting can be used between the dividers 1121 and 1131. Any frame rate between 30.107 Hz and 29.84 Hz can be supported by proper tilting between dividers. The tilting between a large number of divisors on a frame sequence will generate a large number of frame rates. Different sequences of alternative dividers can be used to produce different frame rates. In addition, a controller such as a microprocessor can be programmed to adaptively apply different divisors, not repetition sequences. For example, consider that you want to generate frame synchronization signals that track a non-standard source, this source provides a frame synchronization signal. This system is illustrated in Figure 8. In Figure 8, a pixel clock is generated by an oscillator 800, which may be a free-running crystal oscillator or a controlled oscillator in a locked cycle or frequency as illustrated in FIG. other modalities The pixel clock signal is applied to a first programmable counter 804. The counter 804, in this case, is programmable so that a system (such as the system of Figure 1) can adopt a variety of pixel formats per line. The counter 804 is conditioned by the processor 816, which may be a microprocessor system controller, to divide the pixel clock signal between the appropriate factor to provide the desired horizontal velocity or the horizontal velocity signals twice (2H). That is, in the initialization of the system the processor 816 applies a value corresponding to the divider to the holding circuit 802, whose value is then loaded into the counter 804 which responds to a disturbed pulse Jp also provided by the processor 816. The counter 804 provides an output pulse in the occurrence of a number of pixel clock pulses equal to half the pixel periods of a total horizontal line for the 2H signal, (or equal to the pixel periods of a total horizontal line for the 1H signal if so programmed). The counter 804 is reset by each respective output pulse by this, and thus effectively counts per module, where W is set by the value set in the holding circuit 802. The signal 2H is divided down between 2 in the divider 806 to provide the horizontal synchronization signal. It is also applied as a clock to a second programmable counter 810. Counter 810 is conditioned by set values in a latch circuit 808 to divide the signal 2H to provide a vertical speed signal. The vertical speed signal is divided by 2 in circuit 812 to generate a frame synchronization signal. The frame synchronization signal is applied to the input control terminal Jp of the counter 810 to apply a value corresponding to the desired divisor to the JAM INPUT gate of the counter 810, each frame period. The value corresponding to the desired divisor can be constant or can change. The frame synchronization signal is applied to an input of a comparator 814, shown in this case as a phase detector. A reference frame rate signal REF SYNC is applied to a second input of the comparator. An output of the comparator is applied to the processor 816. The processor, which responds to the values provided by the comparator, generates values corresponding to the divisor or the divisors required, and applies the same to the holding circuit 808. Note that new dividers are applied to the 810 counter only after a full check account. That is, the counter 810 is not interrupted during a frame period to update a newly calculated divider value. It should be noted that since the update of the value corresponding to the divisor is not allowed during periods of respective frames, all but the slowest processors will have enough time, during periods of respective frames, to generate and apply the necessary sequence of divider values to the circuit. of retention 808. An exemplary algorithm for generating a sequence of divisor values (or values corresponding to divisor values) is illustrated by the flow chart of Figure 9. This algorithm applies one of six different values N1-N6, corresponding to six different dividers, to the holding circuit 808 of each frame period. The higher / lower the frame rate from the desired frame rate, the applied value will be greater / less, so as to make faster attack times. Assuming an 81 MHz pixel clock and approximately 1125 lines per frame, the exemplary values N1-N6 can be Nl = 1121; N2 = 1123; N3 = 1125; N4 = 1127; N5 = 1129; N6 = 1131. This algorithm assumes a similar system - to that of Figure 8 in which lps. Phase difference values are applied from a phase detector 814 to the controller 816. In the process the current value of the phase difference, F, is sampled. { 900.}. and it is tested. { 901.}. . If F is less than a first threshold value TH1 (indicating slight deviation of REF SYNC), it is tested. { 902.}. the polarity. If the polarity is positive, a value corresponding to the divisor N3 is accessed. { 904.}. from the memory of the processor and is applied to the holding circuit 808, or a value corresponding to the divider N4 is applied. { 903.}. to the holding circuit 808. Then the system returns to the step. { 900.}. to wait for the next phase difference signal. Yes in step. { 901.}. F is greater than the first threshold value, it is further tested. { 906.}. against a second higher threshold value TH2. If F is less than the second threshold value TH2 (indicating slightly greater deflection of REF SYNC), the polarity is tested. { 906.}. . If the polarity is positive, a value corresponding to the divisor N2 is accessed. { 908.}. from the processor memory and is applied to the holding circuit 808, or a value corresponding to the divider N5 is applied. { 907.}. to the holding circuit 808. Then the system returns to the step. { 900.}. to wait for the next phase difference signal. Yes in step. { 905.}. F is greater than the second threshold value TH2, (indicating even greater deflection of REF SYNC), the polarity is tested. { 906.}. . If the polarity is positive, a value corresponding to the divisor NI is accessed. { 911.}. from the processor memory and is applied to the holding circuit 808, or a value corresponding to the divider N5 is applied. { 910.}. to the holding circuit 808. Then the system returns to the step. { 900.}. to wait for the next phase difference signal. Variations on this algorithm can easily be deduced. For example, the phase difference signal can be filtered or integrated before testing against the different threshold values. In addition, restrictions can be placed on the sequence of values applied to the holding circuit. For example, the application of larger values N1 (N6) may be restricted to not occuring twice in successive frames. As another alternative, as soon as the system is substantially synchronized, some of the values N1-N3 can be forced to alternate with some of the values N4-N5, etcetera. Another variation may include the use of odd and even splitters. The embodiment of Figure 8 was described in the environment of the video signal processing system, however, those skilled in the art of circuits will appreciate that it can be implemented in a wide variety of systems that the generation of synchronization signals is required phase or frequency tracking.

Claims (14)

1. A circuit for generating synchronization signals, to selectively provide synchronization signals having different frequencies, characterized by: a source (26, 401) of a clock signal; a splitter (404, 405), coupled with the source, for dividing, the clock signals to generate the synchronization signals; and a circuit (405) for conditioning the splitter to divide the clock signal by a sequence of alternative dividers.

2. The synchronization signal generator circuit described in claim 1, characterized in that the circuit for conditioning includes a circuit for conditioning the divider to divide the clock signal between a constant divider to generate a synchronization signal having a first frequency , and for conditioning the splitter to divide the clock signal between a sequence of alternating divisors to generate a synchronization signal having a second frequency different from the first frequency.

3. The synchronization signal generator circuit described in claim 2, characterized in that the sequence of alternating divisors includes the constant divider.

4. The synchronization signal generating circuit described in claim 1, characterized in that the source comprises: a controlled oscillator, having a control input port and an output port in which a primary clock signal is available; and a divider circuit coupled with the output port, for dividing the primary clock signal by a constant factor to provide the clock signal. The synchronization signal generating circuit described in claim 4, characterized in that the source further comprises: a clock generator of the system for providing a system clock signal; a phase detector having a first and a second input port coupled with the output port of the controlled oscillator, and the system clock generator respectively and having an output coupled with the control input of the controlled oscillator. 6. The synchronization signal generating circuit described in claim 5 characterized in that the system clock generator comprises: another oscillator controlled to provide the system clock signal, - a module counter for counting pulses of the clock signal of system; a storage element for storing account values provided by the module counter in previously determined cases to generate local clock references; a source of transmitted data packets, some of which include system clock references (SCR); circuits for extracting the clock references from the system, from the data packets; control circuits, which respond to the clock references of the system and to the local clock references to provide a control signal to a control input port of the other controlled oscillator to adjust the frequency of the same. The synchronization signal generating circuit described in claim 4, characterized in that the source further comprises: a source of transmitted data packets, some of which include system clock references (SCR); circuits for extracting the clock references from the system, from the data packets; a module counter for counting pulses of the primary clock signal or a submultiple thereof, - a storage element for storing account values provided by the module counter in previously determined cases for generating local clock references; control circuits, which respond to the clock references of the system and to the local clock references to generate a control signal for the application to the control input port of the controlled oscillator. 8. The timing signal generating circuit described in claim 7, characterized in that the circuit for extracting the system clock references from the data packets includes a reverse transport processor for processing compressed video signal transport packets, the reverse transport processor includes circuits for generating a system clock signal different from the primary clock signal. The synchronization signal generating circuit described in claim 8, characterized in that the circuit for conditioning the splitter includes a decompressor compatible with the MPEG that responds to a signal compatible with the MPEG to determine the divisors by which the splitter is going to condition to divide. The synchronization signal generating circuit described in claim 9, characterized in that the decompressor compatible with the MPEG is coupled to the reverse transport processor and the system clock energizes, at least in part, the reverse transport processor, and the primary clock signal energizes, at least in part, the decompressor compatible with the MPEG. The synchronizing signal generating circuit described in claim 4, characterized in that the controlled oscillator provides a primary clock signal of 81 MHz, the splitter circuit divides the primary clock signal between 1200, and the circuit for conditioning the splitter for dividing the clock signal conditions the splitter to alternately divide between 1000 and 1001. 12. A compressed video signal processing apparatus characterized by: a source (11) of compressed video signal; a reverse transport processor (13) including a system clock generator for providing a synchronized system clock with time stamps included in the compressed video signal, the system clock coupled to energize, at least in part, said reverse transport processor; a decompression apparatus (14), coupled to the reverse transport processor, and including a pixel clock generator separate from the clock generator of the system, and coupled to energize, at least in part, the decompression apparatus; and signal synchronization circuits (14, 16, 20), coupled to the pixel clock generator and responsive to the decompression apparatus, to selectively generate synchronization signals to control an uncompressed video signal display speed between a plurality of deployment speeds. 13. The apparatus described in claim 12 further characterized by circuits for locking the phase of the pixel clock signal with the clock signal of the system. The apparatus described in claim 13, characterized in that the circuit for locking the phase of the pixel clock signal with the clock signal of the system comprises: a controlled oscillator for providing the pixel clock signal; a source of transmitted data packets, some of which include system clock references (SCR); circuits for extracting the system clock references from the data packets; a module counter for counting pulses of the pixel clock signal or a submultiple thereof, - a storage element for storing account values provided by the module counter in previously determined cases for generating local clock references; control circuits, which respond to the system clock references and local clock references to generate a control signal to control the controlled oscillator. another oscillator controlled to provide the system clock signal, - another module counter for counting pulses of the system clock signal or a submultiple thereof; a storage element for storing account values provided by the other module counter in previously determined cases to generate other local clock references, and control circuits, which respond to system clock references and other local clock references to generate a control signal to control the other controlled oscillator.