MXPA96006430A - Self-calibrated digital to analogue converter for a deployment of vi - Google Patents

Abstract

Each of the digital-to-analog (D / A) converters of current summation type N (23) of a liquid crystal display unit generates an analog signal (OUTPUT) that provides pixel video information. In an error sampling interval of the digital-to-analog converter, the digital-to-analog converter output signal developed when the data to be converted is full scale, is compared in a comparator (131), with a voltage of reference (VREF). An error signal (ERROR) is sampled and used to vary a control voltage (VCP2) developed in a capacitor. The control voltage controls the current sources (120) of digital to analog converter in a mirror manner. of current. The reference voltage is coupled in common with each of the comparators of digital-to-analog converters. In this way, the coupling between digital-to-analog converters and the accuracy of each u is improved

Description

AUTO-CALIBRATED DIGITAL TO ANALOG CONVERTER FOR A VIDEO DEPLOYMENT This invention relates generally to digital-to-analog converters used to apply brightness signals to the pixels of a visual display device, and particularly to a liquid crystal display (LCD). Visual display devices, such as liquid crystal displays, are composed of a matrix of a set of pixels configured horizontally in rows and vertically in columns. The video information that is to be displayed is applied as brightness signals (gray scale) to the data lines that are individually associated with each column of pixels. The rows of pixels are scanned in sequence, and the capacitances of the pixels within the activated row are loaded to the different levels of brightness according to the levels of the brightness signals applied to the individual columns. U.S. Patent No. 5,170,155, in the name of Plus et al. (Plus et al.), Entitled "System for Applying Brightness Signals To A Display Device And Comparator Therefore," describes an example of line drivers or data columns. of a set of a liquid crystal display. In the configuration of Plus and collaborators, the video information is stored in a digital format in a memory that has output lines. Each group of output lines applies the stored digital information to a corresponding digital to analog (D / A) converter. An output signal of a given digital-to-analog converter is coupled with a corresponding data line driver, which drives a corresponding data line of the liquid crystal display assembly. U.S. Patent Number 4,827,260, entitled "DIGITAL-TO ANALOG CONVERTER" in the name of Sugawa et al., Discloses a digital-to-analog converter for the processing of video signal referred to as a digital to analog converter. type of current segment or current sum. In an example of this digital-to-analog converter for a n-bit data word, the 2n-l identical current sources are controlled by 2n-l switches. The switches are selectively operated according to the states of the bits of the data word. The currents of the current sources associated with the conductive switches are combined in a summation resistor to produce a summation current. The value of the summation current is increased by the value of the current of a current source when the value of the data word is increased by one. An analog output voltage is developed that is proportional to the summation current in the resistor. A relatively large number of, for example, digital-to-analog current-type converters, for example 40, may be used to simultaneously apply the video information to the corresponding data line drivers. Conveniently, this parallel operation of the digital-to-analog converters provides a shorter cycle time to update the pixel information associated with a given row. A digital-to-analog converter for a visual display of a liquid crystal display may require a precision of, for example, more than 0.25 percent. However, it may be required that the output voltages of the digital-to-analog converters for a given data word agree with an even higher accuracy. This coupling accuracy may be required in order to avoid objectionable perception of the color tone or variations of the gray scale in a portion of a displayed image that is assumed to be uniform. Typically, a single digital-to-analog converter of a current sum type can be built, using a common centroid deployment technique, to prevent significant deviations of the process parameters between the digital-to-analog converter of the current sources. However, due to the large number of digital-to-analog converters required in the pulse circuitry of a liquid crystal display, it is not practical to obtain the aforementioned common centroid display with respect to all the current sources of those digital converters. analogical. In addition, the sum resistors of the different digital-to-analog converters can suffer from a bad coupling, because each can be subject to a greater inaccuracy than, for example, 1 ent. It may be desirable to calibrate the digital-to-analog converters in an automatic and odic manner during the otion of the visual display of the liquid crystal display, to improve the accuracy of digital-to-analog converters. In a given digital-to-analog converter, which incorporates a feature of the invention, the current sources are controlled in common in a current mirror configuration by a control signal. The digital-to-analog converter is automatically calibrated by comparing its current voltage. . output to the full scale with a reference voltage. An error signal is applied that occurs to a sample and sustain configuration. A voltage developed in a capacitor of the sampling and holding configuration is used to generate the control signal of the current sources in a feedback or servo cycle. A change in the control signal varies each of the currents of the current sources by the same proportion in a way to maintain constant current ratios. In accordance with a feature of the invention, the same reference voltage is used in common with each of the digital-to-analog converters. Accordingly, in a convenient manner, any poor coupling of the accuracy between the digital-to-analog converters is substantially reduced. A plurality of digital-to-analog converters, incorporating one aspect of the invention, generate a plurality of analog output signals that are applied to a plurality of data line drivers of a video display apparatus. A plurality of switched networks are included. A given switched network is associated with a given digital-to-analog converter, and responds to a corresponding input data word. The given switched network produces a corresponding analog output signal according to the weights of the bits of the data word. A comparator associated with the given digital-to-analog converter, responds to a reference signal, and to a signal indicating the analog output signal of the given digital-to-analog converter. The comparator generates an error signal according to a difference between the reference signal and the signal indicating the analog output signal. The same reference signal is used to generate each error signal in each of the plurality of digital-to-analog converters. The error signal that is associated with the given digital-to-analog converter is coupled to the switched network of the given digital-to-analog converter, to automatically adjust the output signal of the digital-to-analog converter given in a cycle fashion manner. Servo In accordance with another aspect of the invention, a digital-to-analog current-sum type converter includes a plurality of switched current sources which are controlled in common in a current mirror configuration, and which are selected in accordance with a word of input data. An analog output signal is produced from the currents of the selected current sources. A comparator responds to a reference signal and to a signal indicating the output signal to generate an error signal according to a difference between them. The error signal is coupled with the current mirror configuration to automatically adjust the analog output signal in a servo cycle manner. Figure 1 illustrates a liquid crystal display configuration that includes auto-calibrated digital-to-analog converters, which incorporate an aspect of the invention. Figure 2 illustrates in detail one of the auto-calibrated digital-to-analog converters of Figure 1. In Figure 1, a video signal representing the image information to be displayed is received from, for example, an antenna 12. An analog circuitry 11 provides a video signal on a line 13 as an input signal to an analog-to-digital (A / O) converter 14. The television signal from the analog circuitry 11, is displayed in a liquid crystal assembly 16 which is composed of a large number of pixel elements, such as a liquid crystal cell 16a configured horizontally at n = 560 rows, and vertically at n = 960 columns. The liquid crystal assembly 16 includes n = 960 columns of data lines 17, one for each of the vertical columns of the liquid crystal cells 16a and n = 560 selection lines 18, one for each of the horizontal rows of the liquid crystal cells 16a. The analog-to-digital converter 14 includes an output bus 19 to provide brightness levels, or gray scale codes, to a memory 21 having 40 groups of output lines 22. Each group of output lines 22 of the memory 21 applies the stored digital information to a corresponding digital-to-analog converter (D / A) 23, which incorporates a feature of the invention. There are 40 digital-to-analog converters 23 which correspond to the 40 groups of lines 22, respectively. An output signal OUT of a given digital-to-analog converter 23 is coupled by means of a corresponding line 31, with a corresponding demultiplexer and data line driver 100, which stores the OUT signal. During an interval of 13 microseconds of a given video line time, the OUT signals of the digital-to-analog converter 23 are produced and stored in each of the 24 successive conversion cycles. As a result, the OUTPUT signals are stored in each of the 960 data line drivers and demultiplexers 100. The time between the conversion cycles is approximately 1.24 microseconds. A selection line scanner 60 produces row selection signals on lines 18 to select, in a conventional manner, a given row of set 16. The voltages developed on 960 data lines 17 are applied, during a line time of 32 microseconds, to the pixels 16a of the selected row. As indicated above, a given data bus driver and demultiplexer 100 is used to store the corresponding OUTPUT signal, and to transfer the stored OUTPUT signal to a corresponding data line 17. Each data line 17 is applied to 560 rows of pixel cells 16a. The demultiplexer and data line driver 100 operates as a ramp amplifier in parts. The reference ramp signal RA PA-REF, and the OUT signal, are applied to a comparator 24 which controls an output transistor MN6. A RAMP-DATA data ramp voltage is applied to the data line 17 by the transistor MN6, during each video line time, until a time when the comparator 26 disables the transistor MN6. The instant in which the comparator 26 disables the transistor MN6, is determined by the magnitude of the OUTPUT signal. Accordingly, the voltage of the pixel is determined by the OUTPUT signal. An example of a configuration that may be similar to the demultiplexer and data line driver 100 is explained in detail in the Plus et al. Patent. Figure 2 illustrates in detail one of the self-calibrated digital-to-analog converters 23 of Figure 1, which incorporates a feature of the invention. Similar symbols and numerals of Figures 1 and 2 indicate similar items or functions. Each of the auto-calibrated digital-to-analog converters 23 of Figure 2, converts an 8-bit data word W, containing pixel video information, into analogue OUTPUT voltage. It includes, for example, 28-l = 255 switched current sources 120, which are constructed to be coupled to one another using, for example, a common centroid display. Each switched-mode power source 120 includes a non-switched current source transistor 110, formed by a P-type metal oxide semiconductor transistor (PMOS). Each transistor 110 has a source electrode which is coupled via a common line 110a to the supply voltage of + 5V, and a gate electrode which is coupled in common with the gate electrodes of the other transistors 110 by means of a line 110b. The line 110b is coupled with a drain electrode of a current type P metal oxide semiconductor transistor 111. The transistor 111 has its gate and drain electrodes coupled to each other. A control current lili in transistor 111 controls a magnitude of a current 1110 in each transistor 110, in a current mirroring manner. Each current 1110 has the same magnitude, and it tracks each current 1110 of the other transistors 110 of the digital-to-analog converter 23. In a given switched-current source 120, the transistor of the current source 110 is coupled with a source electrode. of a corresponding P-type metal oxide semiconductor switch transistor 113, and with a source electrode of a corresponding P-type metal oxide semiconductor switch transistor 114. The drain electrodes of transistors 114 are coupled in common with a drain electrode of a N-type metal oxide semiconductor transistor (NMOS) current adder 116, of a current mirror configuration 117. The drain electrodes of each of the transistors 113 are coupled with a reference terminal a ground 118. The switched current sources 120 are organized into 8 groups which are controlled by the 8 bits of the word, respectively. The number of switched current sources 120 that are included in a given group is determined by the weight of the corresponding bit of the word that controls the switched current sources 120 in the group. Accordingly, for example, 127 switched current sources 120 are controlled by a more significant bit MSB of the word W; while a switched current source 120 is controlled by a least significant bit LSB of the word. There are a total of 255 switched current sources 120 in the digital-to-analog converter 23. The gate electrodes of each of the transistors 114 of a given group of switched current sources 120, are coupled in common with an output of a corresponding inverter gate 121. The inverter gate 121 applies a logic level LOW when the corresponding bit of the word is at a logic level HIGH, in a manner to drive transistors 114. Accordingly, current 1110 of each transistor 110 is coupled by means of the corresponding transistor 114, with the current adder transistor 116, and contributes to a current 1116 in the transistor 116. Accordingly, a current 1116 in the transistor 116 is increased by an amount that is determined by the weight of the control bit of the word W. The gate electrodes of each of the transistors 113 of this group of switched current sources 120, are coupled in com with an output of a corresponding inverter gate 122. The inverter gate 122 applies a logic level HIGH, when the corresponding bit of the word is in the logic level HIGH. Consequently, the transistors 113 are turned off. On the other hand, the corresponding inverter gate 121 applies a logic level HIGH when the corresponding bit of the word is at a logic level LOW. Accordingly, transistors 114 are deactivated, and transistors 113 are activated in a manner to decouple current 1110 in each transistor 110, from current adder transistor 116. Therefore, currents 110 do not contribute to current 1116 in the transistor. 116 when the word bit is in the logic level LOW. Conveniently, current 1110 continues to flow unaltered in one of transistors 113 and 114, regardless of the state of the control bit of the word. In this way any alteration of the current switching is conveniently reduced. A full scale of OUTPUT voltage is presented, when each current 1110 in the digital-to-analog converter 23, is coupled with transistor 116. This situation occurs when all 8 bits of the word are in the HIGH state. A zero scale is presented when none of the currents 1110 is coupled with the transistor 116. This situation occurs when the 8 bits of the word are in the LOW state. The summation current 1116 controls a summation current 1123 in a transistor 123 in a current mirroring manner. It follows that the summation current 1123 is increased by a value proportional to the current 1110 when the value of the data word W is increased by one. The current 1123 is coupled with an inversion terminal 124 of an inversion amplifier 125. An output terminal 126 of the inversion amplifier 125 is coupled to the terminal 124 by means of a resistor R. A level change voltage is coupled. of 1.5V to a non-inverting input terminal of the amplifier 125. Accordingly, the analog output voltage OUT of the amplifier 125 is equal to 1.5V + (the value of the summation current 1123 multiplied by the value of the resistor R). When the value of each bit of the word is zero, the OUTPUT voltage is equal to 1.5V. Accordingly, the 1.5V voltage determines the zero scale level of the OUTPUT voltage. A self-calibrating circuit 130 incorporating a feature of the invention includes a differential error amplifier 131 having an inverting input terminal that couples with the output terminal 126 of the amplifier 125, and a non-inverting input terminal that it is coupled with a source, not shown, of a reference voltage VREF, which corresponds to the VREF shown in Figure 1. Amplifier 131 includes a differential pair of metal oxide semiconductor transistors type P 132 and 133, coupled with a pair of metal oxide semiconductor charge transistors type N 138 and 139, respectively. A P 135 metal oxide semiconductor transistor, a current control resistor 137, and a transistor 134 which are coupled in series, control the sum of the currents in transistors 132 and 133 by means of a transistor 136 in a manner of current mirror. An output terminal 140 of the error amplifier 131 is coupled by an error-switching type N-type metal oxide semiconductor transistor 141 to a small sampling capacitance CP1 which may be a parasitic capacitance. The capacitance CP1 is coupled by means of a semiconductor transistor of metal oxide type N 142, to a second integrating capacitance CP2. The transistors 141 and 142 are controlled by complementary control signals of SAMPLING and SAMPLING-INVERSE, respectively. A clamp transistor 150 is coupled between the terminal 140 and a junction terminal 151. The junction terminal 151 is coupled between the transistors 132 and 139. The periodic error sampling of the digital-to-analog converter 23 is presented during an interval of error sampling 160 of the SAMPLE-INVERSE signal, between the successive digital-to-analog conversion intervals 161. During the error sampling interval 160, a pulse of the sampling control signal SAMPLES, activates transistor 141, and a complementary pulse of the SAMPLE-INVERSE sampling control signal turns off the transistor 142. During the sampling interval 160, the SAMPLE signal is applied to an output stage, not shown, of the memory 21 of FIGURE 1, for produce the word that has all its bits in the logical state HIGH. The SAMPLE-INVERSE signal deactivates the transistor 150 in a manner to enable the generation of an ERROR error signal in the terminal 140. Accordingly, the capacitance CP1 develops an error correction voltage VCP1, which is proportional to a difference between the OUTPUT voltage, full scale, and the VREF voltage. After the sampling interval 160, the sample control signal SAMPLING, turns off the transistor 141 and the sample control signal SAMPLE-INVERSE, activates the transistor 142. Consequently, a load stored in the capacitance CP1 is applied which indicates a error in the full-scale OUTPUT voltage, to the error integrating capacitor CP2, to generate a control voltage VCP2. In the continuous state operation, the voltage VCP2 tends to keep the OUTPUT voltage tightly at the voltage level VREF. The holding transistor 150 is conductive at all times, except during the interval 160. Accordingly in a convenient manner, the external sampling interval 160, a signal developed at the terminal 140, is constant in a manner to prevent the introduction of a Noise signal to capacitors CP1 and CP2. The voltage VCP2 is coupled by means of a semiconductor metal oxide semiconductor transistor type N of the source 143, to a voltage to current converter formed by a series configuration of a resistor R1 and a semiconductor transistor of metal oxide type No. 144. The transistor 144 has its gate electrode coupled with its drain electrode. The drain / gate of transistor 144 is coupled to the gate of a metal oxide semiconductor transistor type N 145, to form a current mirror configuration. A current 1145 in transistor 145 is proportional to control voltage VCP2. Current 1145 is a variable current that is added with a constant current 1147 in a transistor 147, to flow as a summation current 1111 in transistor 111. Current 1147 is established in a current mirror manner by a current 1146 that it flows in a transistor 146. Current 1111 controls each of the currents 1110 in a current mirroring manner. A difference or an error between the OUTPUT and VREF voltages, causes current 1145, and consequently, current lili, to change. Consequently, a change occurs in each of the current 1110. Accordingly, the error in the current 1110 is corrected in a servo cycle manner. The error can be corrected at least partially during a given sampling interval 160. A large error may require several sampling intervals for a complete correction. In accordance with a feature of the invention, the error in each of the digital-to-analog converters 23 is corrected using the same reference voltage VREF. Accordingly, in a convenient manner, the differences in the values of the resistors R, or in the values of the currents 1110 between the digital-to-analog converters 23, does not significantly affect the full-scale OUTPUT voltage couplings. . The zero-scale OUTPUT voltage is not significantly affected by the resistors R or the currents 1110, because the currents 1110 are zero on the zero scale. At any intermediate value of the word, the accuracy is maintained because, in each digital-to-analog converter 23, the currents 1110 are equal to one another. Each transistor of the digital-to-analog converter 23 can be implemented using bipolar transistor technology.

Claims (13)

1. A plurality of digital-to-analog converters (23, Figure 1) for generating a plurality of analog output signals (OUTPUT) that are applied to a plurality of data line drivers (100) of a video display apparatus, which comprising: a plurality of switched networks (120, 121, 122), a given switched network being associated with a given digital-to-analog converter, and responding to a corresponding input data word to produce a corresponding analog output signal ( voltage at 124) according to the weights of the bits of that data word; a source of a reference signal at a reference level (VREF); characterized by: a plurality of comparators (131), a given comparator 131 being associated with the given digital-to-analog converter, and which responds to the reference signal and to a signal (voltage 133) indicating the analog output signal (OUTPUT) ) of the given digital-to-analog converter, to generate an error signal (ERROR), according to a difference between them, in such a way that the same reference signal (VREF, Figure 1) is used to generate each signal of error in each of the plurality of digital-to-analog converters, coupling this error signal which is associated with the given digital-to-analog converter, with the switched network of the given digital-to-analog converter, to automatically adjust the output signal of the digital-to-analog converter given in a servo-cycle manner

2. A plurality of digital-to-analog converters according to claim 1, characterized by The digital-to-analog converter (23) further comprises a first switch (141) that responds to a periodic switch control signal (SAMPLING) and coupled with a first capacitance (CP1), and with the comparator, to sample the error signal, during an error sampling interval, and for storing this error signal sampled in the first capacitance, to produce a conversion scale control signal (1145) that couples with the given switched network of the converter digital to analog, to control a conversion scale.

3. A plurality of digital-to-analog converters according to claim 2, further characterized by a second capacitance (CP2), for coupling the first capacitance (CP1) with the second capacitance, outside the error sampling range, to integrate the sampled error signal (VCP1) in this second capacitance.

4. A plurality of digital-to-analog converters according to claim 2, characterized in that during the error sampling interval, the data word () has a previously determined value (11., .1) that is associated with the level of the reference signal, and outside of the error sampling interval, this data word contains pixel video information.

5. A plurality of digital-to-analog converters according to claim 4, characterized in that during the error sampling interval, a value of the input data word () that is applied to the given digital-to-analog converter corresponds to a full-scale output signal (11 ..1).

6. A plurality of digital-to-analog converters according to claim 1, characterized in that the switched network (120, 121, 122) comprises a plurality of switched current sources (120), of a digital to analog type converter. of current summation, and wherein each of the plurality of switched current sources is adjusted by this error signal in a current mirror configuration (111, 110).

7. A plurality of digital-to-analog converters according to claim 6, characterized in that the switched current sources (120) comprise a plurality of non-switched current sources (110) controlled in common by the error signal., and a plurality of switches (114, 113) coupled with the non-switched current sources to form the switched current sources. A plurality of digital-to-analog converters according to claim 1, characterized in that the given digital-to-analog converter comprises a plurality of switched current sources (120) for generating currents that are combined in a current sum resistor (R) to develop a voltage in this resistor, and wherein the voltage in this resistor is coupled with the comparator (131) to generate the error signal (ERROR) in a manner to reduce a dependence of the output signal in the value of the resistor. 9. A digital-to-analog converter of current sum type, which comprises: a source of a word of input data (W); a plurality of switched current sources (120) which are controlled in common in a current mirror configuration (110, 111), and which are selected in accordance with the data word to produce, from the source currents of selected currents, an analog output signal (voltage at 124); a source of a reference signal (VREF) at a reference level; characterized by: a comparator (131) responding to the reference signal, and a signal indicating the output signal to generate an error signal (ERROR) according to a difference between them, coupling the error signal with the Current mirror configuration, to automatically adjust the analog output signal in a servo cycle way. A digital-to-analog converter according to claim 9, further characterized by a first switch (141) that responds to a periodic switch control signal (SAMPLING), and coupled with a first capacitance (VCPl), and with the comparator, for sampling the error signal, during an error sampling interval, and for storing this error signal sampled at the first capacitance, to produce a conversion scale control signal (1145) that is coupled with the configuration mirror current from digital to analog converter, to control a conversion scale. A digital-to-analog converter according to claim 10, further characterized by a second capacitance (CP2), which is coupled with the first capacitance (CP1), outside the error sampling range to integrate the sampled error signal in the second capacitance. 12. A digital-to-analog converter according to claim 10, characterized in that, during the error sampling interval, the data word (W) has a predetermined value (11 .1) that is associated with the level of the reference signal, and outside of this error sampling interval, this data word contains pixel video information). 13. A digital-to-analog converter according to claim 12, characterized in that, during the error sampling interval (ERROR), a value of the input data word (11 .1) that is applied to the converter from digital to analog, corresponds to a full-scale output signal.