MXPA96004528A - System memory unit with performance / improved cost, using dynamic random access memory with extend data output - Google Patents

Abstract

The present invention relates to a system memory unit to a computer system comprising circuits for generating control and memory address, a number of dynamic random access memory banks with extended data output (EDODRAM), and a number of records. The circuits for control generation and memory address are used to generate memory addresses for the EDODRAMs, advantageously supplied on two lines of address duct. Additionally, circuits for memory address control generation are used to generate control signals for EDODRAMs and registers, including advantageously "trimmed" column address strobe signals (CAS). The EDODRAMs are used to accept, store and send out data, according to the memory addresses provided. The registers are used to provide in stages the data that is continuously taken from or towards the EDODRAMs. As a result of the advantageous ways in which memory addresses and CAS signals are provided, the cycle time of a memory access is reduced, even if the circuit elements based on slower CMOS technology to constitute the circuits for generation control and memory address, the EDODARAM, and the registr

Description

SYSTEM MEMORY UNIT WITH PERFORMANCE / IMPROVED COST, USING DYNAMIC RANDOM ACCESS MEMORY WITH EXTENDED DATA OUTPUT BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of computer systems. More specifically, the present invention relates to system memory, for computer systems. 2. Background Information. All computer systems include some amount of system memory. The system memory is substantially slower than the processor. Most computer systems also include cache memory to bypass the performance space between the processor and the system memory. While the cache memory is still slower than the processor, it is faster than the system memory. As the speed of the processor continues to increase, various techniques have been developed to allow the cache to be kept with the fastest processors. Some of these enhanced cache units are capable of performing cache access in as little as six clock cycles, at 66 MHz processor speed (15 ns per clock period). The improved cycle time represents 3Q% -50% reduction in cycle time required by traditional cache units. In contrast, the memory access cycle time for the most common system memory units using dynamic random access memory based on CMOS technology (DRAM) has remained virtually unchanged, requiring 18 to 20 clock cycles at 66 MHz . Therefore, it is convenient to be able to reduce the memory access cycle time of the system memory to maintain speed with the improved cache memory. An emerging solution to the "slow" system memory problem is to use faster Synchronous DRAMs (SDRAMs) based on bi-CMOS technology. SDRAMs are approximately 100% faster than conventional DRAMs. As a result, these faster system memory units can reduce the memory access cycle time by almost 50%. At 66 MHz, a memory access can be completed in as little as 7 to 10 clock cycles. However, at present, SDRAMs cost twice as much as conventional DRAMs. In other words, it takes almost 100% increase in system memory cost, to * achieve a 50% reduction in memory access cycle time. In this way, the fastest system memory unit using SDRAMs is not an economically viable solution for low-scale computer systems, such as entry-level microprocessor-based desktop or laptop computers.

In this way, it is convenient to close the performance space between the improved cache memory and the "slow" system memory, with a much more cost effective solution. As will be described in more detail below, the present invention advantageously achieves these and other desirable results. SUMMARY OF THE INVENTION Under the present invention, the desired results are advantageously achieved by providing a system memory unit to a computer system comprising circuits for generating control and memory address, a number of dynamic random access memory banks with extended data output (EDODRAM, also known as Hyperpage DRAM in the technique), and a number of records. The circuits for control generation and memory address are used to generate memory addresses for EDODRAMs, advantageously supplied on two lines of address duct. Additionally, the circuits for control generation and memory address are used to generate control signals for the EDODRAMs and the registers including column direction sampling signals advantageously "trimmed" (CAS) EDODRAMs are used to accept, store and send data in accordance with the memory addresses provided. The registers are used to send in stages the data that flows continuously out of or towards the EDODRAMs. As a result of the advantageous way to supply memory addresses and CAS signals to the EDODRAMs, the cycle time of a memory access is reduced, even if the circuit elements based on slower CMOS technology are used to constitute the circuits. of control generation and memory address, the EDODRAMs and the registers. During operation, the circuits for control generation and memory address provide the MSs of the memory addresses generated on a line of address conduit, and the LSBs of the memory addresses generated on another line of address conduit, allowing this so that the column memory address is changed quickly. The circuits for control generation and memory address, exploiting the independence of the data output of EDODRAMs with respect to the CAS signals, advantageously withdraw the CAS signal at an early time for each column memory address, to allow an early Memory cell load and in turn faster response to the column memory address. Experience has shown that at a processor speed of 66 MHz, under the present invention, a memory access can be performed at approximately 11 to 13 clock cycles, which represents approximately a 35% reduction in cycle time, including when circuit elements based on conventional CMOS technology are used, to constitute the system's memory unit. More importantly, the 35% reduction in cycle time is achieved with very little increase in cost. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 illustrates an exemplary computer system embodying the teachings of the present invention. Figure 2 illustrates the relevant portions of the embodiment of the system memory unit of the present invention of Figure 1, in greater detail. Figure 3 illustrates the key elements of the address generation portion of a circuit mode for control generation and memory address of Figure 2, in greater detail. Figures 4a-4b are two synchronization diagrams for the memory unit of the system of the present invention of Figure 1, which operates at an exemplary processor speed of 66 MHz.

In the following description, for explanation purposes, specific numbers, materials and configurations are set forth in order to provide a complete understanding of the present invention. However, it will be apparent with skill in the art that the present invention can be practiced without the specific details. In other cases, they are illustrated in well-known systems in the form of a block diagram or diagrammatic in order not to obscure the present invention unnecessarily. Now with reference to Figure 1, a block diagram showing an exemplary computer system embodying the teachings of the present invention is illustrated. The exemplary computer system 10 comprises a processor 12, a cache memory 14, a system memory 16 and a controller 15 coupled to one another through the conduit of the processor 13. Additionally, the exemplary computer system 10 further comprises a number of devices. I / O (1/0) 18 coupled to the controller 15 through an I / O conduit 20. In the currently preferred mode, the processor 12 is arranged in a single integrated circuit (chip). The processor integrated circuit, the cache memory 14, the system memory 16 the controller 15 and the two conduits 13 and 20 are arranged in a single circuit board. Except for the teachings embodied in the system memory unit 16, the processor 12 and the cache memory 14,.,., And the I / O conduit 20 are intended to represent a broad category of these elements that are found in many systems of computer. Their constitutions and functions are well known and will not be described further.

While the present invention is described with the exemplary computer system having the illustrated architecture, and the arrangement described above, based on the description that follows, it will be appreciated that the present invention can be practiced with computer systems having different architectures and these elements physically arranged in other forms. Now with reference to Figure 2, a block diagram illustrates the relevant portions of a modality of the system memory 16 of Figure 1, in greater detail. As illustrated, the system memory 16 comprises circuits for control generation and memory address 22, a number of banks of EDODRAM 24 a number of registers 26a-26b and preferably a buffer 34, coupled together as illustrated. As shown, the coupling between the circuits for control generation and memory address 22 and EDODRAM 24, preferably includes at least two lines for steering duct 28a and 28b. The EDODRAM 24 are organized in pages. The circuits for control generation and memory address 22 are used to generate memory addresses for the EDODRAM 24. In addition, the circuits for control generation and memory address 22 are used to generate control signals for the EDODRAM 24 and the registers 26a and 26b. The buffer 34 is used to buffer the most significant bits (MSBs) of the memory addresses. The buffer 34 is preferably used to reduce the amount of energy required to direct the MSBs of the memory addresses on the first line of Address Conduit 28a, for the EDODRAMs 24 as typically, the system memory includes a large amount of memory. of banks. The EDODRAM 24 is used to accept, store and send data output. EDODRAM 24 store and send data output EDODRAM 24 stores and sends data output according to the memory addresses provided. The registers 26a and 26b are used to send in stages the data that is stored inside or outside the EDODRAM 24. During operation, the circuits for control generation and memory address 22 receive direction and control signals on the processor conduit 13 . In response, the circuits for control generation and memory address 22 generate memory addresses for the EDODRAM 24. Additionally, the circuits for control generation and memory address 22 provide control signals to the EDODRAM 24 and registers 26a and 26b, including a row direction sampling signal (RAS) and a column address sampling signal (CAS) for the EDODRAM 24 and stores the signals (MST and WST) for the registers 26a and 26b. The controller 15 generates all other control signals as required by the EDODRAM 24. As illustrated, the MSBs of the memory, column or row addresses are preferably provided to the EDODRAMs 24 on the first line of address conduit. 28a, while the LSBs of the memory, row or column addresses are preferably provided to the EDODRAMs 24 on the second line of address conduit 28b. As will be described in more detail below, as a result of the advantageous way of providing the memory addresses to the EDODRAMs 24, the memory addresses, in particular the column addresses, are provided at a faster speed to the EDODRAMs 24. Additionally, the circuits for control generation and memory address 22, exploiting the independence of the data output of EDODRAM with respect to the CAS signal, advantageously remove the CAS at an early stage for each column memory address that allows rapid pre-loading of the memory cells. As will also be described in more detail below, as a result of the advantageous way of providing the CAS signal, the data is sent in stream outside or within the EDODRAM 24 at a faster rate. Together, the faster supply of memory addresses and the faster response of the EDODRAM 24 results in a reduction in the total cycle time of a memory access.

The EDODRAM 24 receive the memory addresses and the control signals as feeds. In response, EDODRAM 24 sends data in or out of EDODRAM (MDATA). The registers 26a store each of the data that is sent in stream outside the EDODRAM 24, for read access momentarily, to accommodate the processor configuration time, in response to the MST signal. The register 26b stores each of the data that is sent in current to the EDODRAM 24 for a write access momentarily for operation symmetry, in response to the WST signal. The circuits for generating and controlling memory address 22 will be described in greater detail below. A particular example of EDODRAM 24 is KM44C4004A based on CMOS technology manufactured by Samsung Corporation of Korea, which have operating speeds of 60 ns for RAS to data and 15 ns for CAS to data. The registers 26a-26b are well known and will not be described further. The synchronization of the key signals for effecting the key signals for effecting consecutive and fast current placement of data outside of and within the EDODRAM 24 will be described in greater detail below. Now with reference to Figure 3, a block diagram illustrating key element of the address generation portion of a circuit mode for control generation and memory address 22 of Figure 2 is illustrated in more detail. The portion for generating control signals of the circuits for control generation and memory address 22 can be implemented in any number of ways known in the art. As illustrated, the address generation portion 23 comprises the register 32, an increment 28 and an assembly of XOR gates 30, coupled together as illustrated. The register 32 stores the received start address on the processor conduit 13. The incrementer 28 generates a predetermined series of increment values. The set of the XOR gates 20 generates the LSBs of the memory addresses when performing a series of logical XOR operations against the LSBs of the stored start addresses that are read from the register 32 and the generated increment values. The manner in which the incrementer 28 generates the increment values, and the XOR operations performed are dependent on the system memory access characteristics of the processor 12 and / or the cache memory 14. For example, for the Pentiupp processor, Intel Corporation, if the addresses for a line fill are OxOOOOlOlOH, 0X00001018H, OxOOOOlOOOH and 0x000Q1008H, the addresses for OxOOOH row memory while the addresses for column memory are 0X202H, 0x203H, 0x200H and 0x201H. In other words MA [10: 2] are 0x200H for all four directions of column memory, and MA [1: 0] are 0x2H, 0x3H. OxOH and OxlH for the four column memory addresses. The LSBs of the memory addresses advantageously "divide" and supply the EDODRAMs 24 on the second line of address conduit 28b, to allow the column memory address to be changed at a faster rate by shunting the buffer 34 and save the time that would otherwise have been spent by changing the contents of the buffer 34 when the column memory address is changed. Since only a small number of bits are routed directly to the EDODRAMs 24, the fastest speed of supplying column addresses is advantageously achieved with minimum increase in the energy requirement of the circuits for control generation and memory address 22. Now with Referring to Figures 4a-4b, two synchronization diagrams illustrating the relative timing for a number of key signals for read and / or write access against the system memory 16 of Figure 1 are illustrated. The relative timing of both diagrams are illustrated at an exemplary processor speed of 66 MHz (15ns per clock period) 42, and considering page encounters ie the row memory address remains unchanged from the previous access. In this way, for both reading access as writing, the meeting signal <The page (PGHIT) 46 and the RAS 52 signals simply remain active throughout the duration (to a t10) as illustrated in the two diagrams. Similarly, the MSBs of the memory column address (MA [10: 2]) 48 and therefore the MSBs based on the buffer (BMA [10: 2]) 52, are maintained for the entire duration (to a t10) as illustrated in the two diagrams. Now with reference only to Figure 4a, for read access, since the LSBs of the memory column addresses can be generated rapidly and except for the first memory column address, the subsequent memory column addresses are answered in 15ns , the LSBs of the memory column addresses (MA [1: 0]) 50 are provided and maintained using approximately 11 clock periods (to a t10), as illustrated. The signal CAS 56 is correspondingly removed and rapidly removed in 8 clock periods (t3 to t10) as illustrated. In this way, the memory data (MDATA) 58 is detected in the nine clock periods (t3 to tlx) as illustrated. The internal registration data (iREGDATA) 61 is stored in the nine clock periods (t "to t12) as illustrated. The signal MST 60 is therefore removed correspondingly in the eight clock periods (t5 to t12) as illustrated. As a result, the read data (ODATA) is detected in the eight clock periods (t6 to t13) as illustrated. In other words, the total cycle time for a read access is reduced to thirteen clock periods, an improvement of 35% in total cycle time, even if the EDODRAMs based on slower CMOS technology are used. Now with reference only to Figure 4b, for a write access, similarly since the LSBs of the memory column addresses can be generated quickly and except for the first memory column address, the subsequent memory column addresses are answered in 15ns, the LSBs of the memory column addresses (MA [1: 0]) 50 are provided and maintained using approximately 15 clock periods (or to t10) as illustrated. The CAS signal 54 is correspondingly withdrawn and withdrawn early in 8 clock periods (t3 to txo) as illustrated. In this way, with the write data 63 supplied using nine clock periods (to a t8) as illustrated. The internal registration data (iREGDATA) 61 is stored in the nine clock periods (t4 to t12) as illustrated. The WST signal 59 is correspondingly removed in the eight clock periods (tx to t8), as illustrated. As a result, the memory data is available to store in the nine clock periods (t2 to t10) as illustrated. In other words, the total cycle time for a write access is reduced to eleven clock periods, an improvement of 39% in total cycle time, even if the EDODRAMs based on slower CMOS technology are used.

While the present invention has been described in terms of currently preferred and alternate embodiments, those skilled in the art will recognize that the invention is not limited to the embodiments described. The method and apparatus of the present invention can be practiced with modifications and alteration, within the spirit and scope of the appended claims. The description in this manner will be considered illustrative rather than limiting of the present invention.

Claims (24)

1. EIVI DICA IONES 1.- A system memory unit, characterized in that it comprises: (a) circuits for generating control and direction, for generating a sequence of memory addresses and control signals for read access, the control signals include column direction sampling (CAS) signals that are removed early; (b) a number of dynamic random access memory banks with extended data output (EDODRAM) coupled to the circuits for control and direction generation, for storing a plurality of data and a plurality of EDODRAM memory cells and sending When a sub-set of data is output in response to the sequence of memory addresses and control signals, the EDODRAM keeps the data output independent of the CAS signals and pre-loads the memory cells by removing the CAS signals.
2. 2. The system memory unit as described in claim 1, characterized in that the circuits for control and direction generation are sufficiently energized, to direct directly the generated sequence of memory addresses for all banks of EDODRAMs.
3. 3. The system memory unit as described in claim 1, characterized in that the circuits for generation of control and direction generates common most significant bits (MSBs) of the sequence of memory addresses and less significant non-common bits (LSBs) ) of the sequence of memory addresses, the non-common LSBs are generated consecutively and the common MSBs are generated while the unusual LSBs are generated.
4. 4. The system memory unit as described in claim 3, characterized in that the circuits for generating control and address consecutively generate LSBs uncommon in a plurality of consecutive clock periods and generate the common MSBs during all periods of consecutive clock; the circuits for generation of control and direction also generates and removes the CAS signals correspondingly and the EDODRAMS consecutively send the corresponding sub-data set of output, pre-load appropriate memory cells when removing the CAS signals.
5. 5. The system memory unit as described in claim 4, characterized in that the circuits for generation of control and direction consecutively generate LSBs uncommon in eleven consecutive clock periods and generate the MSBs during all eleven clock periods consecutive; EDODRAMS consecutively sends out the corresponding sub-data set in nine consecutive clock periods.
6. 6. - The system memory unit is coupled to a processor that operates at a processor velpcity of at most 66 MHz; and the circuits for control and direction generation and the EDODRAMS are constituted with circuit elements based on CMOS technology.
7. 7. The system memory unit as described in claim 3, characterized in that the address generation portion of the circuits for control and address generation comprises: (a) a register for storing and sending out an address of access for reading access; (a.2) an increment to receive a base value and generate a plurality of increment values in a pre-determined form; and (a.3) an XOR gate assembly coupled to the register and the incrementer, to generate LSBs using the access address and the incremental values.
8. 8. The system memory unit as described in claim 3, characterized in that the system memory unit also comprises a buffer memory coupled to the circuits for control and direction generation and the EDODRAMs for buffering the EDODRAMs Common to the sequence of memory addresses generated by the circuits for generation of control and direction for the EDODRAMs.
9. 9. - A system memory unit, characterized in that it comprises: (a) circuits for generating control and direction, for generating a sequence of memory addresses and control signals for a write access, the control signals include sampling signals of column address (CAS) that are removed early; (b) a number of dynamic random access memory banks with extended data output (EDODRAM) coupled to the circuits for control and direction generation, to accept and store a plurality of data in a plurality of EDODRAM memory cells , in response to the sequence of memory addresses and control signals, the EDODRAMs keep the data output independent of the CAS signals and pre-load the memory cells by removing the CAS signals.
10. 10. The system memory unit as described in claim 9, characterized in that the circuits for control and direction generation are sufficiently energized, to direct directly the generated sequence of memory addresses for all banks of EDQDRAMs.
11. 11. The system memory unit as described in claim 9, characterized in that the circuits for generating control and direction generate the most significant common bits (MSBs) of the sequence of memory addresses and the least significant non-common bits. (LSBs) of the sequence of memory addresses, the non-common LSBs are generated consecutively and the common MSBs are generated while the unusual LSBs are generated.
12. 12. The system memory unit as described in claim 11, characterized in that the circuits for generation of control and direction consecutively generate the LSBs uncommon in a plurality of consecutive clock periods and generate the common MSBs during all periods of consecutive watches; the circuits for generation of control and direction also generates and removes the CAS signals correspondingly; and the EDODRAMs consecutively accept and store the sub-data set accordingly, pre-loading appropriate memory cells when removing the CAS signals.
13. 13. The system memory unit as described in claim 12, characterized in that the circuits for generation of control and direction consecutively generate the LSBs uncommon in eleven consecutive clock periods and generate the MSBs during all eleven consecutive clock periods.; the EDODRAMS consecutively accept and store the sub-data set correspondingly in nine consecutive clock periods.
14. 14. The system memory unit as described in claim 13, characterized in that the system memory unit is coupled to a processor that operates at a processor speed of at most 66 MHz; and the circuits for control and direction generation and the EDODRAMs are constituted with circuit elements based on CMOS technology.
15. 15. The system memory unit as described in claim 11, characterized in that the address generation portion of the circuits for control and address generation comprises: (a) a register for storing and sending out an address of access for write access; (a.2) an increment to receive a base value and generate a plurality of increment values in a pre-determined form; and (a.3) an XOR gate assembly coupled to the register and the incrementer, to generate the LSBs using the access address and the incremental values.
16. 16. The system memory unit as described in claim 11, characterized in that the system memory unit also comprises an intermediate memory coupled to the circuits for control and direction generation and the EDODRAMs for buffering the EDODRAMs. Common to the sequence of memory addresses generated by the circuits for generation of control and direction for the EDODRAMs.
17. 17. Method to accept, store and send data output, characterized in that it comprises: (a) generating a sequence of memory addresses and control signals for a read access, the control signals include column address sampling signals (CAS) that retire early; (b) storing a plurality of data in a plurality of memory cells of a number of dynamic random access memory banks with extended access output (EDODRAM) and sending out a subset of data in response to the sequence of memory addresses in control signal, the output is achieved by keeping the data output independent of the CAS signal and pre-loading memory cells when removing the CAS signals.
18. 18.- The method of compliance with the claim 17, characterized in that the sequence of memory addresses are generated by generating the most significant common bits (MSBs) of the sequence of memory addresses and the least significant non-common bits (LSBs) of the sequence of memory addresses, the little LSBs commons are generated consecutively and common MSBs are generated while rare LSBs are generated.
19. 19. Method for accepting, storing and sending out data characterized in that it comprises: (a) generating a sequence of memory addresses and control signals for a write access, the control signals include column address sampling signals ( CAS) that retire early; (b) accepting and storing a plurality of data in a plurality of memory cells of a number of dynamic random access memory banks with extended output (EDODRAM), according to the sequence of control signals and memory addresses, the EDODRAM maintains data output independent of CAS signals and pre-loading memory cells when removing CAS signals.
20. 20.- The method according to the claim 19, characterized in that the memory address sequences are generated by generating the most significant common bits (MSBs) of the sequence of memory addresses and the least significant non-common bits (LSBs) of the sequence of memory addresses, the LSBs not commons are generated consecutively and common MSBs are generated while rare LSBs are generated.
21. 21. Circuit board, characterized in that it comprises: (a) a system memory having (a) circuits for generating address control, for generating a sequence of memory addresses and control signals for a read access, the control signals include column address sampling (CAS) signals that are removed early, (a.2) a number of dynamic random access memory banks with extended data output (EDODRAM) coupled to the circuits for control generation and address, to store a plurality of data in a plurality of EDODRAM memory cells and output a sub-data set, in response to the memory address sequence of memory and control signals, "EDODRAM maintains the data output independent of the CAS signals and preloading the memory cells when removing the CAS signals; (b) a cache memory unit, to pass a high-speed buffer to a sub-c set of data; (c) a controller coupled to the system memory unit and the cache memory unit to provide control signals to the cache and system units; and (d) a conduit coupled to the system memory unit and the cache memory unit, to provide addresses to the cache and system signals and to transfer data into and out of the system and cache units.
22. 22. Circuit board characterized in that it comprises: (a) a system memory having (a) circuits for generating address control, for generating a sequence of memory addresses and control signals for a write access, the control signals include column return sampling (CAS) signals that are removed early, (a.2) a number of dynamic random access memory banks with extended data output (EDODRAM) coupled to the circuits for control and direction generation , to accept and store a plurality of data in a plurality of EDODRAM memory cells in response to the sequence of memory addresses and control signals, the EDODRAMs maintain the data output independent of the CAS signals and preloading the cells of memory when removing CAS signals; (b) "a cache memory unit, for high-speed buffering a subset of the data; (c) a controller coupled to the system memory unit and the cache memory unit to provide control signals to cache and system drives; and (d) a conduit coupled to the system memory unit and the cache memory unit, to provide addresses to the cache and system signals and to transfer data into and out of the system and cache units.
23. 23. A computer system characterized in that it comprises: (a) a processor for executing a plurality of instructions; (b) a system memory having (bl) circuits for control generation and direction, for generating a sequence of control signals and memory addresses to generate a read access, the control signals include address sampling signals column (CAS) that are soon removed, (b.2) a number of dynamic random access memory banks with extended data output (EDODRAM) coupled to the circuits for control and direction generation, to store the instructions of a plurality in a plurality of memory cells of the EDODRAMs and sending out a subset of the instructions / data, in response to the memory address sequence of memory and control signals, the EDODRAMs maintain the independent data output of the CAS 'signal - and preloading the memory cells when removing the CAS signal; and (c) a conduit coupled to the processor and the system memory unit to provide addresses to the system memory unit and transfer instructions and data into and out of the system memory unit.
24. 24. A computer system characterized in that it comprises: (a) a processor for executing a plurality of instructions; (b) a system memory having (a) circuits for control and direction generation, for generating a sequence of memory addresses and control signals for write access, the control signals include column address sampling signals ( CAS) that are withdrawn soon, (a.2) a number of dynamic random access memory banks with extended data output (EDODRAM) coupled to the circuits for control and direction generation, to accept and store a plurality of data in a plurality of memory cells of the EDODRAMs in response to the memory address sequence of memory and control signals, the EDODRAMs keep the data output independent of the CAS signals and preloading the memory cells by removing the CAS signals; and (c) a conduit coupled to the processor and the system memory unit to provide addresses to the system memory unit and transfer instructions and data into and out of the system memory unit.