MXPA96004104A - Apparatus for detecting noise in a video signal to co - Google Patents

Abstract

The present invention relates to a phase detector providing angular phase error measurements of the color discontinuity component of a video input signal. Discontinuity phase errors that exceed a given angular threshold are detected, and the number that occurs within a given period of time are counted. From the accumulated account, a noise indicating signal (B0, B1) is derived and applied to a video image processor to control a parameter of displayed images.

Description

DEVICE FOR DETECTING NOISE IN A COLOR VIDEO SIGNAL This invention relates generally to electrical signal detectors and, in particular, to detectors to provide an indication of the noise content of color video signals. Video noise detectors are of general use in video signal processing apparatus. For example, such detectors can be used as an advantage in video systems of a type that are designed to vary functionally according to the noise level of the video signal that is being processed. Such noise-controlled apparatuses include, illustratively, those having programmable bandwidth filters responsive to noise, horizontal peak circuits responsive to noise, variable saturation chrominance processors responsive to noise, and noise-reducing recursive filters. , to name a few uses. For example, Shellard, in U.S. Patent 5, 396,293 entitled ICONIC FIRE CRITER WITH WIDTH OF DIVIDED BAN AS A FU NTION OF BIT ERROR AND LUMINANCE IMAGE, describes a digital video system in which the bandwidth is controlled as a function of the bit error rate ("BER") of the digital video signal. Under noisy conditions, the bit error rate is increased and used to perform a video bandwidth reduction. In a specific embodiment, the bandwidth is controlled as a function of the bit error rate and the amplitude level of the luminance signal. Cochran, in U.S. Patent 4,430,665 entitled COLOR CONTROL AND AUTOMATIC VIDEO SIGNAL PEAK, describes a video system in which noise is detected and used to control two functions, namely the signal level of chrominance and peak video signal. The noise, in the Cochran apparatus, is calculated in one example by a "long-term average" analysis of high frequency noise present in the video signal and is further calculated in another example with the help of the AGC circuits of the receiver. The luminance signal responsive to the noise calculation is controlled to exhibit significant filtering in the presence of noisy received and weak color television signals. Accordingly, the magnitude of the component of the chrominance signal is reduced to prevent a color image displayed from exhibiting super-saturated color. Triano, in US Pat. No. Serial No. 4, 376,952, entitled AUTOMATIC BEEP CONTROL APPARATUS FOR ANSWER TO RU RU, detects noise (for filtering purposes) by filtering the signal from a bandpass. video and applying the filtered signal to a detector via a sampling circuit that is enabled only during blank intervals in order to reject the active video portions of the luminance signal. The detector is of the average pulse type where the representative peak pulses of the sampled signal above a threshold level are generated and averaged to produce a smoothed control signal that is primarily representative of the noise and substantially independent of the transitions of the luminance signal that occurs during the sampling interval. Liu, in U.S. Patent No. 4,383,306, entitled CI RCU ITO VARIABLE PEAK CONTROL, describes a system in which the video signal is "filtered" under noisy conditions and in which the detection Noise is made by comparing the signal levels of successive vertical image points. In one example, the signal of three successive vertical lines are put in temporal coincidence (successively delaying the signal for periods of time 1H and 2-H), sampled and the samples are subjected to image analysis for the presence of noise of impulse. Roader et al, in U.S. Patent Serial No. 4,684, 989 entitled SIGNAL BACKGROUND RU DETECTOR, describes a system for calculating noise that includes circuits for producing difference samples corresponding to signal differences between redundant intervals recurrent signal. A number of such difference samples is averaged, and some of the difference samples contributing to each average are subtracted from the averages. The magnitude values are extracted from the differences between the averages and the difference samples and a predetermined number of the magnitude values are averaged to produce the noise calculation signal. The present invention is directed, in a first aspect, to cover the need for a noise detector that avoids the complexities of image analysis and provides a solid and reliable indication of noise. The noise detection apparatus according to the invention comprises means for deriving a discontinuity component from an input video signal.; means for measuring a phase angle of the discontinuity component relative to a phase reference signal provided thereto; and means for deriving a noise inductive signal from the phase angle measurements. A desirable application of the principles of the invention includes a source for providing an input signal having a periodic component and a variable oscillator for generating an oscillatory signal. Means are provided for sampling the input signal at instants determined by the oscillatory signal to provide samples of the periodic component of the input signal. An arithmetic processor, which responds to the samples, generates an angular phase error signal to phase-lock the oscillatory signal of the variable oscillator to the periodic component of the input signal, and a signal indicating noise is deduced from the signal of angular phase error. The invention is illustrated in the accompanying drawings, wherein like elements are denoted by similar reference designators and in which: Figure 1 is a block diagram of a television set including the invention; Figure 2 is a detailed block diagram of an inhibiting counter suitable for use in the example of the Figure 1; Figure 3 is a detailed block diagram of a discontinuity sample accumulator suitable for use in the apparatus of Figure 1; Figure 4 is a detailed block diagram of a rectangular to polar coordinate converter, suitable for use in the apparatus of Figure 1; Figure 5 is a detailed block diagram of a limiter suitable for use in the apparatus of Figure 1; Figure 6 is a phase diagram illustrating certain aspects of the operation of the example of Figure 1; and Figure 7 is a table illustrating the operation of the rectangular to polar coordinate converter of Figure 4. Figure 1 illustrates a television set 10 showing the invention, including a video source 12 for providing a video signal S1 and a video signal display and processing unit 14 for displaying the video signal. For the television receiver applications, the source 12 may include one or more baseband video inputs and suitable switching for selection of plural video input signals. For TV monitor applications the tuner can be omitted. The display and processing unit 14 may be of conventional design including, for example, chrominance and luminance processing circuits, an exhibitor (e.g., a kinescope or a liquid crystal display device) and suitable display driver circuits. To simplify the drawing, the details of color and sound processing are omitted. The baseband video signal S1, provided by the source 12, is converted to a digital signal S2 for application to the video display and processing unit 14 by means of an analog-to-digital (A / D) converter 20 in a circuit of digital phase coupling 16 (indicated with dashed lines) showing the invention. The noise indicating signal (BO, B1) is applied to a control input of an image enhancement processor 18 which is coupled to receive a video signal S3 from the display processor 14 and to provide an improved video signal S4 of Return to the display processor for display. The purpose of the processor 18 is to improve one or more parameters of the displayed image and to vary the improvement as a function of the noise level as indicated by the two-bit noise indicating signal (BO, B1). For this purpose, the improvement processor 18 may be of conventional design such as the previously described systems. It should be remembered that the Shellard system provides a desirable reduction in video bandwidth as the noise level increases. The Liu and Troiano systems apply "filtering" under poor signal-to-noise ratio conditions, and the Cochran system uses the noise signal to control the chrominance signal and video peak level. Another useful application of the noise signal would be to control the degree of noise reduction applied to video signals. It is evident that there are many other suitable applications for the noise level indicating signal (BO, B1) of the present invention. The digital phase lock circuit 16 comprises the analog to digital (A / D) converter 20 to which the video signal 51 is applied and that supplies the converted video signal (digital) 52 to the display and processing unit 14, as mentioned above. A phase-locked sampling clock signal S5 of four times the frequency of the color subcarrier (4Fsc) is provided to the D / A converter 20, to a discontinuity accumulator (or "quadrature phase detector") 22 and to a timing unit 24 by a voltage controlled oscillator 26 The timing unit 24 is synchronized with the "master clock" signal (S5) provided by the VCO 26 and with deflection timing signals DF L of the video display and processing unit 14., in order to generate a number of timing signals for the phase-locked circuit 16, including horizontal synchronization (HS), vertical synchronization (VS) and discontinuity gate signals. The discontinuity gate signal BG, the clock signal 4Fsc and the sampled video source S2, are applied to the discontinuity accumulator 22 which searches and totalizes the even and nons samples of the signal S2 that occur during the discontinuity interval in two groups of samples. This includes an in-phase group of X samples (occurring at discontinuity peaks) and a phase-squaring group of Y samples (occurring at zero-discontinuity crossings). The numbers X and Y represent the coordinates of the discontinuity vector in a Cartesian coordinate system (rectangular). An exemplary accumulator is shown in Figure 3 and is described below. The X and Y coordinates of the discontinuity vector are then applied to a rectangular to polar coordinate converter 30 which converts the XY coordinates of rectangular to polar coordinate forms (R, f) having a term of magnitude R and a term of phase angle f. A direct approach to providing this conversion would be to apply the values of X and Y to the address entries of a read-only memory (ROM) programmed with the corresponding values of radius and angle. However, such a configuration would require a relatively large memory. A better approach, which eliminates the need for a large memory, would be to calculate the angles using trigonometric approaches of sine, cosine or tangent. Figure 3 is an example of a coordinate system converter of this type (rectangular to polar) and is discussed in detail below. The term of magnitude R provided by the polar converter 30 is applied to a discontinuity detector 32 which emits as output an signal S8 denoted "WHITE YN EGRO" at an input of a discontinuity jitter processor 40, when the signal S 1 video does not include discontinuity component thus indicating a black and white (monochromatic) image. Two additional signals generated by the polar converter 30 are a NON DISCONTINUOUS signal S6 and a SENDER S7 signal, both of which are applied to the respective inputs of the jitter processor 40. The "NO DISCONNECT" signal is generated by a second discontinuity detector that is located in the polar converter (and shown in Figure 4) and detects the absence of individual discontinuities of the video signal S2. The jitter processor needs this information to inhibit processing during the selected lines of a color video signal. For example, discontinuity is not present during certain lines of the vertical interval (for example, lines 1-9 when vertical synchronization is present). The individual discontinuities may also not be in a color video signal during the active video ranges due, for example, to loss of signal due to magnetic tape exclusions, noise or the like.

In brief summary, there is a special need for two discontinuity detectors in the noise detection system of the present invention. One of these detectors (32 in Figure 1) is provided with a relatively long time constant or response speed (e.g., one field or more) to identify that the black and white (monochromatic) have no discontinuity component. This detector inhibits the noise detection system for all monochromatic video input signals. The other discontinuity detector (432, 436 in Figure 4) is provided with a relatively short time constant or response speed (e.g., a time line) to identify missing discontinuities in a line-by-line basis. For the particular rapid discontinuity detector shown in Figure 4 (and discussed below) a comparator 432 makes an essentially instantaneous determination if the magnitude of the discontinuity vector (signal L, the largest of the X and Y coordinates) is above or below a threshold value set by a threshold source "Non-Discontinuity" 436. In a color video signal, some discontinuities are always missing, such as lines 1 -9 of the vertical interval, and some are occasionally missing, due to tape or noise cancellations. To achieve an estimated estimate of noise in a color video signal, the missing discontinuities are detected and used to provide an operation modification of the jitter processor 40.

As indicated above, the polar converter 30 also produces a signal called "OCTAIN" to the jitter processor 40. This signal identifies which of one of the eight octants of forty-five degrees occupies the discontinuity vector angle, relative to the reference phase of the VCO 26. Figure 6 illustrates the octants and the table in Figure 7 lists the binary three-bit code identifying each 45-degree octant. As for the phase lock circuit, the octant information is used to make an arc approach tangent to the discontinuity angle as will be explained. The octant information, in the present invention, also serves an additional purpose unrelated to the angle calculation. Specifically, the octant information in the present invention also serves to inhibit the processing of certain phase angles from the noise calculation. As an example, the "OCTANT" signal (S7) inhibits processing in the fluctuation processor 40 for discontinuity angles in the octant of 45 degrees from 135 degrees to 180 degrees and in the octant of 45 degrees from -135 degrees to 180 degrees (Octants 3 and 7, respectively). This prevents erroneous measurements of video noise in the presence of certain anti-copy encoded video signals. An anti-copy encoded video signal is one whose portions of the video signal are intentionally altered in a manner that makes video recording of the signal difficult. An "anti-copy" system of this type inverts the discontinuity phase by four of each video line. The advantage of this aspect of the invention is that by inhibiting the processing of the discontinuity phase noise signal in the two octants adjacent to 180 degrees, the anti-copy encoded discontinuity signal in the two octants adjacent to 180 is prevented. degrees interfere with the measurement of discontinuity fluctuation of video noise. The phase 0 angle signal (signal S9), produced by the polar converter 30, is used for two purposes in the present invention, namely (i) for noise detection in the video signal S1 and (ii) for phase-locked the VCO 26 to the discontinuity component of the video signal S1. Specifically, the phase 0 signal provided by the converter 30 is applied to an adder 41, a frequency error detector 42 and a hook detector 44. The output of the latch detector 44 is applied to a switch 46 so that it couples the frequency error output of the detector 42 to another input of the adder 41 when the latch detector indicates that the system is not latched. The frequency error detector 42 measures the rate of change of the phase 0 signal from line to line and is, essentially, a differentiator and can be implemented by storing the phase of a previous line in a latch and subtracting the previous and current phase values to obtain the derivative with respect to time. Since the phase derivative with respect to time equals the frequency, the output of the frequency error detector is proportional to the frequency error when the system is not latched. In this out-of-hook condition, the latching detector 44 enables the switch 46 to sum the frequency error signal S 10 to the phase angle signal S9 in the adder 41. This "increase" of the phase angle signal when the circuit is out of engagement has been found to desirably improve the speed of the phase lock. However, once engaged, the latch detector 44 opens the switch 46 by removing the frequency error signal S10 from the adder 41 and subsequently the phase control is only by the phase angle signal S9. The output of the adder 41, as mentioned above, comprises the discontinuity phase angle signal S9 when the system is engaged (switch 46 open) and comprises the sum of S9 and the frequency error signal S10 when the system * is out of hook. The output signal of the adder S17 is applied to a limiting circuit 50 which provides limitation and separates the limited phase angle signal in its sign S 1 1 (positive or negative) and its magnitude S12 (the unsigned angle) and these signals S1 1 and S12, respectively, are applied to a binary rate multiplier 60. The purpose of the binary rate multiplier 60 is to generate current pulses to charge and discharge a capacitor in the circuit filter 62, connected to the multiplier 60 in order to control the oscillation frequency of VCO 26. The number or output of current pulses is proportional to the magnitude of the phase angle signal f. For example, when the sign signal S1 1 is positive, the binary rate multiplier 60 generates positive current pulses (signal S13) to charge the circuit capacitor and increase the VCO frequency. Conversely, when the sign S 1 1 is negative, the multiplier 60 generates negative current pulses (signal S 14) to discharge the circuit capacitor and decrease the VCO frequency. In latching, the magnitude of the phase angle 0 approaches zero and only enough pulses are produced to maintain a latching condition. The reason for limiting the phase 0 angle signal in the limiter 50 is to prevent large frequency or phase errors from generally influencing the operation of the circuit. An additional function provided by the limiter 50 is to provide an indicator signal ("LIMITATION") S15 to the jitter processor 40 which indicates when the limiter 50 is in a limiting condition. Thus, the "limiting" signal means that the system is engaged and that the discontinuity phase angle is greater than a predetermined limiting value or minimum. Under these conditions, the magnitude signal S 12 is limited, thus limiting the charge or discharge currents for the filter of the circuit 62. An exemplary "limiting" value when the system is engaged is a phase angle of approximately 3.5 degrees. When unhooked, the level of limitation is increased (by a factor of ten or more) to improve the speed of reacquiring the hitch. An appropriate implementation of the limiter 50 is shown in Figure 5 and discussed below. The "limiting" signal S15 provided by the limiter 50 is applied to the discontinuity jitter processor 40. The combination of the limiter 50 and the processor 40, in accordance with an aspect of the invention, provides the function of deriving the signal noise indicator B0. B1 of the phase angle measurements provided by the polar converter 30. In more detail, it should be remembered that the limiter 50 detects phase discontinuity errors that exceed a relatively small angle (e.g., 3.5 degrees) when the system is engaged . The discontinuity jitter processor provides the function of counting the number of lines in a given time interval (e.g., a field or frame) for which the phase angle measurement (f) exceeds the threshold angle of detection (3.5 degrees). From the count, the jitter processor 40 generates and outputs the count or a scale version thereof as the noise signal. In this example, the count of discontinuity phase excursions that exceed the threshold phase angle value and that occur within a field is scaled down to provide a two-bit output signal (bits B0 and B1) which provide four discrete levels of noise indication (for example, 00, 01, 10 and 1 1 in binary). The noise indicating signal is then applied to the image enhancement processor 18, to adjust image parameters displayed by the unit 14 such as contrast, sharpness, bandwidth or noise reduction, as discussed above. Figure 2 is a detailed block diagram of a suitable implementation of the processor 40. Essentially, the processor 40 comprises a non-enveloping inhibitor field rate counter, whose output is scaled down to the two most significant bits (MSBs) to form the noise signal B0. B 1. The processor 40 includes six inputs and two outputs. The inputs 1, 2 and 3 respectively receive the "limitation" signal S15, the "black and white" signal S8 and the "non-discontinuity" signal S6. The inputs 4 and 5 receive, respectively, the two least significant bits "1" and "0" of the octave signal S7 and the input 6 receives a vertical timing signal VS from the timing unit 24. The two outputs 7 and 8 provide the two bits B0 and B1 of the noise reduction signal to the image enhancement processor 18. The processor 40 is implemented, illustratively, by an ascending counter 500, whose output is divided by 16 in a divider 508 and applied to an output latch 510 that provides the noise signal output signal bits B0 and B1. The ascending counter 500 is measured in time by the limiting signal S 15 via the inhibiting gate AN D 502. Each time the limiter 50 indicates a phase angle greater than the minimum value (for example 3.5 degrees when being engaged) the counter 500 It is advanced. The counter 500 is reinitialized once each field by the vertical synchronization signal VS which also encloses the output of the counter in the latch 510. The output of the counter 500 has been "scaled down" or divided by 16 in the divider 508 to provide a more condensed presentation of the noise information. For example, a binary output value of "00" means that the limitation has been carried out less than 16 times during a field. An output of "01" means that the limitation occurred at least 16 times but less than 32 times during a field. An output of "10" indicates that the limitation has occurred at least 32 times but less than 48 times. Finally, an output of "1 1" means that the limitation has been carried out at least 48 times during a field. Conveniently, it has been found that scaling the count down to provide the above four indications of the number of times the discontinuity angle (or "jitter") has exceeded the minimum acceptable phase error (e.g. about 3.5 degrees) provides a number useful for noise level indications. If a finer resolution is desired, the output of the counter 500 can be divided by a number less than 16. The maximum resolution can be obtained by taking the "C" count of the counter directly as the noise signal. In order to prevent the counter from "wrapping" or "overflowing" in cases where a large number of errors are made, the split count is compared by a comparator 512 with a numerical value of "3" (binary "1 1" ). This means that a count of 48 has been achieved in a field and the output of the comparator, being applied to an inhibitor input (signified by an open circle) of the AND gate 502, avoids the subsequent count during the field. The foregoing is a convenient aspect of the invention because it avoids indications of "false false" noise. For example, suppose that a very noisy video signal advances the 500 counter beyond its module. Then the counter output, at the end of a field, can be any number. If that number is less than 16, then the noise signal will equal "00", meaning a relatively noise-free condition when, in fact, it is totally the opposite. Accordingly, the comparator 512 avoids the "wrapping" of the counter 500 and thus ensures that the counter 500 can not count beyond a value of "48" regardless of how many limit indications the limiter 50 provides. The above discussion of the "non-envelope" or overflow protection aspects of meter 500 illustrates one of four inhibition conditions for the meter. The other three "inhibition" conditions for the 500 meter are (i) WHITE AND BLACK, (ii) NO DISCONNECT, (iii) SECRET MASTERING R. It must be remembered that the monochromatic video signals do not have discontinuity and therefore to avoid the erroneous noise calculations the discontinuity detector output (Signal S8) of the long time constant (field interval) which means that the signal of video is monochromatic is applied (in terminal 29 to a second input of inhibition of the gate AN D 502. (The inhibition inputs are signified in the drawing by open circles in the gate inputs.) The signal of NO DISCONTI NUI DAD S6 provided by a short time constant discontinuity detector is also applied at input terminal 3 to another inhibit input of gate AN D 502 to avoid counting during the vertical synchronization interval (when the discontinuity is not present) and to avoid counting defective discontinuities in another way (eg missing discontinuity due to tape oxide exclusions, et. c.) that would otherwise produce an inaccurate count. The last inhibition condition of the counter 500 is applied for discontinuity angles within a sector extending 45 degrees on either side of 180 degrees corresponding to the octants 3 and 7 (shown in Figure 6) of the phase angle of discontinuity . This is referred to in the drawing as "sector masking" and its purpose, as previously explained, is to exclude all discontinuities from being counted which are likely to be intentionally reversed by anti-copy video coding techniques. As mentioned above, one technique of this type reverses the discontinuity phase for 4 out of 20 video lines. Conveniently, excluding inverted lines in the measurement phase preserves the integrity of the noise calculation.

The "sector mask" 504 (indicated with dashed lines) comprises an AN gate D of two inputs 56 which receives the two least significant bits ("1" and "0") of the octant signal S7. The full octant code is shown in Figure 7. This code identifies the sectors shown in Figure 6 and determines the arithmetic processing used in the polar converter 30 to convert the quadrature samples X and Y into polar coordinates R and f. As seen in the code table, to cover a sector of 180 degrees plus or minus 45 degrees, you only need to inhibit the 500 counter for two octants, namely the octant 3 and the octant 7. As is evident from the table binary three-bit code, the two least significant bits of octants 3 and 7 are both logical "values". So that by putting the two least significant bits of the octant code in AN D, gate 506 will be enabled any time the octant code is either "3" (01 1 in binary) or "7" (1 1) 1 in binary). Therefore, the output of the gate 506 is connected to an inhibiting input of the gate 502 where the count is inhibited each time the phase angle of discontinuity is in the "excluded" sector (octants 3 or 7). Figure 3 is a detailed logic diagram of a suitable implementation of the discontinuity accumulator (or quadrature phase detector) 22 of Figure 1. When making a brief review, the function of the accumulator is to sample the discontinuity four times the frequency of the color subcarrier (4Fsc) thus producing a sample for each 90 degrees of the discontinuity signal. When the circuit is engaged, the pairs occur in the peaks of discontinuity thus forming the "X" or "in phase" samples and the nons samples occur at the junctions of the discontinuity axis to form the samples "Y" or "quadrature phase". Taken together, these two values, X and Y, represent the discontinuity vector in a rectangular coordinate system. The function of the accumulator 22 is to perform the arithmetic operations necessary to adequately search and totalize the samples including the removal of the direct current compt (DC) or "pedestal" value (for example, around the black level) from the samples of discontinuities produced by the A / D convert 20. In more detail, the video signal samples produced by the A / D converter 20 are in the form of unsigned binary. Since the discontinuity appears during the drag portion of horizontal synchronization, it will have a pedestal or DC value around the black level. The exact value may be unknown or may vary with the signal source. In order to remove this compt from the discontinuity measurements, the video signal S2 of the A / D converter 20 is converted first of unsigned binary to a form of two complements by inverting the most significant bit (MSB) by means of an inverter 300 This change in the rhythmic form facilitates the addition and subtraction of the samples in the accumulator. The samples of two add-ons of the inverter 300 are then applied to an adder / its transducer 302 comprising an exclusive OR gate 304 and a full adder 306. The selection of the addition or subtraction modes is controlled by a clock signal Fsc in the color subcarrier regime which is a quarter of the 4-Fsc clock rate of the VCO 26. The adder / subtractor output is stored in two bolts connected in series 312 and 314 and fed back to the adder summing input. As the bolts in the 4 Fsc sample rate change and change from addition to subtraction every two sample periods using the Fsc clock, the in-phase "X" samples will be accumulated in bolt 312 and the Quadrature phase samples "Y" will be accumulated in latch 31 4. As the adder / subtractor alternates between admission and subtraction every two sample periods of the 4 Fsc clock, the "X" samples are added and subtracted alternately to produce the accumulated value "X" on the 312 lock. The alternative addition and subtraction of the X-value samples (for example, + X0, -X2, + X4. X6, + X8, -X1 0 etc.) results in the cancellation of the DC component of X. The continuity component of X is not canceled because the "sign" or discontinuity polarity alternates every two samples and thus add the discontinuity samples. Accordingly, the discontinuity samples are accumulated and the DC component or pedestal portion of the samples implemented is canceled. The same result occurs for the samples Y. To confide the samples X and Y to only discontinuity, the output of the adder 306 (a sum of 1 3 bits) is applied to the latch of the accumulator 312 via a gate of d iscontin uity 31 0 that is habituated for 48 of the 4-Fsc clock periods during the discontinuity interval of each line. A typical discontinuity (NTSC) will have 8 complete cycles corresponding to 32 samples of the 4-Fsc clock. The discontinuity gate is made substantially more widely than the discontinuity width to ensure the capture of all discontinuity cycles in the case of substantial timing errors in the video source. At the end of the discontinuity gate period (48 samples of the 4-Fsc clock) a closed discontinuity gate signal (provided by the timing unit 24) is applied to the latches 316 and 31 8 which store the vector data of accumulated discontinuity X and Y for the rest of the line during which time the information is converted to polar form, is passed through the limiter 50 and the calculation of ru is made counting the number of times the limit of the limiter, as previously explained. Figure 4 is a detailed logic diagram using the polar converter 30 that provides the functions of (i) rectangu lar to polar coordinate form (magnitude and angle) for the discontinuity vector, (ii) identification of the specific octante in which the continuity vector is and (iii) generation of the "NO DISCONTI NUI DA D" signal. To provide polar conversion, the X and Y coordinates of the accumulator 22 are applied to respective inputs of a comparison and division circuit 410 via complementing circuits of one, comprising an inverter or complementer (400 or 403) and a multiplex switch ( 402 or 404) controlled by the sign bit of the input signal. This converts the complement coordinates of the two to binary without sign to facilitate comparisons and division of subsequent magnitude. For example, when the sign of X is "0" (bit 13, indicating a positive number), the remaining 12 bits of the magnitude of X are passed directly to the input X of circuit 410 via multiplexer 402. If, however, , the sign of X is negative (binary "1", indicating a negative number), then the multiplexer switch 402 couples the 12 magnitude bits complemented to the input X of the circuit 410 thus converting X to binary form without sign. The magnitude bits (for example, 1-12) of the input signal Y are similarly converted to unsigned form under the control of the sign bit Y (bit 13) for application to the Y input of the division and comparison circuit 410 Internally, the comparison and division circuit 410 includes a magnitude comparator to identify the largest of X and y and produces this value as an "L" (ie, "major") signal as output. The "L" signal is used to represent the "MAG NITU D" of the polar discontinuity vector S 12 for application to the discontinuity detector 30. The polar magnitude signal "L" is also applied to a NO-DISCONNECT UI detector. Short time constant DAD comprising a comparator 432 comparing the "L" signal with a reference level signal provided by a threshold source of NO DISCONTINUITY 436. For purposes of general system adjustment, the threshold source 436 is programmable to provide a number of reference values. Illustratively, the discontinuity reference values of 16, 32, 64 and 128 are available. In terms of I RÉ signal levels, these correspond to discontinuity amplitudes of IR levels É of 1, 2, 4 and 8. The comparator compares the "L" signal (which is the "largest" of the X vector components). and Y), with the discontinuity reference level provided by the source 436 and outputting the NO-DISCONTINUITY signal S6 when the magnitude signal "L" is smaller than the discontinuity reference signal R. As mentioned above, the time constant of this discontinuity detector is relatively short because the detection occurs on a line-by-line basis compared to the long-time constant discontinuity detector 32, which has a field-time time constant for detecting signals from monochromatic video The signal NO-DISCONTIN U SAD S6, as indicated above, inhibits the calculation of the video noise level for lines with missing discontinuities such as vertical synchronization lines and lines with discontinuity exclusions. The identification of specific octants of the discontinuity vector is provided by an octagonal identification signal of three S7 bits. The most significant bit comprises the sign bit of the input signal "Y". The second most significant bit B1 comprises the sign bit of the input signal "X". The least significant bit LSB comprises the exclusive OR of the sign bit of the input signal "X" with the output of the comparator of magnitude X <And in circuit 410. Figure 7, as indicated above, identifies 0-7 octants in terms of their three-bit code. Summarizing, the two lower bits of the octant code are formed in AND gate in the 504 sector mask to exclude noise calculation discontinuities close to 180 degrees (+/- 45 degrees) to avoid errors of the video material of protected tapes with anti-copy of the type in which the discontinuity is periodically inverted. Now considering the details of the polar conversion function of the converter 30, this conversion is based on an approximation that for small angles (eg, less than 45 degrees) the tangent arc of the angle defined by the rectangular coordinates X and Y is approximately equal the smallest of X and Y divided by the largest of X and Y. The circuit 410 includes a magnitude detector, as previously explained, which determines the relative sizes of X and Y. This detector is used internally to perform a division of the smallest of the largest signal (meaning "S / L") and this number is used to represent the 7 least significant bits of the polar angle that covers a range of 45 degrees. To cover a complete circle (360 degrees) the converter 30 adds or subtracts angles of 0, 90, or 180 degrees depending on the octant in which the discontinuity vector is. The octants are determined as described above and the arithmetic of deriving the full value for each octant is shown in Figure 7. In more detail, the arithmetic calculations of Figure 7 for the discontinuity vector angle are made by the converter 30 by a complete adder 420 that by means of exclusive gate OR 414 and inverter 422, is capable of either addition or subtraction. Two multiple switches are provided, 416 and 418, which provide the numerical equivalent of the set angles of 0, 90 and 180 degrees to an input of adder 420. By selecting the appropriate set angle, and combining it arithmetically (for example by adding or subtracting it) ) with the tangent act approximation of the discontinuity angle (the S / L signal), any discontinuity angle in 0-3 octants can be represented. The remaining octants 4-7 are calculated by inverting the corresponding octant of 0-3 octants. This is carried out by the exclusive gate 428 connected to the output of the adder 420. As an example of calculating the angle of discontinuity, suppose that the vectors X and Y are both positive and that X is greater than Y. This defines a discontinuity vector in the octant "0" that is between zero and forty-five degrees, and whose angular value is approximately equal to Y / X (the smallest divided by the largest). Since X is positive, the multiplexer switch 416 will select the "zero" constant as an output that corresponds to zero angular degrees. Since X is assumed to be greater than Y, the comparator signal X < And it will also be zero thus making the multiplexer switch 418 select the output of the switch 416 which is zero degrees, as mentioned above. The adder 420, by this condition adds a constant of zero (from switches 416 and 418) to the tangent arc approach (S / L) of the comparison and division circuit 410 and as the sign of Y is zero (Y is positive ) the exclusive output OR gate 428 will pass this value (+ S / L) as the discontinuity phase angle S9. For different octants, adder 420 adds constants other than S / L, as shown in the inner striped circle at the adder output and also shown in the table in Figure 7. For example, for a discontinuity vector that is in octant 1, the full vector angle is the value of S / L subtracted from the 90 degree reference provided by switch 416. In octant 2, the value of 90 degrees is added to the value S / L and in the octant 3, the discontinuity vector is determined by subtracting the S / L value of 180 degrees. For the remaining octants 4-7, the value of the discontinuity vector is found exactly for the corresponding octants 0-3, except that the output of the adder 420 is inverted by the exclusive OR gate 428 thus inverting the sign of the angle of discontinuity phase indicated.

Figure 5 is a detailed logic diagram of the limiter 50. This unit converts the discontinuity vector error signal (e.g., phase plus frequency signal S17) into magnitude and sign format and provides dual-mode limiting action. Limit the magnitude of the error signal to "7" when the system is engaged and to a level of "127" when the system is not engaged. The binary values of 7 and 127 correspond, in terms of angular degrees of discontinuity to approximately 3.5 degrees and 63 degrees, respectively. Conveniently, providing a wider limiting angle before the limitation for the non-blocked condition is reached provides an additional improvement in the pickup speed of addition in addition to the speed improvement provided by the frequency term (S10) which is added to the phase term (S9) by adder 41 when the circuit is in the non-latching condition. In more detail, in the limiter 50 the phase signal plus frequency S 17 of the adder 41 is converted from the complement form of the two to unsigned binary by a complementing of one 502 and a multiplexing switch 504. The switch 504 is controlled by the sign bit of the input signal to select the 14 bits of magnitude as an output (S50) when the sign bit is zero (indicating a positive number) and select the completor output of one 502 when the bit of sign is "1" (meaning a negative number) thus producing an unsigned binary output signal S50. The sign bit of the input signal (bit 15) is also stored in a latch 510 in order to provide the sign bit signal S 1 1 for use by the binary rate multiplier to determine the polarity of the current of the signal. output (current creation or current suppression) to the circuit filter. The unsigned binary phase angle signal S50 is applied to a comparator 508, of which a multiplex switch 512 for selecting the last seven least significant bits of signal S50 (provided by truncator 605) when signal S50 is greater than a value of "127", otherwise, the switch 512 selects a constant value of "high limit" of "127" as the output. In this way the circuit portion provides a first level of limitation of the discontinuity phase angle signal at a level of "127". If, for example, the discontinuity phase angle is any value less than 127, then the comparator 508 will select the truncated signal S54 as the output signal S56 of the switch 512. Conversely, any discontinuity angle value greater than 127 will cause the switch 512 to select the reference value of "127" as the output signal S56. A second stage of limitation of the signal S56 is provided by a comparator 514, a gate AN D of inhibition 516 and a second multiplex switch 518. Specifically, the comparator 514 compares the signal of discontinuity angle S56 with a reference level of "7" and provides a high output if the signal S56 is greater than the value of 7. (Note, the binary "7" corresponds to an angle of approximately 3.5 degrees). The gate 516 receives the output of the comparator 514 and is enabled by the hook detector 44 when the output of the hook detector is low meaning a "hooking" condition of the circuit. If the input signal is less than a value of "7", and the circuit is latched, then the switch 518 will select the signal S56 as the phase angle of discontinuity. If the input signal is greater than 7, and the circuit is latched, gate 516 will cause switch 518 to select a fixed limiting value of "7" as an output, thus limiting the discontinuity phase angle to approximately 3.5 degrees when the circuit is engaged. As the signal of magnitude of discontinuity S58 has no sign, the limiting angle can be plus or minus 3.5 degrees as the discontinuity phase can be advancing or delaying the reference phase (note that the reference phase is the output of the VCO 26 divided by 4, which is the frequency of the Fsc subcarrier ). However, if the circuit is not latched, gate 516 will cause switch 518 to select signal S56 (which has a limitation level of 127) as the output discontinuity vector angle. A latch 520 is provided to store the discontinuity vector angle signal S12. Making a brief summary, gate 516 provides the "limiting" output signal S15 to processor 40. This signal will be high if the circuit is engaged and the discontinuity angle is greater than the reference value of "7" corresponding to a Discontinuity phase angle of approximately 3.5 degrees. The "limiting" signal will be low if the circuit is not latched or if the discontinuity phase angle error is below the value of "7" which corresponds approximately to a discontinuity phase error of 3.5 degrees. The processor 40, as previously explained, records the number of times the limitation has been carried out when the circuit is engaged to develop the signal indicating the video noise level (B0.B1).

Claims (12)

1. CLAIMS 1. Apparatus for detecting noise, characterized by: a signal source for providing a color video signal; an angle measurement circuit for measuring a phase angle of such a color video signal relative to a phase reference signal provided thereto; and an output circuit for deriving a noise signal from the phase angle measurements. Apparatus as indicated in claim 1, further characterized in that the output circuit includes: means for counting the number of lines in a given time interval for which the phase angle measurement exceeds a first angle; and means for outputting the account or a scaled version thereof as the noise signal. Apparatus as set forth in claim 1, further characterized by: an inhibitor circuit for excluding phase angle measurements from said count falling within a predetermined range of angles disposed approximately at an angle of 180 degrees. 4. Apparatus as set forth in claim 1, further characterized in that the measurement circuit further includes: quadrature sensing means for applying a discontinuity component of said color video signal and the reference signal to respective quadrature phase detectors to develop quadrature and phase output signals, X and Y, respectively; and rectangular to polar conversion means for converting said quadrature and phase phase output signals, X and Y, to a phase angle indicating signal for application to the output circuit to derive said noise indicating signal. Apparatus as indicated in claim 1, further characterized in that the measurement circuit further includes: sampling means for generating samples of said discontinuity component at four times the frequency of said reference frequency; an accumulator to search for said samples in order to provide two related groups of sample quadrature; and a polar converter for forming, from each two groups of samples, a phase angle indicating signal for use in deriving said noise signal. Apparatus as indicated in claim 1, further characterized in that the output circuit comprises: a counter circuit for counting phase angle measurements that fall within a given range of values within a given time interval; and means for outputting a signal representative of the count as said signal indicating noise. Apparatus as indicated in claim 1, further characterized by: a pair of sensor circuits for detecting the absence of discontinuities in a line basis per line and in a field basis per field, respectively; and an inhibition circuit that responds to said sensor circuits to inhibit angle measurements in the absence of discontinuities. Apparatus as set forth in claim 1, further characterized by: an inhibitor circuit for excluding phase angle measurements falling within selected octants of the derivation of said noise signal. 9. Apparatus as indicated in claim 1, further characterized by: means for inhibiting said measurements for phase angles near zero degrees; means for inhibiting said measurements for phase angles close to 180 degrees; means for inhibiting said measurements missing components of said discontinuity components; and means for identifying monochromatic ranges of said video signal and for inhibiting such measurements during said monochromatic ranges. 10. Apparatus as set forth in claim 1, further characterized by: means for modifying a parameter of said color video signal as a predetermined function of said noise indicating signal. 1 1. A phase-locked circuit, characterized by: a source for providing an input signal having a periodic component; a variable oscillator to generate an oscillatory signal; means for sampling said input signal at times determined by such oscillatory signal to provide samples of such periodic component of the input signal; means responsive to such samples for generalizing a phase error signal to phase-lock such oscillatory signal of said variable oscillator to the periodic component of the input signal; and means for deriving a signal indicating noise from the phase error signal. 12. A phase-locked circuit, as indicated in claim 1, further characterized in that said bypass means comprise: a detector for detecting values of such a phase error signal that exceeds a given phase angle; and a counter for counting the number of detected error values occurring within a given time interval.