MXPA96001881A - Automatic converter of image examination format with switching without cost - Google Patents

Abstract

The present invention relates to an adapter scan format converter in an encoder / transmitter of a video signal processing system such as a high definition television (HDTV) system, as a function of what format is desired for coding and transmission via an output channel. Similarly, a receiver, a received scan format is automatically converted to a desired format for display as necessary. For example, a received interlaced signal (I) will be automatically converted to a progressive format (P) to be compatible with a progressive scan display device. A received progressive signal will be passed to the display device without format conversion. The automatic scan conversion is performed seamlessly so that, for example, the conversion between the progressive main television program material and the interlaced commercial material is produced without artifacts and is essentially invisible to an observer.

Description

Automatic Image Scan Format Converter with # Seamless Switching Field of the invention This invention relates to the field of digital image signal processing. In particular, this invention relates to a line scan converter system suitable for use with high definition image signal processing such as the high definition television system proposed for use in the United States of America. > BACKGROUND OF THE INVENTION Recent developments in the field of video signal processing have produced digital high-definition television signal transmission and processing systems (H DTV). A H DTV terrestrial transmission system recently proposed as the H DTV Grand Alliance system in the States United States uses a vestigial sideband (VSB) transmission format to transmit a stream of data in the form of packets. The H DTV Grand Alliance system is a proposed transmission standard that is under consideration in the United States of North America by the Federal Commission of Communications (FCC) through its City Council Service Committee Advanced Television (ACATS). A description of the H DTV system Grand Alliance as presented to the ACATS Technical Subgroup on February 22, 1994 (draft document) is found in the documents of the National Association of Transmitters of 1994, Documents of the 48th Annual Transmission Engineering Conference, from March 20 to 24, 1994. The H DTV Grand Alliance system supports image information in two frame line scan formats. A 5 format is an interlaced 2: 1 line with a frame rate of 30 Hz. The other is a non-interlaced, or progressive 1: 1 (sequential line) format with a frame rate of 60 Hz. interlaced image shows the following characteristics: ^ u 2200 pixels x 1 125 l image lines (total) 1920 pixels x 1080 image lines (active) The progressive image display shows the following characteristics: 1600 pixels x 787.5 image lines (total ) 15 1280 pixels x 720 image lines (active). The source material to be transmitted to a television receiver can display any format. For example, a television broadcast program from one source may be in progressive form while one or more commercial or other material participant from other sources may be in interlaced form. Summary of the Invention In accordance with the principles of the present invention, it is hereby recognized as desirable to provide an adapter scan format converter in a transmitter as a function of what format is desired to encode and transmit via a exit channel. Likewise, in a receiver, it is recognized as desirable to automatically convert a received scan format to a desired format for display by an associated image display device. In such a case, for example, a received interleaved signal will be automatically converted to progressive form if necessary to be compatible with a progressive scan display device, and a received progressive signal will pass to the display device without format conversion. In accordance with a feature of the invention, the automatic scan conversion is performed seamlessly so that, for example, the conversion between the progressive main program material and the interlaced commercial material, or vice versa, is produced without artifacts and is essentially invisible for an observer. BRIEF DESCRIPTION OF THE DRAWINGS In the drawings: Figure 1 is a block diagram of a receiver and transmitter television system in which the invention can be employed. Figure 2 shows details of a scan format converter system in accordance with the principles of the present invention. Figures 3A and 3B illustrate signal waveforms useful in understanding the operation of the system shown in Figure 2.

Figure 4 shows a portion of the system of Figure 2 with # more detail. Detailed Description of the Drawings In Figure 1, a source 10 of the interlaced video signal "I" and a source 12 of the progressive video signal "P" on a transmitter / encoder of transmitting television provides output video signals to respective inputs of an automatic scanning format converter 14, which operates in accordance with the principles of the present invention. The scan converter 14 will be shown and described in more detail with respect to Figure 2. In this example the television system is a H DTV system of the type proposed by the Grand Alliance in the United States of America as mentioned previously. Video sources 10 and 12 are synchronized with each other ("genlocked"). In this example, only one of these sources is active at the same time, although in some systems both can be active. In the case where only one of the signal sources is active at the same time, the converter automatically selects the input port with the active video signal. If the format of scanning of the active video signal is the same as the desired format for a transmitted video signal, the scanning format of the input video signal is not altered by the converter 14. If the input format is different, the converter 14 automatically converts the format of the video signal from input in order to be compatible with the desired output signal format. The output signal of the scan converter 14 is compressed into data by an M PEG encoder 16, as is known, before being applied to a transport processor 18. The processor 18 formats compressed data of the encoder 16 into data packets, preassign the data packets with header information that identifies the content of the respective packets, for example adds synchronization and other information. The data packets of the transport processor 18 are processed for transmission via a transmission channel 25, by a transmission processor 20. The processor 20 includes data formatting, error coding, buffering, digital-to-analog converter and modulating networks. of RF (radio frequency) for conditioning the video signal for transmission via the channel 25. In a decoder / receiver, the signal of the channel 25 is first processed by a unit 30 including filtering networks and RF tuning, I F networks (intermediate frequency), error and demodulation processing networks, and an inverter analog to digital, for example. An output signal from the unit 30 is processed by a unit 32 that performs the inverse of the operation of the unit 18 on the transmitter. Specifically, unit 32 evaluates the header information to identify the constituent components of the data packet and separates these components (for example, video information, audio and synchronization) for processing by respective circuits. The * > data components of the decoder 32 are decompressed by a decoder M PEG 34, as is known. The M PEG 34 decoder includes an interlaced video signal output port on which an interlaced video signal of 1080 transmitted lines will appear, and a progressive video signal output port on which a 720 progressive video signal will appear transmitted lines. The MPEG decoder 34 also includes provisions for deriving encoded information from the received data stream indicating whether a received video signal exhibits interleaved or progressive form. A television receiver includes an associated display device which may be of an interlaced scan type or a type of progressive scan. These possibilities are illustrated by means of a device interlaced display 38 and a progressive display device 39. A practical receiver will have one but not both display devices.

The receiver's display device receives a signal to be displayed from a 36 format converter (after the processing by appropriate circuits of display exciter and signal conditioning not shown to simplify the drawing). The format converter 36 is programmed with information (for example, by the manufacturer of the receiver or via a locally generated control signal) to indicate the type of the associated exhibition, that is, interlaced or progressive, since in This example assumes that an associated display device is capable of displaying display video information in only one scanning format. Therefore, the format converter 36 is configured to automatically provide a signal of output in a format compatible with the display device, regardless of which of the two video signal formats is received and decoded. If, the display is an interlaced device such as the unit 38, the converter 36 will divert an interlaced video signal received from the unit 34 to the output of the receiver.

^ R) converter 36 without modifying its scan format. If a received video signal is progressive, the converter 36 will automatically detect this by detecting that the progressive output port of the MPEG 34 decoder is active, converts said signal to interlaced form, and provides said signal at its signal output interlaced. Thus, an interlaced video signal will always be provided to an interlaced display f independently of the scan format of a transmitted video signal. Analogous observations pertain to a receiver with an associated progressive display such as the device 39. 20 Figure 2 shows additional details of a scan format converter such as units 14 and 36 in Figure 1. For purposes of the following discussion it is assumed that the converter of Figure 2 corresponds to the unit 36 in the receiver of Figure 1. An input network 42 and an input network 44, 25 respectively receive digital (P) and progressive output signals. digital interleaving (I) of the M PEG decoder 34. Each of the * Input networks include circuits to separate the video component and synchronization components. The synchronization components include a horizontal synchronization component (H), a vertical synchronization component (V), a frame reference pulse (FRP) and a pixel clock CLK. The frequency of the pixel clock is derived from the product of the total number of pixels, the total number of lines, and the number of fields / seconds. The FRP frame reference pulse is a reference signal Wó developed by the MPEG decoder 34. Appears in a prescribed portion of the vertical extinction range, and provides a reference point from which subsequent circuits count clocks of the first pixel of an interlaced field or a progressive frame. The converter 36 also includes an analog input to receive analog color video components R, G, B (or Y, U, V) and associated horizontal and vertical synchronization components H, V. These components can be generated by a recorder video cassette recorder (VCR) or a video camera for example, and they are converted to digital form by an analog-to-digital converter 48. The video outputs of the units 42, 44 and 48 are applied to respective signal inputs of an input multiplexer (MUX) 46. A mode control unit and sync 70, responds to the digital synchronization components H and V, to the pulses of FR P frame reference, and to CLK clocks for source signals * progressive and interleaved, as well as to the synchronization components H and V (H, V RG B) for the analog signal source after conversion to digital form by the converter 48. A control input of the network 70 receives a Output Format Control signal to determine the operating characteristics of the format converter as a function of whether an interlaced or progressive format is desired for an output video signal. This signal can be produced by a local switch setting, and | B > determines whether the output video signal will be interlaced or progressive. This determination can be made by a transmission operator in a transmitter, or a manufacturer of the receiver. The output signals produced by the network 70 include a frame reference pulse FRP (I) for interleaved signals, a pulse of FRP frame reference (P) for progressive signals, an image element fs clock (pixel), a clock of? A fs of half-rate pixel clock, and a Control signal. The Control signal is applied to an output multiplexer 60 to pass either progressive video signal or interlaced to an output, as will be discussed further ahead. The network 70 may include a phase-locked circuit (PLL) network frame and a field-hook circuit of the FRP signals. The pixel clock fs for an interlaced video signal is a 74.25 MHz signal (2200 pixels x 1 125 total lines x 30 Hz field regime). The pixel clock fs for a video signal Progressive is a 75.6 MHz signal (1600 pixels x 787.5 lines total r x 60 Hz frame rate). These pixel clock frequencies are related by a convenient divider ratio of 55/56 (for example, 75.6 x 55/56 = 74.25), and therefore, are easily reproducible. The video information is transferred to the converter system via the A / D unit 48 and the input multiplexer 46, and of the converter system via the D / A unit 62, at full pixel rate fs. The subsystems within the format converter operate in response to the clock of Í fs. ^) The conversion of format from progressive to interlaced (720 lines to 540 lines) is carried out by a Conversion Path Pl including the input multiplexer 46, a horizontal and vertical prefilter 54 that performs a 4: 3 decimal ratio, a multiplexer of output 60 and a digital-to-analog converter 62. 15 The conversion of interleaved to progressive format is performed by a Conversion Path lP including multiplexer 46, a line bent de-interleaver 50, a horizontal filter and post-filter network. vertical 52 which performs a 3: 2 decimal ratio, output multiplexer 60 and converter 62. The techniques for performing the interpolation and the decimal ratio are well known. In a bypass mode where the scanning format of an input signal is not changed in the output, the video signal is passed via a Bypass Path including the input multiplexer 46, the output multiplexer 60 and the frequency converter. digital to 25 analog 62.

At the output, the frame reference pulses FR P and the video information are respectively converted to analog sync components H, V and analog color video components R, G and B by the converter 62. Then, these components are passed to known circuits of video signal processing and synchronization and display exciter. The output port 64 is used only in an encoder of encoder / transmitter format, for example, unit 14 in Figure 1, to pass digital information to the MPEG encoder 16. The digital-to-analog converter 62 includes a Programmable Logic Network (as it is known) with a counter to generate the output synchronization components H and V. For this purpose the FRP is applied to a reset input of the counter, and the Programmable Logic Network operates in response to the fs clock and an output format selection signal (derived from the Control signal) to produce the H and V output synchronization components after conversion to the analog form. In the case of the conversion of interlaced to progressive video, via the conversion path l-P, the input multiplexer 46 receives a digital video signal, for example, from the units 42 or 48, at the pixel clock rate. Then, the multiplexer 46 generates an output signal at one half of the input data rate. Specifically, the pixel data arriving in a time sequence A, B, C, D, ... are converted to a data stream of two pixels in parallel, for example, A, B then C, D and so on. successively. This data stream is provided to a * input of de-interleaver unit 50, which also receives an FRP synchronization component from unit 46 De-interleaver unit 50 operates as is known by storing odd field lines 1, 3, 5, ... and even field lines 2 , 4, 6, ... A video frame is generated by creating additional lines in each field so that an output signal of the unit 50 represents a progressive video frame constituted by lines 1, 2, 3, 4, 5 , 6, ... and so on. This de-interlacing operation flü could be as simple as repeating lines, or as elaborate as estimating motion in each field for each of the color signal components R, G, B, and using motion derived vectors to adjust coefficients in several directions in order to produce additional pixels as is known.

In the latter case, unit 50 finds the largest movement vector among the three components of color RG B. This vector is used by interpolation networks to generate new values of pixel of the derived line. So, unit 50 generates an output signal with twice as many lines as the input signal, it is say, 1080 lines derived from the 540 lines in each field. The horizontal and vertical postfilter 52 subjects the output video signal of unit 50 to a 3: 2 decimal ratio in the horizontal direction to generate 1280 pixels of output of 1920 input pixels. In the vertical direction, the filter 52 provides decimally the output signal of unit 50 by 3: 2 to generate 720 output lines of 1080 input lines This progressive signal is routed via the multiplexer 60 and the digital-to-analog converter 62 to subsequent display and signal processing circuits. In the case of conversion from progressive to interlaced via the Conversion Path Pl, an output signal from the multiplexer 46 and the FRP component are applied to a horizontal and vertical pre-filter 54. The filter 54 subjects the video signal to interpolation 2 : 3 in the horizontal direction to generate 1920 output pixels of 1280 input pixels. In the vertical direction, the filter 54 subjects the video signal to a 2: 3 decimal ratio to generate 1080 output lines of 720 input lines. The interleaved output signal of the unit 54 is routed via the multiplexer 60 and the digital-to-analog converter 62 to subsequent signal processing and display circuits. In the case of both trajectory processing P-l and l-P, the time of the FRP at the outputs of units 52 and 54 remains fixed. The format converter network continuously produces video information in the selected format regardless of the input signal format. The output multiplexer 60 includes a frame memory network (delay) in the Bypass Trajectory to compensate for the signal processing delays associated with the P-1 conversion path and the I-P conversion path. This frame delay also facilitates seamless switching between video signals of different format. The commutation It happens in the borders of the painting. The frame delay allows the input video to randomly switch between the two formats and still provide an output signal in the desired format in a direct current without shooting any frames. If the format converter is configured to provide a progressive scan output, the input signal format can change between the progressive and interlaced format without interrupting the signal data flow or losing video information in the output signal of the converter. Format. This feature allows, for example, that a television commercial be in progressive scan format while the material of the main television program is in interlaced scanning format. Both types of video information, when merged into a similar scanning format using the switching feature without format converter sewing, can be transmitted and received in real time as a continuous stream of video information. This characteristic will be shown and discussed in relation to * with Figures 3 and 4. Consider the case when the video signal format of The output is selected to be interlaced and the input video signal initially exhibits a progressive format. So, initially the format converter operates to convert the progressive input format to the desired output interlaced format. The prefilter 54 in Figure 2 exhibits a processing delay of slightly more than one frame duration to convert from progressive to interlaced format. The magnitude of this delay is not ~ Critical, but it must be a fixed and known delay. Assume that while the converted interleaved signal is being transferred to the output multiplexer 60, the format of the input signal changed from progressive to interlace (which is the desired output format). This change is detected by the mode control network 70. This can be achieved by detecting a preceding circuit mode control signal such as the decoder 34 in Figure 2, or by detecting activity on the analog signal port (e.g. * ^ j in the case of the format converter 14 of Figure 2). The Control signal provided by the network 70 to the output multiplexer 60, indicates that this format change has occurred, causing the output multiplexer 60 to begin storing the new interlaced input video signal that is passed directly from the output to the input multiplexer 46 to the output multiplexer 60 via the Bypass Trajectory. The multiplexer 60 stores this signal ,? interlaced in a memory of the middle frame memo. The delay of the frame buffer allows the output multiplexer 60 to route the progressive video signal processed from the filter 54 in its entirety to the output digital-to-analog converter unit 62 for display, followed by the interleaved video deviated from the frame buffer. The seamless switching process described above is illustrated by the waveforms of Figure 3A for the case of provide an interlaced video output signal. The way of Wave A illustrates the position of the Frame Reference Pulse FR P '^ during the vertical blanking interval before the active video line scan interval. The interval between each FRP is a picture box in this example. In the waveform (B), the 5 pin-0 and the pin-1 represent progressive video input frames. These frames appear delayed in the output of the pre-filter 54 (Figure 2) as horizontal and vertical prefilter 1 (hvpre-1) and horizontal and vertical prefilter 0 (hvpre-O) of waveform data (C). After conversion to interlaced format, these frames * ^) respectively appear as output interlaced video iout-0 and iout-1 shown in wave form (E). In this example, the output video information iout-0 corresponds to the input box pin-0. The output video information iout-1 corresponds to the pin-1 progressive video input, and is the last frame converted from progressive-to-interlaced to appear before the input signal changes to interlaced format. In (1) in the Figure , 3A the output multiplexer 60 delays filtered data from the HVPRE by a few lines as will be explained in relation to Figure 4.

In (2) in Figure 3A the output multiplexer delays the information video in the path of Detour by 2 frames, as will also be discussed in relation to Figure 4. The input video signal changes to interlace format in a time TO. These new interlaced frames are labeled as iin-0 and iin-1 in the D-wave form. The interlaced video is submitted to a delay of two frames associated with the multiplexer output 60 as indicated above, resulting in ^ respectively iout-2 how is munstr? ^? The wave form E So, the deviated interlaced video appears at the output at time T1 and so on. In the interlaced video output shown as waveform (E), the interleaved data iout-2, which appear just after time T1 at a frame boundary, are the first output data of the new interlaced input video signal . From the time T1 forward, that is, from the first line of the next picture frame, the video lines They continue seamlessly without interruption. In the desired interlaced output signal (waveform E), an interlaced format is produced seamlessly from the iout-0 data to the iout-2 data, etc. , as the video input changes from progressive to interlaced format. The switching of a progressive format (form of wave B) to the interlaced format (waveform D) does not produce visible artifacts and is not noticed by an observer. The format transition occurs in a predetermined fixed amount of time (delay) after the appearance of the FRP to facilitate the seamless transition and avoid a discontinuity in an image displayed. Figure 3B illustrates the seamless switching process in the case of providing a progressive video output signal format. This is done in a manner analogous to that discussed with respect to Figure 3A for an interlaced output signal format. In the case of Figure 3B, a form of wave C associated with the output of de-interleaver 50 in the Figure u 2, and a waveform D associated with the output of the HV Post Filter 52 on the path lP in the sisterm ^ e Figure 2. The waveform D in Figure 3B is analogous to the C waveform in the Figure 3A. As in the case of Figure 3A, a delay of a few lines is indicated by (1) in Figure 3B, and (2) indicates that the progressive video of the Detour path is delayed by two frames by the output multiplexer 60. Similarly, the converted progressive data appears in the interval T0-T1, while the new progressive data starts at time T1. »Figure 4 shows details of the output multiplexer 60. A multiplexer 80 receives an interlaced video input signal from a first IF FO 82 buffer, a progressive video input signal from a second IF FO buffer. 86, and a progressive or interlaced video signal from a memory Intermediate frame 84. The interlaced video signals are provided to the memory 82 of the prefilter 54 (FIG. 2) in the conversion path Pl, the input video signals are provided directly to the frame buffer 84 of the multiplexer. input 46 (Figure 2), and the input signals from Progressive video is provided to the buffer 86 of the post filter 52 (Figure 2) in the conversion path l-P. The size of the buffers 82 and 86 is not critical, that is, several video lines. The buffers 82 and 86 are used to compensate for the associated different signal delays with three different input sources.

The frame buffer 84 receives data directly from the input multiplexer 60 in FIG. The buffer 84 exhibits a delay of two frames in this example. However, a delay of one frame can be used in accordance with the requirements of other systems. The output signals of the multiplexer 80 are passed to a digital-to-analog converter 62 (Figure 2) via the latch 90. In practice, the output multiplexer 60 in Figure 2 receives three Frame Reference Pulses (FRP), one of each of the ^ 5 filters 52 and 54 and another one of the input multiplexer 46. These pulses may be misaligned with each other by a few lines of image. The clock-to-data time may also be misaligned between three sources. Therefore, FI FO buffers are used to "clean up" any delay and misalignment of time before of the seamless switching operation associated with the multiplexer 80 in Figure 4. For this purpose, the buffers 82 and 84 exhibit a small delay of a few image lines to place processed data near a frame boundary to facilitate Seamless switching. The seamless format switching by the multiplexer 80 is facilitated by the read / write time measurement of the buffers 82, 84 and 86, and by the reference of the FRP pulses. For example, when the scan converter is in the conversion mode from progressive to interlaced, the data type clock to precede the buffer 82 (FI FO 1 WR CLK) is aligned with the clock! fs for the filter 54. The write clock for the frame buffer 84 (FB WR CLK) is aligned with the% fs clock for the input multiplexer 46. The data read clocks for the buffers 82 and 84 They are the same (RD CLK). The pulse FR P of the output multiplexer that referenced the pulse FRP of the input multiplexer. The output data from the buffer 82 and the frame buffer 84 are referenced to the same clock edge. Similar observations apply to buffers 84 and 86 when the * converter is in the interlace-to-progressive conversion mode. A unit 95 including a state machine (eg, a programmed microprocessor) and a logic network develops the read clock (RD CLK) and write clocks for buffers 82, 86 and 84 (FI FO 1 WR CLK, FI FO 2 WR CLK, and FB WR CLK respectively) in response to the interlace and progressive frame reference pulses l, P FRP, interlaced and progressive pixel clocks l, P 34 fs, and the control signal from the control network 70 in Figure 2. Unit 95 also produces a MUXSEL signal that is applied to a control input of the multiplexer 80. In response to this signal, the multiplexer 80 selects as its input either (a) the output of the buffer 82 or the output of the frame buffer 84, or (b) the output of the buffer 86 or the output of the frame buffer 84. The Multiplexer 80 selects between the two selections in (a) and the two selections in (b) in response to the control signal MUXSEL of the state machine 95, whose signal is at the same time developed in response to the Control signal of the network 70 in Figure 2. These control signals indicate which of the PI or lP conversions are present, or deflect the conditions ll or PP where no conversion will be made. An output FRP of the unit 95 is applied to the digital-to-analog converter 62 in Figure 2. In the case of digital input signals, the interlace and progressive frame reference pulses FRP (I) and FRP (P) are ^^ b provided from ancestor circuits, for example, the decoder 34 of FIG. 1 in the case of a receiver, for example. In the case of analog input signals R, G, B and H, V, the network 70 of Figure 1 may for example include a phase locked circuit (PLL) which responds to the component of analog input H synchronization to produce related input and output clocks. The input clock can be applied to a counter, a reset input from which it receives the # synchronization component V. The counter produces synchronization signals H and V as well as FRP (I) and FRP (P) signals at times certain suitable for use by the elements of the system of Figure 2. Although the invention has been described in the context of a high definition television system, the principles of the invention are applicable to other video signal processing systems such as standard definition television systems.

Claims (9)

Claims 1. In a system for processing a video signal s to display either a first image line scan format (I) or, alternatively a second different image line scan format (P), an apparatus including: a processor output compatible with a predetermined format of said first or second formats; an automatic scan format converter that? responds to said signals by displaying either said first or second formats to automatically provide an output signal with a predetermined format of the aforementioned first or second line scan formats in order to be compatible with the requirements of 15 format of such output processor; and characterized by a switching network associated with said converter exhibiting seamless switching between such first and
1. F second formats. 2. A system according to claim 1,
2. Characterized in that said converter comprises: a controlled output selection network having an input to receive a signal from a first path (conversion path P-1) to convert a signal displaying said first format to a signal exhibiting the 25 mentioned second format, an entry to receive a signal of a second path (IP conversion path) to convert a signal exhibiting such a second format to the first format, and an input to receive a signal with such a first or second format of a third path (deflection path) to pass a signal without format conversion; and a memory device in such a third path to pass signals to said third input of said selection network; wherein said memory device exhibits a delay that is significant in relation to an image frame interval.
3. 3. A system according to claim 2, characterized in that said memory device exhibits at least one image frame delay.
4. 4. A system according to claim 3, characterized in that said first and second trajectories exhibit a signal delay less than the delay of said memory device.
5. 5. A system according to claim 2, characterized in that said video signal is a television signal; said first format is an interlaced line scan format (I); and said second format is a non-interlaced sequential line sequential (P) scan format.
6. 6. A system according to claim 2, characterized in that said converter automatically converts the format of an input signal to said predetermined format if said input signal does not exhibit such predetermined format; and the converter passes an input signal without format conversion if said input signal exhibits said predetermined format.
7. 7. A system according to claim 2, characterized in that said system is a receiver system further comprising a decoding network coupled between a receiver input and such a format converter; and an image display device compatible with such 15 default line scan format.
8. 8. A system according to claim 2, characterized in that said memory device in the third path (Detour) exhibits, * at least, an image frame delay; Said first and second trajectories each include a storage device exhibiting a significantly shorter delay than said memory device in the third path; said frame memory device in such 25 third path and such a storage device in the first path are similarly synchronized in time to read data in a progressive to interlace scan conversion mode; and said frame memory device in such a third path and such storage device in the second path are similarly synchronized in time to read data in an interlace to progressive scan conversion mode.
9. 9. A system according to claim 8, * characterized in that such storage devices in such first and second paths exhibit a delay of a few image lines. *